0134f130e7
Extracting the common MI_* instructions that can be used with any engine to their own header will make it easier as we add additional engine instructions in upcoming patches. Also, since the majority of GPU instructions (both MI and non-MI) have a "length" field in bits 7:0 of the instruction header, a common define is added for that. Instruction-specific length fields are still defined for special case instructions that have larger/smaller length fields. v2: - Use "instr" instead of "inst" as the short form of "instruction" everywhere. (Lucas) - Include xe_reg_defs.h instead of the i915 compat header. (Lucas) Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://lore.kernel.org/r/20231016163449.1300701-12-matthew.d.roper@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
111 lines
2.4 KiB
C
111 lines
2.4 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#include "xe_bb.h"
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#include "instructions/xe_mi_commands.h"
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#include "regs/xe_gpu_commands.h"
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#include "xe_device.h"
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#include "xe_exec_queue_types.h"
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#include "xe_gt.h"
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#include "xe_hw_fence.h"
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#include "xe_sa.h"
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#include "xe_sched_job.h"
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#include "xe_vm_types.h"
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static int bb_prefetch(struct xe_gt *gt)
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{
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struct xe_device *xe = gt_to_xe(gt);
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if (GRAPHICS_VERx100(xe) >= 1250 && !xe_gt_is_media_type(gt))
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/*
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* RCS and CCS require 1K, although other engines would be
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* okay with 512.
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*/
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return SZ_1K;
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else
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return SZ_512;
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}
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struct xe_bb *xe_bb_new(struct xe_gt *gt, u32 dwords, bool usm)
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{
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struct xe_tile *tile = gt_to_tile(gt);
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struct xe_bb *bb = kmalloc(sizeof(*bb), GFP_KERNEL);
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int err;
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if (!bb)
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return ERR_PTR(-ENOMEM);
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/*
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* We need to allocate space for the requested number of dwords,
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* one additional MI_BATCH_BUFFER_END dword, and additional buffer
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* space to accomodate the platform-specific hardware prefetch
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* requirements.
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*/
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bb->bo = xe_sa_bo_new(!usm ? tile->mem.kernel_bb_pool : gt->usm.bb_pool,
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4 * (dwords + 1) + bb_prefetch(gt));
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if (IS_ERR(bb->bo)) {
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err = PTR_ERR(bb->bo);
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goto err;
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}
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bb->cs = xe_sa_bo_cpu_addr(bb->bo);
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bb->len = 0;
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return bb;
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err:
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kfree(bb);
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return ERR_PTR(err);
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}
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static struct xe_sched_job *
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__xe_bb_create_job(struct xe_exec_queue *q, struct xe_bb *bb, u64 *addr)
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{
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u32 size = drm_suballoc_size(bb->bo);
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bb->cs[bb->len++] = MI_BATCH_BUFFER_END;
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xe_gt_assert(q->gt, bb->len * 4 + bb_prefetch(q->gt) <= size);
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xe_sa_bo_flush_write(bb->bo);
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return xe_sched_job_create(q, addr);
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}
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struct xe_sched_job *xe_bb_create_migration_job(struct xe_exec_queue *q,
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struct xe_bb *bb,
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u64 batch_base_ofs,
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u32 second_idx)
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{
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u64 addr[2] = {
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batch_base_ofs + drm_suballoc_soffset(bb->bo),
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batch_base_ofs + drm_suballoc_soffset(bb->bo) +
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4 * second_idx,
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};
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xe_gt_assert(q->gt, second_idx <= bb->len);
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xe_gt_assert(q->gt, q->vm->flags & XE_VM_FLAG_MIGRATION);
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return __xe_bb_create_job(q, bb, addr);
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}
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struct xe_sched_job *xe_bb_create_job(struct xe_exec_queue *q,
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struct xe_bb *bb)
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{
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u64 addr = xe_sa_bo_gpu_addr(bb->bo);
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xe_gt_assert(q->gt, !(q->vm && q->vm->flags & XE_VM_FLAG_MIGRATION));
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return __xe_bb_create_job(q, bb, &addr);
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}
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void xe_bb_free(struct xe_bb *bb, struct dma_fence *fence)
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{
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if (!bb)
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return;
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xe_sa_bo_free(bb->bo, fence);
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kfree(bb);
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}
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