6db6e56065
Change all relevant DP controller related programming for YUV420 cases. Namely, change the pixel clock math to consider YUV420 and modify the MVID programming to consider YUV420. Changes in v2: - Move configuration control programming to a different commit - Slight code simplification - Add VSC SDP check when doing mode_pclk_khz division in dp_bridge_mode_valid Signed-off-by: Paloma Arellano <quic_parellan@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/579640/ Link: https://lore.kernel.org/r/20240222194025.25329-12-quic_parellan@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>