771ced73fc
[Why] Depend on res_pool->res_cap->num_timing_generator to query timing gernerator information, it would case underflow at the fused display pipes case. Due to the res_pool->res_cap->num_timing_generator records default timing generator resource built in driver, not the current chip. [How] Some ASICs would be fused display pipes less than the default setting. In dcnxx_resource_construct function, driver would obatin real timing generator count and store it into res_pool->timing_generator_count. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Yi-Ling Chen <Yi-Ling.Chen2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> |
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| drm | ||
| host1x | ||
| ipu-v3 | ||
| trace | ||
| vga | ||
| Makefile | ||