b3e0c5f734
Rework alternatives to allow for callbacks. With this every alternative entry has additional data encoded: - When (aka context) an alternative is supposed to be applied - The type of an alternative, which allows for type specific handling and callbacks - Extra type specific payload (patch information), which can be passed to callbacks in order to decide if an alternative should be applied or not With this only the "late" context is implemented, which means there is no change to the previous behaviour. All code is just converted to the more generic new infrastructure. Reviewed-by: Alexander Gordeev <agordeev@linux.ibm.com> Tested-by: Sven Schnelle <svens@linux.ibm.com> Signed-off-by: Heiko Carstens <hca@linux.ibm.com> Signed-off-by: Vasily Gorbik <gor@linux.ibm.com>
149 lines
3.3 KiB
C
149 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* S390 version
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* Copyright IBM Corp. 1999
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* Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
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*
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* Derived from "include/asm-i386/spinlock.h"
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*/
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#ifndef __ASM_SPINLOCK_H
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#define __ASM_SPINLOCK_H
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#include <linux/smp.h>
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#include <asm/atomic_ops.h>
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#include <asm/barrier.h>
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#include <asm/processor.h>
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#include <asm/alternative.h>
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#define SPINLOCK_LOCKVAL (get_lowcore()->spinlock_lockval)
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extern int spin_retry;
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bool arch_vcpu_is_preempted(int cpu);
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#define vcpu_is_preempted arch_vcpu_is_preempted
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/*
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* Simple spin lock operations. There are two variants, one clears IRQ's
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* on the local processor, one does not.
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*
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* We make no fairness assumptions. They have a cost.
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*
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* (the type definitions are in asm/spinlock_types.h)
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*/
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void arch_spin_relax(arch_spinlock_t *lock);
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#define arch_spin_relax arch_spin_relax
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void arch_spin_lock_wait(arch_spinlock_t *);
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int arch_spin_trylock_retry(arch_spinlock_t *);
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void arch_spin_lock_setup(int cpu);
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static inline u32 arch_spin_lockval(int cpu)
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{
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return cpu + 1;
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}
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static inline int arch_spin_value_unlocked(arch_spinlock_t lock)
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{
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return lock.lock == 0;
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}
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static inline int arch_spin_is_locked(arch_spinlock_t *lp)
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{
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return READ_ONCE(lp->lock) != 0;
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}
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static inline int arch_spin_trylock_once(arch_spinlock_t *lp)
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{
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barrier();
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return likely(__atomic_cmpxchg_bool(&lp->lock, 0, SPINLOCK_LOCKVAL));
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}
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static inline void arch_spin_lock(arch_spinlock_t *lp)
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{
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if (!arch_spin_trylock_once(lp))
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arch_spin_lock_wait(lp);
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}
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static inline int arch_spin_trylock(arch_spinlock_t *lp)
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{
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if (!arch_spin_trylock_once(lp))
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return arch_spin_trylock_retry(lp);
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return 1;
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}
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static inline void arch_spin_unlock(arch_spinlock_t *lp)
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{
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typecheck(int, lp->lock);
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kcsan_release();
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asm_inline volatile(
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ALTERNATIVE("nop", ".insn rre,0xb2fa0000,7,0", ALT_FACILITY(49)) /* NIAI 7 */
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" sth %1,%0\n"
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: "=R" (((unsigned short *) &lp->lock)[1])
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: "d" (0) : "cc", "memory");
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}
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/*
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* Read-write spinlocks, allowing multiple readers
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* but only one writer.
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*
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* NOTE! it is quite common to have readers in interrupts
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* but no interrupt writers. For those circumstances we
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* can "mix" irq-safe locks - any writer needs to get a
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* irq-safe write-lock, but readers can get non-irqsafe
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* read-locks.
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*/
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#define arch_read_relax(rw) barrier()
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#define arch_write_relax(rw) barrier()
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void arch_read_lock_wait(arch_rwlock_t *lp);
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void arch_write_lock_wait(arch_rwlock_t *lp);
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static inline void arch_read_lock(arch_rwlock_t *rw)
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{
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int old;
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old = __atomic_add(1, &rw->cnts);
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if (old & 0xffff0000)
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arch_read_lock_wait(rw);
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}
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static inline void arch_read_unlock(arch_rwlock_t *rw)
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{
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__atomic_add_const_barrier(-1, &rw->cnts);
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}
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static inline void arch_write_lock(arch_rwlock_t *rw)
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{
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if (!__atomic_cmpxchg_bool(&rw->cnts, 0, 0x30000))
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arch_write_lock_wait(rw);
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}
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static inline void arch_write_unlock(arch_rwlock_t *rw)
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{
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__atomic_add_barrier(-0x30000, &rw->cnts);
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}
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static inline int arch_read_trylock(arch_rwlock_t *rw)
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{
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int old;
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old = READ_ONCE(rw->cnts);
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return (!(old & 0xffff0000) &&
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__atomic_cmpxchg_bool(&rw->cnts, old, old + 1));
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}
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static inline int arch_write_trylock(arch_rwlock_t *rw)
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{
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int old;
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old = READ_ONCE(rw->cnts);
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return !old && __atomic_cmpxchg_bool(&rw->cnts, 0, 0x30000);
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}
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#endif /* __ASM_SPINLOCK_H */
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