6ccc971ee2
FEAT_NV has the interesting property of relying on ERET being trapped. An added complexity is that it also traps ERETAA and ERETAB, meaning that the Pointer Authentication aspect of these instruction must be emulated. Add an emulation of Pointer Authentication, limited to ERETAx (always using SP_EL2 as the modifier and ELR_EL2 as the pointer), using the Generic Authentication instructions. The emulation, however small, is placed in its own compilation unit so that it can be avoided if the configuration doesn't include it (or the toolchan in not up to the task). Reviewed-by: Joey Gouly <joey.gouly@arm.com> Reviewed-by: Oliver Upton <oliver.upton@linux.dev> Link: https://lore.kernel.org/r/20240419102935.1935571-13-maz@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org>
80 lines
2.0 KiB
C
80 lines
2.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ARM64_KVM_NESTED_H
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#define __ARM64_KVM_NESTED_H
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#include <linux/bitfield.h>
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#include <linux/kvm_host.h>
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#include <asm/kvm_emulate.h>
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static inline bool vcpu_has_nv(const struct kvm_vcpu *vcpu)
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{
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return (!__is_defined(__KVM_NVHE_HYPERVISOR__) &&
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cpus_have_final_cap(ARM64_HAS_NESTED_VIRT) &&
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vcpu_has_feature(vcpu, KVM_ARM_VCPU_HAS_EL2));
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}
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/* Translation helpers from non-VHE EL2 to EL1 */
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static inline u64 tcr_el2_ps_to_tcr_el1_ips(u64 tcr_el2)
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{
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return (u64)FIELD_GET(TCR_EL2_PS_MASK, tcr_el2) << TCR_IPS_SHIFT;
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}
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static inline u64 translate_tcr_el2_to_tcr_el1(u64 tcr)
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{
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return TCR_EPD1_MASK | /* disable TTBR1_EL1 */
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((tcr & TCR_EL2_TBI) ? TCR_TBI0 : 0) |
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tcr_el2_ps_to_tcr_el1_ips(tcr) |
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(tcr & TCR_EL2_TG0_MASK) |
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(tcr & TCR_EL2_ORGN0_MASK) |
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(tcr & TCR_EL2_IRGN0_MASK) |
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(tcr & TCR_EL2_T0SZ_MASK);
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}
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static inline u64 translate_cptr_el2_to_cpacr_el1(u64 cptr_el2)
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{
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u64 cpacr_el1 = 0;
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if (cptr_el2 & CPTR_EL2_TTA)
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cpacr_el1 |= CPACR_ELx_TTA;
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if (!(cptr_el2 & CPTR_EL2_TFP))
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cpacr_el1 |= CPACR_ELx_FPEN;
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if (!(cptr_el2 & CPTR_EL2_TZ))
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cpacr_el1 |= CPACR_ELx_ZEN;
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return cpacr_el1;
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}
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static inline u64 translate_sctlr_el2_to_sctlr_el1(u64 val)
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{
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/* Only preserve the minimal set of bits we support */
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val &= (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | SCTLR_ELx_SA |
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SCTLR_ELx_I | SCTLR_ELx_IESB | SCTLR_ELx_WXN | SCTLR_ELx_EE);
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val |= SCTLR_EL1_RES1;
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return val;
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}
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static inline u64 translate_ttbr0_el2_to_ttbr0_el1(u64 ttbr0)
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{
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/* Clear the ASID field */
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return ttbr0 & ~GENMASK_ULL(63, 48);
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}
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extern bool forward_smc_trap(struct kvm_vcpu *vcpu);
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int kvm_init_nv_sysregs(struct kvm *kvm);
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#ifdef CONFIG_ARM64_PTR_AUTH
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bool kvm_auth_eretax(struct kvm_vcpu *vcpu, u64 *elr);
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#else
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static inline bool kvm_auth_eretax(struct kvm_vcpu *vcpu, u64 *elr)
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{
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/* We really should never execute this... */
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WARN_ON_ONCE(1);
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*elr = 0xbad9acc0debadbad;
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return false;
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}
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#endif
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#endif /* __ARM64_KVM_NESTED_H */
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