Rodrigo Siqueira bdf4473394 drm/amd/display: Create patch bounding box function for isolate FPU ...

In the DCN30 resource, we have a small patch to the bounding box struct;
this patch uses FPU operations. This commit moves that specific part to
its function under the DML folder.

Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2022-07-25 17:16:20 -04:00

..

dcn30_afmt.c

drm/amd/display: Add VPG and AFMT low power support for DCN3.1

2021-09-14 15:57:11 -04:00

dcn30_afmt.h

drm/amd/display: Add VPG and AFMT low power support for DCN3.1

2021-09-14 15:57:11 -04:00

dcn30_cm_common.c

drm/amd/display: Correct algorithm for reversed gamma

2021-03-23 23:32:36 -04:00

dcn30_cm_common.h

drm/amd/display: Add DCN3 DPP

2020-07-01 01:59:14 -04:00

dcn30_dccg.c

drm/amd/display: Add interface for ADD & DROP PIXEL Registers

2021-06-08 12:22:42 -04:00

dcn30_dccg.h

drm/amd/display: Add interface for ADD & DROP PIXEL Registers

2021-06-08 12:22:42 -04:00

dcn30_dio_link_encoder.c

drm/amd/display: Add DP 2.0 BIOS and DMUB Support

2021-09-01 16:55:10 -04:00

dcn30_dio_link_encoder.h

drm/amd/display: add dcn30_link_encoder_validate_output_with_stream to header

2020-12-15 11:34:04 -05:00

dcn30_dio_stream_encoder.c

drm/amd/display: Program ACP related register

2022-07-05 16:13:18 -04:00

dcn30_dio_stream_encoder.h

drm/amd/display: Program ACP related register

2022-07-05 16:13:18 -04:00

dcn30_dpp_cm.c

drm/amd/display: add gamut coefficient set A and B

2022-03-15 14:25:15 -04:00

dcn30_dpp.c

drm/amd/display: Re-implementing ARGB16161616 pixel format as 22

2022-07-13 11:25:17 -04:00

dcn30_dpp.h

drm/amd/display: Add dependant changes for DCN32/321

2022-06-03 16:43:38 -04:00

dcn30_dwb_cm.c

drm/amd/display: fix incorrect CM/TF programming sequence in dwb

2021-08-09 15:43:10 -04:00

dcn30_dwb.c

drm/amd/display: Add DCN3 DWB

2020-07-01 01:59:14 -04:00

dcn30_dwb.h

drm/amd/display: Add DCN3 DWB

2020-07-01 01:59:14 -04:00

dcn30_hubbub.c

drm/amd/display: Add pstate verification and recovery for DCN31

2022-03-15 14:33:57 -04:00

dcn30_hubbub.h

drm/amd/display: log additional register state for debug

2021-07-21 13:39:25 -04:00

dcn30_hubp.c

drm/amd/display: implement dc_mode_memclk

2021-12-14 16:08:41 -05:00

dcn30_hubp.h

drm/amd/display: Add missing mask for DCN3

2021-04-09 16:53:05 -04:00

dcn30_hwseq.c

drm/amd/display: Add basic infrastructure for enabling FAMS

2022-07-05 16:12:00 -04:00

dcn30_hwseq.h

drm/amd/display: Firmware assisted MCLK switch and FS

2022-06-14 21:38:41 -04:00

dcn30_init.c

drm/amd/display: Firmware assisted MCLK switch and FS

2022-06-14 21:38:41 -04:00

dcn30_init.h

drm/amd/display: Init function tables for DCN3

2020-07-01 01:59:15 -04:00

dcn30_mmhubbub.c

drm/amd/display: fix function scopes

2021-12-13 16:34:26 -05:00

dcn30_mmhubbub.h

drm/amd/display: Add DCN3 MMHUBHUB

2020-07-01 01:59:14 -04:00

dcn30_mpc.c

drm/amd/display: Add dependant changes for DCN32/321

2022-06-03 16:43:38 -04:00

dcn30_mpc.h

drm/amd/display: Prepare for new interfaces

2022-07-05 16:10:45 -04:00

dcn30_opp.h

drm/amd/display: Add DCN3 OPP header

2020-07-01 01:59:14 -04:00

dcn30_optc.c

drm/amd/display: Make OPTC3 function accessible to other DCN

2022-07-05 16:11:54 -04:00

dcn30_optc.h

drm/amd/display: Add dependant changes for DCN32/321

2022-06-03 16:43:38 -04:00

dcn30_resource.c

drm/amd/display: Create patch bounding box function for isolate FPU

2022-07-25 17:16:20 -04:00

dcn30_resource.h

drm/amd/display: Move FPU associated DCN30 code to DML folder

2022-05-26 14:56:31 -04:00

dcn30_vpg.c

drm/amd/display: Fix issue with dynamic bpp change for DCN3x

2021-09-23 15:17:30 -04:00

dcn30_vpg.h

drm/amd/display: Fix issue with dynamic bpp change for DCN3x

2021-09-23 15:17:30 -04:00

Makefile

drm/amdgpu/display: make FP handling in Makefiles consistent

2022-06-14 21:38:41 -04:00