Dan Williams c1915142e8 tools/testing/cxl: Mock one level of switches ... The CXL port enumeration process adds intermediate CXL ports that are discovered between "root" CXL ports enumerated by 'cxl_acpi' and endpoints enumerated by 'cxl_pci + cxl_mem'. Test the dynamic discovery of intermediate switch ports in a CXL topology. Link: https://lore.kernel.org/r/164298432189.3018233.13142151550113000967.stgit@dwillia2-desk3.amr.corp.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>		2022-02-08 22:57:33 -08:00
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cxl	tools/testing/cxl: Mock one level of switches	2022-02-08 22:57:33 -08:00
fault-injection	…
ktest	bootconfig/tracing/ktest: Update ktest example for boot-time tracing	2021-08-16 11:39:51 -04:00
kunit	kunit: tool: Default --jobs to number of CPUs	2021-12-15 16:44:55 -07:00
nvdimm	memremap: remove support for external pgmap refcounts	2021-12-04 12:46:09 -08:00
radix-tree	tools: Fix math.h breakage	2021-11-30 09:14:42 -08:00
scatterlist	tools/testing/scatterlist: add missing defines	2022-01-30 09:56:58 +02:00
selftests	arm64 fixes:	2022-01-29 08:57:22 +02:00
vsock	vsock_diag_test: remove free_sock_stat() call in test_no_sockets	2021-10-15 17:21:34 -07:00