Files
linux/drivers
Imre Deak dada1a9ffc drm/i915: fix initial timestamps for PP sequencing logic
The initial jiffies value can be non-0, so set the inital panel power
sequencer timestamps accordingly. This didn't cause a problem on 64 bit
machines but on 32 bit jiffies is initially -300*HZ, so if the panel
power is initally off in the call from edp_panel_vdd_on()->
wait_panel_power_cycle() we'd wait up to ~300 sec more than needed.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-01-29 20:46:05 +01:00
..
2013-11-19 15:53:02 -05:00
2013-10-29 12:53:07 +02:00
2013-11-07 19:24:20 +01:00
2013-12-10 08:48:15 +01:00