Matthew Auld ea19684afb drm/i915/display: consider DG2_RC_CCS_CC when migrating buffers ... For these types of display buffers, we need to able to CPU access some part of the backing memory in prepare_plane_clear_colors(). As a result we need to ensure we always place in the mappable part of lmem, which becomes necessary on small-bar systems. v2(Nirmoy & Ville): - Add some commentary for why we need to CPU access the buffer. - Split out the other changes, so we just consider the display change here. v3: - Handle this in the dpt path. v4(Ville): - Drop the intel_fb_rc_ccs_cc_plane() sanity check in pin_and_fence_fb_obj(), since we can also trigger this on DG1 it seems. Fixes: eb1c535f0d ("drm/i915: turn on small BAR support") Reported-by: Jianshui Yu <jianshui.yu@intel.com> Signed-off-by: Matthew Auld <matthew.auld@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Nirmoy Das <nirmoy.das@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Acked-by: Nirmoy Das <nirmoy.das@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221004131916.233474-4-matthew.auld@intel.com (cherry picked from commit e3afc69018) Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>		2022-10-11 17:29:05 +01:00
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drm	drm/i915/display: consider DG2_RC_CCS_CC when migrating buffers	2022-10-11 17:29:05 +01:00
host1x	gpu: host1x: Use the bitmap API to allocate bitmaps	2022-07-08 17:38:34 +02:00
ipu-v3	…
trace	…
vga	…
Makefile	gpu: host1x: Add context bus	2022-06-01 11:50:42 +02:00