Hexagon requires that register predicates in assembly be parenthesized. Link: https://github.com/ClangBuiltLinux/linux/issues/754 Link: http://lkml.kernel.org/r/20191209222956.239798-3-ndesaulniers@google.com Signed-off-by: Nick Desaulniers <ndesaulniers@google.com> Suggested-by: Sid Manning <sidneym@codeaurora.org> Acked-by: Brian Cain <bcain@codeaurora.org> Cc: Lee Jones <lee.jones@linaro.org> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Tuowen Zhao <ztuowen@gmail.com> Cc: Mika Westerberg <mika.westerberg@linux.intel.com> Cc: Luis Chamberlain <mcgrof@kernel.org> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Alexios Zavras <alexios.zavras@intel.com> Cc: Allison Randal <allison@lohutok.net> Cc: Will Deacon <will@kernel.org> Cc: Richard Fontana <rfontana@redhat.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Boqun Feng <boqun.feng@gmail.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
109 lines
2.2 KiB
C
109 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_HEXAGON_FUTEX_H
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#define _ASM_HEXAGON_FUTEX_H
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#ifdef __KERNEL__
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#include <linux/futex.h>
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#include <linux/uaccess.h>
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#include <asm/errno.h>
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/* XXX TODO-- need to add sync barriers! */
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#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
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__asm__ __volatile( \
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"1: %0 = memw_locked(%3);\n" \
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/* For example: %1 = %4 */ \
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insn \
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"2: memw_locked(%3,p2) = %1;\n" \
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" if (!p2) jump 1b;\n" \
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" %1 = #0;\n" \
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"3:\n" \
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".section .fixup,\"ax\"\n" \
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"4: %1 = #%5;\n" \
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" jump 3b\n" \
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".previous\n" \
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".section __ex_table,\"a\"\n" \
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".long 1b,4b,2b,4b\n" \
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".previous\n" \
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: "=&r" (oldval), "=&r" (ret), "+m" (*uaddr) \
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: "r" (uaddr), "r" (oparg), "i" (-EFAULT) \
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: "p2", "memory")
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static inline int
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arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr)
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{
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int oldval = 0, ret;
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pagefault_disable();
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switch (op) {
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case FUTEX_OP_SET:
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__futex_atomic_op("%1 = %4\n", ret, oldval, uaddr, oparg);
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break;
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case FUTEX_OP_ADD:
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__futex_atomic_op("%1 = add(%0,%4)\n", ret, oldval, uaddr,
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oparg);
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break;
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case FUTEX_OP_OR:
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__futex_atomic_op("%1 = or(%0,%4)\n", ret, oldval, uaddr,
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oparg);
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break;
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case FUTEX_OP_ANDN:
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__futex_atomic_op("%1 = not(%4); %1 = and(%0,%1)\n", ret,
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oldval, uaddr, oparg);
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break;
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case FUTEX_OP_XOR:
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__futex_atomic_op("%1 = xor(%0,%4)\n", ret, oldval, uaddr,
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oparg);
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break;
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default:
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ret = -ENOSYS;
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}
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pagefault_enable();
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if (!ret)
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*oval = oldval;
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return ret;
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}
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static inline int
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futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, u32 oldval,
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u32 newval)
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{
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int prev;
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int ret;
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if (!access_ok(uaddr, sizeof(u32)))
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return -EFAULT;
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__asm__ __volatile__ (
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"1: %1 = memw_locked(%3)\n"
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" {\n"
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" p2 = cmp.eq(%1,%4)\n"
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" if (!p2.new) jump:NT 3f\n"
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" }\n"
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"2: memw_locked(%3,p2) = %5\n"
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" if (!p2) jump 1b\n"
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"3:\n"
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".section .fixup,\"ax\"\n"
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"4: %0 = #%6\n"
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" jump 3b\n"
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".previous\n"
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".section __ex_table,\"a\"\n"
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".long 1b,4b,2b,4b\n"
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".previous\n"
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: "+r" (ret), "=&r" (prev), "+m" (*uaddr)
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: "r" (uaddr), "r" (oldval), "r" (newval), "i"(-EFAULT)
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: "p2", "memory");
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*uval = prev;
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return ret;
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}
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#endif /* __KERNEL__ */
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#endif /* _ASM_HEXAGON_FUTEX_H */
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