6732c0e494
Legacy ARC700 processors (first generation of MMU enabled ARC cores) had VIPT cached which could be configured such that they could alias. Corresponding support in kernel (with all the obnoxious cache flush overhead) was added in ARC port 10 years ago to support 1 silicon. That is long bygone and we can let it RIP. Cc: Matthew Wilcox (Oracle) <willy@infradead.org> Signed-off-by: Vineet Gupta <vgupta@kernel.org>
69 lines
2.3 KiB
C
69 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* vineetg: May 2011: for Non-aliasing VIPT D-cache following can be NOPs
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* -flush_cache_dup_mm (fork)
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* -likewise for flush_cache_mm (exit/execve)
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* -likewise for flush_cache_{range,page} (munmap, exit, COW-break)
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*
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* vineetg: April 2008
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* -Added a critical CacheLine flush to copy_to_user_page( ) which
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* was causing gdbserver to not setup breakpoints consistently
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*/
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#ifndef _ASM_CACHEFLUSH_H
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#define _ASM_CACHEFLUSH_H
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#include <linux/mm.h>
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#include <asm/shmparam.h>
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void flush_cache_all(void);
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void flush_icache_range(unsigned long kstart, unsigned long kend);
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void __sync_icache_dcache(phys_addr_t paddr, unsigned long vaddr, int len);
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void __inv_icache_pages(phys_addr_t paddr, unsigned long vaddr, unsigned nr);
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void __flush_dcache_pages(phys_addr_t paddr, unsigned long vaddr, unsigned nr);
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
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void flush_dcache_page(struct page *page);
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void flush_dcache_folio(struct folio *folio);
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#define flush_dcache_folio flush_dcache_folio
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void dma_cache_wback_inv(phys_addr_t start, unsigned long sz);
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void dma_cache_inv(phys_addr_t start, unsigned long sz);
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void dma_cache_wback(phys_addr_t start, unsigned long sz);
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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/* TBD: optimize this */
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#define flush_cache_vmap(start, end) flush_cache_all()
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#define flush_cache_vunmap(start, end) flush_cache_all()
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#define flush_cache_dup_mm(mm) /* called on fork (VIVT only) */
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#define flush_cache_mm(mm) /* called on munmap/exit */
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#define flush_cache_range(mm, u_vstart, u_vend)
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#define flush_cache_page(vma, u_vaddr, pfn) /* PF handling/COW-break */
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/*
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* A new pagecache page has PG_arch_1 clear - thus dcache dirty by default
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* This works around some PIO based drivers which don't call flush_dcache_page
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* to record that they dirtied the dcache
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*/
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#define PG_dc_clean PG_arch_1
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#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
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do { \
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memcpy(dst, src, len); \
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if (vma->vm_flags & VM_EXEC) \
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__sync_icache_dcache((unsigned long)(dst), vaddr, len); \
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} while (0)
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
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memcpy(dst, src, len); \
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#endif
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