Horatiu Vultur d8ea7ff399 net: mscc: ocelot: Add support for MRP ... Add basic support for MRP. The HW will just trap all MRP frames on the ring ports to CPU and allow the SW to process them. In this way it is possible to for this node to behave both as MRM and MRC. Current limitations are: - it doesn't support Interconnect roles. - it supports only a single ring. - the HW should be able to do forwarding of MRP Test frames so the SW will not need to do this. So it would be able to have the role MRC without SW support. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>		2021-02-16 14:47:46 -08:00
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arc	include/: replace HTTP links with HTTPS ones	2020-08-12 10:57:59 -07:00
at91	ARM: at91: add atmel tcb capabilities	2020-07-11 18:57:03 +02:00
bcm2835	Revert "firmware: raspberrypi: Introduce vl805 init routine"	2020-08-18 13:01:11 +02:00
brcmstb	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500	2019-06-19 17:09:55 +02:00
fsl	ethernet: ucc_geth: remove bd_mem_part and all associated code	2021-01-21 12:19:56 -08:00
imx	ARM: imx: move cpu definitions into a header	2020-05-20 23:03:47 +08:00
mediatek	iommu/mediatek: Clean up struct mtk_smi_iommu	2019-08-30 15:57:27 +02:00
mscc	net: mscc: ocelot: Add support for MRP	2021-02-16 14:47:46 -08:00
qcom	It looks like a smaller batch of clk updates this time around. In the core	2020-08-07 13:35:51 -07:00
rockchip	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288	2019-06-05 17:36:37 +02:00
sa1100	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500	2019-06-19 17:09:55 +02:00
sifive	riscv: move sifive_l2_cache.h to include/soc	2020-01-12 10:12:44 -08:00
tegra	memory: tegra: Correct stub of devm_tegra_memory_controller_get()	2020-11-26 18:50:36 +01:00