Mario Kart 64
rcp.h
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1 #ifndef _RCP_H_
2 #define _RCP_H_
3 
4 /**************************************************************************
5  * *
6  * Copyright (C) 1995, Silicon Graphics, Inc. *
7  * *
8  * These coded instructions, statements, and computer programs contain *
9  * unpublished proprietary information of Silicon Graphics, Inc., and *
10  * are protected by Federal copyright law. They may not be disclosed *
11  * to third parties or copied or duplicated in any form, in whole or *
12  * in part, without the prior written consent of Silicon Graphics, Inc. *
13  * *
14  **************************************************************************/
15 
16 /**************************************************************************
17  *
18  * File: rcp.h
19  *
20  * This file contains register and bit definitions for RCP memory map.
21  * $Revision: 1.20 $
22  * $Date: 1997/07/23 08:35:21 $
23  * $Source: /disk6/Master/cvsmdev2/PR/include/rcp.h,v $
24  *
25  **************************************************************************/
26 
27 #include <PR/R4300.h>
28 #include <PR/ultratypes.h>
29 
30 /**********************************************************************
31  *
32  * Here is a quick overview of the RCP memory map:
33  *
34 
35 0x0000_0000 .. 0x03ef_ffff RDRAM memory
36 0x03f0_0000 .. 0x03ff_ffff RDRAM registers
37 
38  RCP registers (see below)
39 0x0400_0000 .. 0x040f_ffff SP registers
40 0x0410_0000 .. 0x041f_ffff DP command registers
41 0x0420_0000 .. 0x042f_ffff DP span registers
42 0x0430_0000 .. 0x043f_ffff MI registers
43 0x0440_0000 .. 0x044f_ffff VI registers
44 0x0450_0000 .. 0x045f_ffff AI registers
45 0x0460_0000 .. 0x046f_ffff PI registers
46 0x0470_0000 .. 0x047f_ffff RI registers
47 0x0480_0000 .. 0x048f_ffff SI registers
48 0x0490_0000 .. 0x04ff_ffff unused
49 
50 0x0500_0000 .. 0x05ff_ffff cartridge domain 2
51 0x0600_0000 .. 0x07ff_ffff cartridge domain 1
52 0x0800_0000 .. 0x0fff_ffff cartridge domain 2
53 0x1000_0000 .. 0x1fbf_ffff cartridge domain 1
54 
55 0x1fc0_0000 .. 0x1fc0_07bf PIF Boot Rom (1984 bytes)
56 0x1fc0_07c0 .. 0x1fc0_07ff PIF (JoyChannel) RAM (64 bytes)
57 0x1fc0_0800 .. 0x1fcf_ffff Reserved
58 0x1fd0_0000 .. 0x7fff_ffff cartridge domain 1
59 0x8000_0000 .. 0xffff_ffff external SysAD device
60 
61 The Indy development board use cartridge domain 1:
62 0x1000_0000 .. 0x10ff_ffff RAMROM
63 0x1800_0000 .. 0x1800_0003 GIO interrupt (6 bits valid in 4 bytes)
64 0x1800_0400 .. 0x1800_0403 GIO sync (6 bits valid in 4 bytes)
65 0x1800_0800 .. 0x1800_0803 CART interrupt (6 bits valid in 4 bytes)
66 
67 
68 
69 **************************************************************************/
70 
71 
72 /*************************************************************************
73  * RDRAM Memory (Assumes that maximum size is 4 MB)
74  */
75 #define RDRAM_0_START 0x00000000
76 #define RDRAM_0_END 0x001FFFFF
77 #define RDRAM_1_START 0x00200000
78 #define RDRAM_1_END 0x003FFFFF
79 
80 #define RDRAM_START RDRAM_0_START
81 #define RDRAM_END RDRAM_1_END
82 
83 
84 /*************************************************************************
85  * Address predicates
86  */
87 #if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
88 #define IS_RDRAM(x) ((unsigned)(x) >= RDRAM_START && \
89  (unsigned)(x) < RDRAM_END)
90 #endif
91 
92 
93 /*************************************************************************
94  * RDRAM Registers (0x03f0_0000 .. 0x03ff_ffff)
95  */
96 #define RDRAM_BASE_REG 0x03F00000
97 
98 #define RDRAM_CONFIG_REG (RDRAM_BASE_REG+0x00)
99 #define RDRAM_DEVICE_TYPE_REG (RDRAM_BASE_REG+0x00)
100 #define RDRAM_DEVICE_ID_REG (RDRAM_BASE_REG+0x04)
101 #define RDRAM_DELAY_REG (RDRAM_BASE_REG+0x08)
102 #define RDRAM_MODE_REG (RDRAM_BASE_REG+0x0c)
103 #define RDRAM_REF_INTERVAL_REG (RDRAM_BASE_REG+0x10)
104 #define RDRAM_REF_ROW_REG (RDRAM_BASE_REG+0x14)
105 #define RDRAM_RAS_INTERVAL_REG (RDRAM_BASE_REG+0x18)
106 #define RDRAM_MIN_INTERVAL_REG (RDRAM_BASE_REG+0x1c)
107 #define RDRAM_ADDR_SELECT_REG (RDRAM_BASE_REG+0x20)
108 #define RDRAM_DEVICE_MANUF_REG (RDRAM_BASE_REG+0x24)
109 
110 #define RDRAM_0_DEVICE_ID 0
111 #define RDRAM_1_DEVICE_ID 1
112 
113 #define RDRAM_RESET_MODE 0
114 #define RDRAM_ACTIVE_MODE 1
115 #define RDRAM_STANDBY_MODE 2
116 
117 #define RDRAM_LENGTH (2*512*2048)
118 #define RDRAM_0_BASE_ADDRESS (RDRAM_0_DEVICE_ID*RDRAM_LENGTH)
119 #define RDRAM_1_BASE_ADDRESS (RDRAM_1_DEVICE_ID*RDRAM_LENGTH)
120 
121 #define RDRAM_0_CONFIG 0x00000
122 #define RDRAM_1_CONFIG 0x00400
123 #define RDRAM_GLOBAL_CONFIG 0x80000
124 
125 
126 /*************************************************************************
127  * PIF Physical memory map (total size = 2 KB)
128  *
129  * Size Description Mode
130  * 1FC007FF +-------+-----------------+-----+
131  * | 64 B | JoyChannel RAM | R/W |
132  * 1FC007C0 +-------+-----------------+-----+
133  * |1984 B | Boot ROM | * | * = Reserved
134  * 1FC00000 +-------+-----------------+-----+
135  *
136  */
137 #define PIF_ROM_START 0x1FC00000
138 #define PIF_ROM_END 0x1FC007BF
139 #define PIF_RAM_START 0x1FC007C0
140 #define PIF_RAM_END 0x1FC007FF
141 
142 
143 /*************************************************************************
144  * Controller channel
145  * Each game controller channel has 4 error bits that are defined in bit 6-7 of
146  * the Rx and Tx data size area bytes. Programmers need to clear these bits
147  * when setting the Tx/Rx size area values for a channel
148  */
149 #define CHNL_ERR_NORESP 0x80 /* Bit 7 (Rx): No response error */
150 #define CHNL_ERR_OVERRUN 0x40 /* Bit 6 (Rx): Overrun error */
151 #define CHNL_ERR_FRAME 0x80 /* Bit 7 (Tx): Frame error */
152 #define CHNL_ERR_COLLISION 0x40 /* Bit 6 (Tx): Collision error */
153 
154 #define CHNL_ERR_MASK 0xC0 /* Bit 6-7: channel errors */
155 
156 
157 /*************************************************************************
158  * External device info
159  */
160 #define DEVICE_TYPE_CART 0 /* ROM cartridge */
161 #define DEVICE_TYPE_BULK 1 /* ROM bulk */
162 #define DEVICE_TYPE_64DD 2 /* 64 Disk Drive */
163 #define DEVICE_TYPE_SRAM 3 /* SRAM */
164 
165 /*************************************************************************
166  * SP Memory
167  */
168 #define SP_DMEM_START 0x04000000 /* read/write */
169 #define SP_DMEM_END 0x04000FFF
170 #define SP_IMEM_START 0x04001000 /* read/write */
171 #define SP_IMEM_END 0x04001FFF
172 
173 /*************************************************************************
174  * SP CP0 Registers
175  */
176 
177 #define SP_BASE_REG 0x04040000
178 
179 /* SP memory address (R/W): [11:0] DMEM/IMEM address; [12] 0=DMEM,1=IMEM */
180 #define SP_MEM_ADDR_REG (SP_BASE_REG+0x00) /* Master */
181 
182 /* SP DRAM DMA address (R/W): [23:0] RDRAM address */
183 #define SP_DRAM_ADDR_REG (SP_BASE_REG+0x04) /* Slave */
184 
185 /* SP read DMA length (R/W): [11:0] length, [19:12] count, [31:20] skip */
186 /* direction: I/DMEM <- RDRAM */
187 #define SP_RD_LEN_REG (SP_BASE_REG+0x08) /* R/W: read len */
188 
189 /* SP write DMA length (R/W): [11:0] length, [19:12] count, [31:20] skip */
190 /* direction: I/DMEM -> RDRAM */
191 #define SP_WR_LEN_REG (SP_BASE_REG+0x0C) /* R/W: write len */
192 
193 /* SP status (R/W): [14:0] valid bits; see below for write/read mode */
194 #define SP_STATUS_REG (SP_BASE_REG+0x10)
195 
196 /* SP DMA full (R): [0] valid bit; dma full */
197 #define SP_DMA_FULL_REG (SP_BASE_REG+0x14)
198 
199 /* SP DMA busy (R): [0] valid bit; dma busy */
200 #define SP_DMA_BUSY_REG (SP_BASE_REG+0x18)
201 
202 /* SP semaphore (R/W): Read: [0] semaphore flag (set on read) */
203 /* Write: [] clear semaphore flag */
204 #define SP_SEMAPHORE_REG (SP_BASE_REG+0x1C)
205 
206 /* SP PC (R/W): [11:0] program counter */
207 #define SP_PC_REG 0x04080000
208 
209 /* SP MEM address: bit 12 specifies if address is IMEM or DMEM */
210 #define SP_DMA_DMEM 0x0000 /* Bit 12: 0=DMEM, 1=IMEM */
211 #define SP_DMA_IMEM 0x1000 /* Bit 12: 0=DMEM, 1=IMEM */
212 
213 /*
214  * Values to clear/set bit in status reg (SP_STATUS_REG - write)
215  */
216 #define SP_CLR_HALT 0x00001 /* Bit 0: clear halt */
217 #define SP_SET_HALT 0x00002 /* Bit 1: set halt */
218 #define SP_CLR_BROKE 0x00004 /* Bit 2: clear broke */
219 #define SP_CLR_INTR 0x00008 /* Bit 3: clear intr */
220 #define SP_SET_INTR 0x00010 /* Bit 4: set intr */
221 #define SP_CLR_SSTEP 0x00020 /* Bit 5: clear sstep */
222 #define SP_SET_SSTEP 0x00040 /* Bit 6: set sstep */
223 #define SP_CLR_INTR_BREAK 0x00080 /* Bit 7: clear intr on break */
224 #define SP_SET_INTR_BREAK 0x00100 /* Bit 8: set intr on break */
225 #define SP_CLR_SIG0 0x00200 /* Bit 9: clear signal 0 */
226 #define SP_SET_SIG0 0x00400 /* Bit 10: set signal 0 */
227 #define SP_CLR_SIG1 0x00800 /* Bit 11: clear signal 1 */
228 #define SP_SET_SIG1 0x01000 /* Bit 12: set signal 1 */
229 #define SP_CLR_SIG2 0x02000 /* Bit 13: clear signal 2 */
230 #define SP_SET_SIG2 0x04000 /* Bit 14: set signal 2 */
231 #define SP_CLR_SIG3 0x08000 /* Bit 15: clear signal 3 */
232 #define SP_SET_SIG3 0x10000 /* Bit 16: set signal 3 */
233 #define SP_CLR_SIG4 0x20000 /* Bit 17: clear signal 4 */
234 #define SP_SET_SIG4 0x40000 /* Bit 18: set signal 4 */
235 #define SP_CLR_SIG5 0x80000 /* Bit 19: clear signal 5 */
236 #define SP_SET_SIG5 0x100000 /* Bit 20: set signal 5 */
237 #define SP_CLR_SIG6 0x200000 /* Bit 21: clear signal 6 */
238 #define SP_SET_SIG6 0x400000 /* Bit 22: set signal 6 */
239 #define SP_CLR_SIG7 0x800000 /* Bit 23: clear signal 7 */
240 #define SP_SET_SIG7 0x1000000 /* Bit 24: set signal 7 */
241 
242 /*
243  * Patterns to interpret status reg (SP_STATUS_REG - read)
244  */
245 #define SP_STATUS_HALT 0x001 /* Bit 0: halt */
246 #define SP_STATUS_BROKE 0x002 /* Bit 1: broke */
247 #define SP_STATUS_DMA_BUSY 0x004 /* Bit 2: dma busy */
248 #define SP_STATUS_DMA_FULL 0x008 /* Bit 3: dma full */
249 #define SP_STATUS_IO_FULL 0x010 /* Bit 4: io full */
250 #define SP_STATUS_SSTEP 0x020 /* Bit 5: single step */
251 #define SP_STATUS_INTR_BREAK 0x040 /* Bit 6: interrupt on break */
252 #define SP_STATUS_SIG0 0x080 /* Bit 7: signal 0 set */
253 #define SP_STATUS_SIG1 0x100 /* Bit 8: signal 1 set */
254 #define SP_STATUS_SIG2 0x200 /* Bit 9: signal 2 set */
255 #define SP_STATUS_SIG3 0x400 /* Bit 10: signal 3 set */
256 #define SP_STATUS_SIG4 0x800 /* Bit 11: signal 4 set */
257 #define SP_STATUS_SIG5 0x1000 /* Bit 12: signal 5 set */
258 #define SP_STATUS_SIG6 0x2000 /* Bit 13: signal 6 set */
259 #define SP_STATUS_SIG7 0x4000 /* Bit 14: signal 7 set */
260 
261 /*
262  * Use of SIG bits
263  */
264 #define SP_CLR_YIELD SP_CLR_SIG0
265 #define SP_SET_YIELD SP_SET_SIG0
266 #define SP_STATUS_YIELD SP_STATUS_SIG0
267 #define SP_CLR_YIELDED SP_CLR_SIG1
268 #define SP_SET_YIELDED SP_SET_SIG1
269 #define SP_STATUS_YIELDED SP_STATUS_SIG1
270 #define SP_CLR_TASKDONE SP_CLR_SIG2
271 #define SP_SET_TASKDONE SP_SET_SIG2
272 #define SP_STATUS_TASKDONE SP_STATUS_SIG2
273 #define SP_CLR_RSPSIGNAL SP_CLR_SIG3
274 #define SP_SET_RSPSIGNAL SP_SET_SIG3
275 #define SP_STATUS_RSPSIGNAL SP_STATUS_SIG3
276 #define SP_CLR_CPUSIGNAL SP_CLR_SIG4
277 #define SP_SET_CPUSIGNAL SP_SET_SIG4
278 #define SP_STATUS_CPUSIGNAL SP_STATUS_SIG4
279 
280 /* SP IMEM BIST REG (R/W): [6:0] BIST status bits; see below for detail */
281 #define SP_IBIST_REG 0x04080004
282 
283 /*
284  * Patterns to interpret status reg (SP_BIST_REG - write)
285  */
286 #define SP_IBIST_CHECK 0x01 /* Bit 0: BIST check */
287 #define SP_IBIST_GO 0x02 /* Bit 1: BIST go */
288 #define SP_IBIST_CLEAR 0x04 /* Bit 2: BIST clear */
289 
290 /*
291  * Patterns to interpret status reg (SP_BIST_REG - read)
292  */
293 /* First 2 bits are same as in write mode:
294  * Bit 0: BIST check; Bit 1: BIST go
295  */
296 #define SP_IBIST_DONE 0x04 /* Bit 2: BIST done */
297 #define SP_IBIST_FAILED 0x78 /* Bit [6:3]: BIST fail */
298 
299 
300 /*************************************************************************
301  * DP Command Registers
302  */
303 #define DPC_BASE_REG 0x04100000
304 
305 /* DP CMD DMA start (R/W): [23:0] DMEM/RDRAM start address */
306 #define DPC_START_REG (DPC_BASE_REG+0x00)
307 
308 /* DP CMD DMA end (R/W): [23:0] DMEM/RDRAM end address */
309 #define DPC_END_REG (DPC_BASE_REG+0x04)
310 
311 /* DP CMD DMA end (R): [23:0] DMEM/RDRAM current address */
312 #define DPC_CURRENT_REG (DPC_BASE_REG+0x08)
313 
314 /* DP CMD status (R/W): [9:0] valid bits - see below for definitions */
315 #define DPC_STATUS_REG (DPC_BASE_REG+0x0C)
316 
317 /* DP clock counter (R): [23:0] clock counter */
318 #define DPC_CLOCK_REG (DPC_BASE_REG+0x10)
319 
320 /* DP buffer busy counter (R): [23:0] clock counter */
321 #define DPC_BUFBUSY_REG (DPC_BASE_REG+0x14)
322 
323 /* DP pipe busy counter (R): [23:0] clock counter */
324 #define DPC_PIPEBUSY_REG (DPC_BASE_REG+0x18)
325 
326 /* DP TMEM load counter (R): [23:0] clock counter */
327 #define DPC_TMEM_REG (DPC_BASE_REG+0x1C)
328 
329 /*
330  * Values to clear/set bit in status reg (DPC_STATUS_REG - write)
331  */
332 #define DPC_CLR_XBUS_DMEM_DMA 0x0001 /* Bit 0: clear xbus_dmem_dma */
333 #define DPC_SET_XBUS_DMEM_DMA 0x0002 /* Bit 1: set xbus_dmem_dma */
334 #define DPC_CLR_FREEZE 0x0004 /* Bit 2: clear freeze */
335 #define DPC_SET_FREEZE 0x0008 /* Bit 3: set freeze */
336 #define DPC_CLR_FLUSH 0x0010 /* Bit 4: clear flush */
337 #define DPC_SET_FLUSH 0x0020 /* Bit 5: set flush */
338 #define DPC_CLR_TMEM_CTR 0x0040 /* Bit 6: clear tmem ctr */
339 #define DPC_CLR_PIPE_CTR 0x0080 /* Bit 7: clear pipe ctr */
340 #define DPC_CLR_CMD_CTR 0x0100 /* Bit 8: clear cmd ctr */
341 #define DPC_CLR_CLOCK_CTR 0x0200 /* Bit 9: clear clock ctr */
342 
343 /*
344  * Patterns to interpret status reg (DPC_STATUS_REG - read)
345  */
346 #define DPC_STATUS_XBUS_DMEM_DMA 0x001 /* Bit 0: xbus_dmem_dma */
347 #define DPC_STATUS_FREEZE 0x002 /* Bit 1: freeze */
348 #define DPC_STATUS_FLUSH 0x004 /* Bit 2: flush */
349 /*#define DPC_STATUS_FROZEN 0x008*/ /* Bit 3: frozen */
350 #define DPC_STATUS_START_GCLK 0x008 /* Bit 3: start gclk */
351 #define DPC_STATUS_TMEM_BUSY 0x010 /* Bit 4: tmem busy */
352 #define DPC_STATUS_PIPE_BUSY 0x020 /* Bit 5: pipe busy */
353 #define DPC_STATUS_CMD_BUSY 0x040 /* Bit 6: cmd busy */
354 #define DPC_STATUS_CBUF_READY 0x080 /* Bit 7: cbuf ready */
355 #define DPC_STATUS_DMA_BUSY 0x100 /* Bit 8: dma busy */
356 #define DPC_STATUS_END_VALID 0x200 /* Bit 9: end valid */
357 #define DPC_STATUS_START_VALID 0x400 /* Bit 10: start valid */
358 
359 
360 /*************************************************************************
361  * DP Span Registers
362  */
363 #define DPS_BASE_REG 0x04200000
364 
365 /* DP tmem bist (R/W): [10:0] BIST status bits; see below for detail */
366 #define DPS_TBIST_REG (DPS_BASE_REG+0x00)
367 
368 /* DP span test mode (R/W): [0] Span buffer test access enable */
369 #define DPS_TEST_MODE_REG (DPS_BASE_REG+0x04)
370 
371 /* DP span buffer test address (R/W): [6:0] bits; see below for detail */
372 #define DPS_BUFTEST_ADDR_REG (DPS_BASE_REG+0x08)
373 
374 /* DP span buffer test data (R/W): [31:0] span buffer data */
375 #define DPS_BUFTEST_DATA_REG (DPS_BASE_REG+0x0C)
376 
377 /*
378  * Patterns to interpret status reg (DPS_TMEM_BIST_REG - write)
379  */
380 #define DPS_TBIST_CHECK 0x01 /* Bit 0: BIST check */
381 #define DPS_TBIST_GO 0x02 /* Bit 1: BIST go */
382 #define DPS_TBIST_CLEAR 0x04 /* Bit 2: BIST clear */
383 
384 /*
385  * Patterns to interpret status reg (DPS_TMEM_BIST_REG - read)
386  */
387 /* First 2 bits are same as in write mode:
388  * Bit 0: BIST check; Bit 1: BIST go
389  */
390 #define DPS_TBIST_DONE 0x004 /* Bit 2: BIST done */
391 #define DPS_TBIST_FAILED 0x7F8 /* Bit [10:3]: BIST fail */
392 
393 
394 /*************************************************************************
395  * MIPS Interface (MI) Registers
396  */
397 #define MI_BASE_REG 0x04300000
398 
399 /*
400  * MI init mode (W): [6:0] init length, [7] clear init mode, [8] set init mode
401  * [9/10] clear/set ebus test mode, [11] clear DP interrupt
402  * (R): [6:0] init length, [7] init mode, [8] ebus test mode
403  */
404 #define MI_INIT_MODE_REG (MI_BASE_REG+0x00)
405 #define MI_MODE_REG MI_INIT_MODE_REG
406 
407 /*
408  * Values to clear/set bit in mode reg (MI_MODE_REG - write)
409  */
410 #define MI_CLR_INIT 0x0080 /* Bit 7: clear init mode */
411 #define MI_SET_INIT 0x0100 /* Bit 8: set init mode */
412 #define MI_CLR_EBUS 0x0200 /* Bit 9: clear ebus test */
413 #define MI_SET_EBUS 0x0400 /* Bit 10: set ebus test mode */
414 #define MI_CLR_DP_INTR 0x0800 /* Bit 11: clear dp interrupt */
415 #define MI_CLR_RDRAM 0x1000 /* Bit 12: clear RDRAM reg */
416 #define MI_SET_RDRAM 0x2000 /* Bit 13: set RDRAM reg mode */
417 
418 /*
419  * Patterns to interpret mode reg (MI_MODE_REG - read)
420  */
421 #define MI_MODE_INIT 0x0080 /* Bit 7: init mode */
422 #define MI_MODE_EBUS 0x0100 /* Bit 8: ebus test mode */
423 #define MI_MODE_RDRAM 0x0200 /* Bit 9: RDRAM reg mode */
424 
425 /* MI version (R): [7:0] io, [15:8] rac, [23:16] rdp, [31:24] rsp */
426 #define MI_VERSION_REG (MI_BASE_REG+0x04)
427 #define MI_NOOP_REG MI_VERSION_REG
428 
429 /* MI interrupt (R): [5:0] valid bits - see below for bit patterns */
430 #define MI_INTR_REG (MI_BASE_REG+0x08)
431 
432 /*
433  * MI interrupt mask (W): [11:0] valid bits - see below for bit patterns
434  * (R): [5:0] valid bits - see below for bit patterns
435  */
436 #define MI_INTR_MASK_REG (MI_BASE_REG+0x0C)
437 
438 /*
439  * The following are values to check for interrupt setting (MI_INTR_REG)
440  */
441 #define MI_INTR_SP 0x01 /* Bit 0: SP intr */
442 #define MI_INTR_SI 0x02 /* Bit 1: SI intr */
443 #define MI_INTR_AI 0x04 /* Bit 2: AI intr */
444 #define MI_INTR_VI 0x08 /* Bit 3: VI intr */
445 #define MI_INTR_PI 0x10 /* Bit 4: PI intr */
446 #define MI_INTR_DP 0x20 /* Bit 5: DP intr */
447 
448 /*
449  * The following are values to clear/set various interrupt bit mask
450  * They can be ORed together to manipulate multiple bits
451  * (MI_INTR_MASK_REG - write)
452  */
453 #define MI_INTR_MASK_CLR_SP 0x0001 /* Bit 0: clear SP mask */
454 #define MI_INTR_MASK_SET_SP 0x0002 /* Bit 1: set SP mask */
455 #define MI_INTR_MASK_CLR_SI 0x0004 /* Bit 2: clear SI mask */
456 #define MI_INTR_MASK_SET_SI 0x0008 /* Bit 3: set SI mask */
457 #define MI_INTR_MASK_CLR_AI 0x0010 /* Bit 4: clear AI mask */
458 #define MI_INTR_MASK_SET_AI 0x0020 /* Bit 5: set AI mask */
459 #define MI_INTR_MASK_CLR_VI 0x0040 /* Bit 6: clear VI mask */
460 #define MI_INTR_MASK_SET_VI 0x0080 /* Bit 7: set VI mask */
461 #define MI_INTR_MASK_CLR_PI 0x0100 /* Bit 8: clear PI mask */
462 #define MI_INTR_MASK_SET_PI 0x0200 /* Bit 9: set PI mask */
463 #define MI_INTR_MASK_CLR_DP 0x0400 /* Bit 10: clear DP mask */
464 #define MI_INTR_MASK_SET_DP 0x0800 /* Bit 11: set DP mask */
465 
466 /*
467  * The following are values to check for interrupt mask setting
468  * (MI_INTR_MASK_REG - read)
469  */
470 #define MI_INTR_MASK_SP 0x01 /* Bit 0: SP intr mask */
471 #define MI_INTR_MASK_SI 0x02 /* Bit 1: SI intr mask */
472 #define MI_INTR_MASK_AI 0x04 /* Bit 2: AI intr mask */
473 #define MI_INTR_MASK_VI 0x08 /* Bit 3: VI intr mask */
474 #define MI_INTR_MASK_PI 0x10 /* Bit 4: PI intr mask */
475 #define MI_INTR_MASK_DP 0x20 /* Bit 5: DP intr mask */
476 
477 
478 /*************************************************************************
479  * Video Interface (VI) Registers
480  */
481 #define VI_BASE_REG 0x04400000
482 
483 /* VI status/control (R/W): [15-0] valid bits:
484  * [1:0] = type[1:0] (pixel size)
485  * 0: blank (no data, no sync)
486  * 1: reserved
487  * 2: 5/5/5/3 ("16" bit)
488  * 3: 8/8/8/8 (32 bit)
489  * [2] = gamma_dither_enable (normally on, unless "special effect")
490  * [3] = gamma_enable (normally on, unless MPEG/JPEG)
491  * [4] = divot_enable (normally on if antialiased, unless decal lines)
492  * [5] = reserved - always off
493  * [6] = serrate (always on if interlaced, off if not)
494  * [7] = reserved - diagnostics only
495  * [9:8] = anti-alias (aa) mode[1:0]
496  * 0: aa & resamp (always fetch extra lines)
497  * 1: aa & resamp (fetch extra lines if needed)
498  * 2: resamp only (treat as all fully covered)
499  * 3: neither (replicate pixels, no interpolate)
500  * [11] = reserved - diagnostics only
501  * [15:12] = reserved
502  *
503  */
504 #define VI_STATUS_REG (VI_BASE_REG+0x00)
505 #define VI_CONTROL_REG VI_STATUS_REG
506 
507 /* VI origin (R/W): [23:0] frame buffer origin in bytes */
508 #define VI_ORIGIN_REG (VI_BASE_REG+0x04)
509 #define VI_DRAM_ADDR_REG VI_ORIGIN_REG
510 
511 /* VI width (R/W): [11:0] frame buffer line width in pixels */
512 #define VI_WIDTH_REG (VI_BASE_REG+0x08)
513 #define VI_H_WIDTH_REG VI_WIDTH_REG
514 
515 /* VI vertical intr (R/W): [9:0] interrupt when current half-line = V_INTR */
516 #define VI_INTR_REG (VI_BASE_REG+0x0C)
517 #define VI_V_INTR_REG VI_INTR_REG
518 
519 /*
520  * VI current vertical line (R/W): [9:0] current half line, sampled once per
521  * line (the lsb of V_CURRENT is constant within a field, and in
522  * interlaced modes gives the field number - which is constant for non-
523  * interlaced modes)
524  * - Any write to this register will clear interrupt line
525  */
526 #define VI_CURRENT_REG (VI_BASE_REG+0x10)
527 #define VI_V_CURRENT_LINE_REG VI_CURRENT_REG
528 
529 /*
530  * VI video timing (R/W): [ 7: 0] horizontal sync width in pixels,
531  * [15: 8] color burst width in pixels,
532  * [19:16] vertical sync width in half lines,
533  * [29:20] start of color burst in pixels from h-sync
534  */
535 #define VI_BURST_REG (VI_BASE_REG+0x14)
536 #define VI_TIMING_REG VI_BURST_REG
537 
538 /* VI vertical sync (R/W): [9:0] number of half-lines per field */
539 #define VI_V_SYNC_REG (VI_BASE_REG+0x18)
540 
541 /* VI horizontal sync (R/W): [11: 0] total duration of a line in 1/4 pixel
542  * [20:16] a 5-bit leap pattern used for PAL only
543  * (h_sync_period)
544  */
545 #define VI_H_SYNC_REG (VI_BASE_REG+0x1C)
546 
547 /*
548  * VI horizontal sync leap (R/W): [11: 0] identical to h_sync_period
549  * [27:16] identical to h_sync_period
550  */
551 #define VI_LEAP_REG (VI_BASE_REG+0x20)
552 #define VI_H_SYNC_LEAP_REG VI_LEAP_REG
553 
554 /*
555  * VI horizontal video (R/W): [ 9: 0] end of active video in screen pixels
556  * : [25:16] start of active video in screen pixels
557  */
558 #define VI_H_START_REG (VI_BASE_REG+0x24)
559 #define VI_H_VIDEO_REG VI_H_START_REG
560 
561 /*
562  * VI vertical video (R/W): [ 9: 0] end of active video in screen half-lines
563  * : [25:16] start of active video in screen half-lines
564  */
565 #define VI_V_START_REG (VI_BASE_REG+0x28)
566 #define VI_V_VIDEO_REG VI_V_START_REG
567 
568 /*
569  * VI vertical burst (R/W): [ 9: 0] end of color burst enable in half-lines
570  * : [25:16] start of color burst enable in half-lines
571  */
572 #define VI_V_BURST_REG (VI_BASE_REG+0x2C)
573 
574 /* VI x-scale (R/W): [11: 0] 1/horizontal scale up factor (2.10 format)
575  * [27:16] horizontal subpixel offset (2.10 format)
576  */
577 #define VI_X_SCALE_REG (VI_BASE_REG+0x30)
578 
579 /* VI y-scale (R/W): [11: 0] 1/vertical scale up factor (2.10 format)
580  * [27:16] vertical subpixel offset (2.10 format)
581  */
582 #define VI_Y_SCALE_REG (VI_BASE_REG+0x34)
583 
584 /*
585  * Patterns to interpret VI_CONTROL_REG
586  */
587 #define VI_CTRL_TYPE_16 0x00002 /* Bit [1:0] pixel size: 16 bit */
588 #define VI_CTRL_TYPE_32 0x00003 /* Bit [1:0] pixel size: 32 bit */
589 #define VI_CTRL_GAMMA_DITHER_ON 0x00004 /* Bit 2: default = on */
590 #define VI_CTRL_GAMMA_ON 0x00008 /* Bit 3: default = on */
591 #define VI_CTRL_DIVOT_ON 0x00010 /* Bit 4: default = on */
592 #define VI_CTRL_SERRATE_ON 0x00040 /* Bit 6: on if interlaced */
593 #define VI_CTRL_ANTIALIAS_MASK 0x00300 /* Bit [9:8] anti-alias mode */
594 #define VI_CTRL_DITHER_FILTER_ON 0x10000 /* Bit 16: dither-filter mode */
595 
596 /*
597  * Possible video clocks (NTSC or PAL)
598  */
599 #define VI_NTSC_CLOCK 48681812 /* Hz = 48.681812 MHz */
600 #define VI_PAL_CLOCK 49656530 /* Hz = 49.656530 MHz */
601 #define VI_MPAL_CLOCK 48628316 /* Hz = 48.628316 MHz */
602 
603 
604 /*************************************************************************
605  * Audio Interface (AI) Registers
606  *
607  * The address and length registers are double buffered; that is, they
608  * can be written twice before becoming full.
609  * The address must be written before the length.
610  */
611 #define AI_BASE_REG 0x04500000
612 
613 /* AI DRAM address (W): [23:0] starting RDRAM address (8B-aligned) */
614 #define AI_DRAM_ADDR_REG (AI_BASE_REG+0x00) /* R0: DRAM address */
615 
616 /* AI length (R/W): [14:0] transfer length (v1.0) - Bottom 3 bits are ignored */
617 /* [17:0] transfer length (v2.0) - Bottom 3 bits are ignored */
618 #define AI_LEN_REG (AI_BASE_REG+0x04) /* R1: Length */
619 
620 /* AI control (W): [0] DMA enable - if LSB == 1, DMA is enabled */
621 #define AI_CONTROL_REG (AI_BASE_REG+0x08) /* R2: DMA Control */
622 
623 /*
624  * AI status (R): [31]/[0] ai_full (addr & len buffer full), [30] ai_busy
625  * Note that a 1->0 transition in ai_full will set interrupt
626  * (W): clear audio interrupt
627  */
628 #define AI_STATUS_REG (AI_BASE_REG+0x0C) /* R3: Status */
629 
630 /*
631  * AI DAC sample period register (W): [13:0] dac rate
632  * - vid_clock/(dperiod + 1) is the DAC sample rate
633  * - (dperiod + 1) >= 66 * (aclockhp + 1) must be true
634  */
635 #define AI_DACRATE_REG (AI_BASE_REG+0x10) /* R4: DAC rate 14-lsb*/
636 
637 /*
638  * AI bit rate (W): [3:0] bit rate (abus clock half period register - aclockhp)
639  * - vid_clock/(2 * (aclockhp + 1)) is the DAC clock rate
640  * - The abus clock stops if aclockhp is zero
641  */
642 #define AI_BITRATE_REG (AI_BASE_REG+0x14) /* R5: Bit rate 4-lsb */
643 
644 /* Value for control register */
645 #define AI_CONTROL_DMA_ON 0x01 /* LSB = 1: DMA enable*/
646 #define AI_CONTROL_DMA_OFF 0x00 /* LSB = 1: DMA enable*/
647 
648 /* Value for status register */
649 #define AI_STATUS_FIFO_FULL 0x80000000 /* Bit 31: full */
650 #define AI_STATUS_DMA_BUSY 0x40000000 /* Bit 30: busy */
651 
652 /* DAC rate = video clock / audio frequency
653  * - DAC rate >= (66 * Bit rate) must be true
654  */
655 #define AI_MAX_DAC_RATE 16384 /* 14-bit+1 */
656 #define AI_MIN_DAC_RATE 132
657 
658 /* Bit rate <= (DAC rate / 66) */
659 #define AI_MAX_BIT_RATE 16 /* 4-bit+1 */
660 #define AI_MIN_BIT_RATE 2
661 
662 /*
663  * Maximum and minimum values for audio frequency based on video clocks
664  * max frequency = (video clock / min dac rate)
665  * min frequency = (video clock / max dac rate)
666  */
667 #define AI_NTSC_MAX_FREQ 368000 /* 368 KHz */
668 #define AI_NTSC_MIN_FREQ 3000 /* 3 KHz ~ 2971 Hz */
669 
670 #define AI_PAL_MAX_FREQ 376000 /* 376 KHz */
671 #define AI_PAL_MIN_FREQ 3050 /* 3 KHz ~ 3031 Hz */
672 
673 #define AI_MPAL_MAX_FREQ 368000 /* 368 KHz */
674 #define AI_MPAL_MIN_FREQ 3000 /* 3 KHz ~ 2968 Hz */
675 
676 
677 /*************************************************************************
678  * Peripheral Interface (PI) Registers
679  */
680 #define PI_BASE_REG 0x04600000
681 
682 /* PI DRAM address (R/W): [23:0] starting RDRAM address */
683 #define PI_DRAM_ADDR_REG (PI_BASE_REG+0x00) /* DRAM address */
684 
685 /* PI pbus (cartridge) address (R/W): [31:0] starting AD16 address */
686 #define PI_CART_ADDR_REG (PI_BASE_REG+0x04)
687 
688 /* PI read length (R/W): [23:0] read data length */
689 #define PI_RD_LEN_REG (PI_BASE_REG+0x08)
690 
691 /* PI write length (R/W): [23:0] write data length */
692 #define PI_WR_LEN_REG (PI_BASE_REG+0x0C)
693 
694 /*
695  * PI status (R): [0] DMA busy, [1] IO busy, [2], error
696  * (W): [0] reset controller (and abort current op), [1] clear intr
697  */
698 #define PI_STATUS_REG (PI_BASE_REG+0x10)
699 
700 /* PI dom1 latency (R/W): [7:0] domain 1 device latency */
701 #define PI_BSD_DOM1_LAT_REG (PI_BASE_REG+0x14)
702 
703 /* PI dom1 pulse width (R/W): [7:0] domain 1 device R/W strobe pulse width */
704 #define PI_BSD_DOM1_PWD_REG (PI_BASE_REG+0x18)
705 
706 /* PI dom1 page size (R/W): [3:0] domain 1 device page size */
707 #define PI_BSD_DOM1_PGS_REG (PI_BASE_REG+0x1C) /* page size */
708 
709 /* PI dom1 release (R/W): [1:0] domain 1 device R/W release duration */
710 #define PI_BSD_DOM1_RLS_REG (PI_BASE_REG+0x20)
711 
712 /* PI dom2 latency (R/W): [7:0] domain 2 device latency */
713 #define PI_BSD_DOM2_LAT_REG (PI_BASE_REG+0x24) /* Domain 2 latency */
714 
715 /* PI dom2 pulse width (R/W): [7:0] domain 2 device R/W strobe pulse width */
716 #define PI_BSD_DOM2_PWD_REG (PI_BASE_REG+0x28) /* pulse width */
717 
718 /* PI dom2 page size (R/W): [3:0] domain 2 device page size */
719 #define PI_BSD_DOM2_PGS_REG (PI_BASE_REG+0x2C) /* page size */
720 
721 /* PI dom2 release (R/W): [1:0] domain 2 device R/W release duration */
722 #define PI_BSD_DOM2_RLS_REG (PI_BASE_REG+0x30) /* release duration */
723 
724 #define PI_DOMAIN1_REG PI_BSD_DOM1_LAT_REG
725 #define PI_DOMAIN2_REG PI_BSD_DOM2_LAT_REG
726 
727 #define PI_DOM_LAT_OFS 0x00
728 #define PI_DOM_PWD_OFS 0x04
729 #define PI_DOM_PGS_OFS 0x08
730 #define PI_DOM_RLS_OFS 0x0C
731 
732 /*
733  * PI status register has 3 bits active when read from (PI_STATUS_REG - read)
734  * Bit 0: DMA busy - set when DMA is in progress
735  * Bit 1: IO busy - set when IO is in progress
736  * Bit 2: Error - set when CPU issues IO request while DMA is busy
737  */
738 #define PI_STATUS_ERROR 0x04
739 #define PI_STATUS_IO_BUSY 0x02
740 #define PI_STATUS_DMA_BUSY 0x01
741 
742 /* PI status register has 2 bits active when written to:
743  * Bit 0: When set, reset PIC
744  * Bit 1: When set, clear interrupt flag
745  * The values of the two bits can be ORed together to both reset PIC and
746  * clear interrupt at the same time.
747  *
748  * Note:
749  * - The PIC does generate an interrupt at the end of each DMA. CPU
750  * needs to clear the interrupt flag explicitly (from an interrupt
751  * handler) by writing into the STATUS register with bit 1 set.
752  *
753  * - When a DMA completes, the interrupt flag is set. CPU can issue
754  * another request even while the interrupt flag is set (as long as
755  * PIC is idle). However, it is the CPU's responsibility for
756  * maintaining accurate correspondence between DMA completions and
757  * interrupts.
758  *
759  * - When PIC is reset, if PIC happens to be busy, an interrupt will
760  * be generated as PIC returns to idle. Otherwise, no interrupt will
761  * be generated and PIC remains idle.
762  */
763 /*
764  * Values to clear interrupt/reset PIC (PI_STATUS_REG - write)
765  */
766 #define PI_STATUS_RESET 0x01
767 #define PI_SET_RESET PI_STATUS_RESET
768 
769 #define PI_STATUS_CLR_INTR 0x02
770 #define PI_CLR_INTR PI_STATUS_CLR_INTR
771 
772 #define PI_DMA_BUFFER_SIZE 128
773 
774 #define PI_DOM1_ADDR1 0x06000000 /* to 0x07FFFFFF */
775 #define PI_DOM1_ADDR2 0x10000000 /* to 0x1FBFFFFF */
776 #define PI_DOM1_ADDR3 0x1FD00000 /* to 0x7FFFFFFF */
777 #define PI_DOM2_ADDR1 0x05000000 /* to 0x05FFFFFF */
778 #define PI_DOM2_ADDR2 0x08000000 /* to 0x0FFFFFFF */
779 
780 
781 /*************************************************************************
782  * RDRAM Interface (RI) Registers
783  */
784 #define RI_BASE_REG 0x04700000
785 
786 /* RI mode (R/W): [1:0] operating mode, [2] stop T active, [3] stop R active */
787 #define RI_MODE_REG (RI_BASE_REG+0x00)
788 
789 /* RI config (R/W): [5:0] current control input, [6] current control enable */
790 #define RI_CONFIG_REG (RI_BASE_REG+0x04)
791 
792 /* RI current load (W): [] any write updates current control register */
793 #define RI_CURRENT_LOAD_REG (RI_BASE_REG+0x08)
794 
795 /* RI select (R/W): [2:0] receive select, [2:0] transmit select */
796 #define RI_SELECT_REG (RI_BASE_REG+0x0C)
797 
798 /* RI refresh (R/W): [7:0] clean refresh delay, [15:8] dirty refresh delay,
799  * [16] refresh bank, [17] refresh enable
800  * [18] refresh optimize
801  */
802 #define RI_REFRESH_REG (RI_BASE_REG+0x10)
803 #define RI_COUNT_REG RI_REFRESH_REG
804 
805 /* RI latency (R/W): [3:0] DMA latency/overlap */
806 #define RI_LATENCY_REG (RI_BASE_REG+0x14)
807 
808 /* RI error (R): [0] nack error, [1] ack error */
809 #define RI_RERROR_REG (RI_BASE_REG+0x18)
810 
811 /* RI error (W): [] any write clears all error bits */
812 #define RI_WERROR_REG (RI_BASE_REG+0x1C)
813 
814 
815 /*************************************************************************
816  * Serial Interface (SI) Registers
817  */
818 #define SI_BASE_REG 0x04800000
819 
820 /* SI DRAM address (R/W): [23:0] starting RDRAM address */
821 #define SI_DRAM_ADDR_REG (SI_BASE_REG+0x00) /* R0: DRAM address */
822 
823 /* SI address read 64B (W): [] any write causes a 64B DMA write */
824 #define SI_PIF_ADDR_RD64B_REG (SI_BASE_REG+0x04) /* R1: 64B PIF->DRAM */
825 
826 /* Address SI_BASE_REG + (0x08, 0x0c, 0x14) are reserved */
827 
828 /* SI address write 64B (W): [] any write causes a 64B DMA read */
829 #define SI_PIF_ADDR_WR64B_REG (SI_BASE_REG+0x10) /* R4: 64B DRAM->PIF */
830 
831 /*
832  * SI status (W): [] any write clears interrupt
833  * (R): [0] DMA busy, [1] IO read busy, [2] reserved
834  * [3] DMA error, [12] interrupt
835  */
836 #define SI_STATUS_REG (SI_BASE_REG+0x18) /* R6: Status */
837 
838 /* SI status register has the following bits active:
839  * 0: DMA busy - set when DMA is in progress
840  * 1: IO busy - set when IO access is in progress
841  * 3: DMA error - set when there are overlapping DMA requests
842  * 12: Interrupt - Interrupt set
843  */
844 #define SI_STATUS_DMA_BUSY 0x0001
845 #define SI_STATUS_RD_BUSY 0x0002
846 #define SI_STATUS_DMA_ERROR 0x0008
847 #define SI_STATUS_INTERRUPT 0x1000
848 
849 /*************************************************************************
850  * Development Board GIO Control Registers
851  */
852 
853 #define GIO_BASE_REG 0x18000000
854 
855 /* Game to Host Interrupt */
856 #define GIO_GIO_INTR_REG (GIO_BASE_REG+0x000)
857 
858 /* Game to Host SYNC */
859 #define GIO_GIO_SYNC_REG (GIO_BASE_REG+0x400)
860 
861 /* Host to Game Interrupt */
862 #define GIO_CART_INTR_REG (GIO_BASE_REG+0x800)
863 
864 
865 /*************************************************************************
866  * Common macros
867  */
868 #if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
869 #define IO_READ(addr) (*(vu32 *)PHYS_TO_K1(addr))
870 #define IO_WRITE(addr,data) (*(vu32 *)PHYS_TO_K1(addr)=(u32)(data))
871 #define RCP_STAT_PRINT \
872  rmonPrintf("current=%x start=%x end=%x dpstat=%x spstat=%x\n", \
873  IO_READ(DPC_CURRENT_REG), \
874  IO_READ(DPC_START_REG), \
875  IO_READ(DPC_END_REG), \
876  IO_READ(DPC_STATUS_REG), \
877  IO_READ(SP_STATUS_REG))
878 
879 #endif
880 
881 #endif /* _RCP_H_ */