mirror of
https://github.com/n64decomp/mk64
synced 2026-06-16 14:10:23 -04:00
MegaMech
553 lines
107 KiB
HTML
553 lines
107 KiB
HTML
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
|
<html xmlns="http://www.w3.org/1999/xhtml">
|
|
<head>
|
|
<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
|
|
<meta http-equiv="X-UA-Compatible" content="IE=9"/>
|
|
<meta name="generator" content="Doxygen 1.9.1"/>
|
|
<meta name="viewport" content="width=device-width, initial-scale=1"/>
|
|
<title>Mario Kart 64: include/PR/R4300.h Source File</title>
|
|
<link href="tabs.css" rel="stylesheet" type="text/css"/>
|
|
<script type="text/javascript" src="jquery.js"></script>
|
|
<script type="text/javascript" src="dynsections.js"></script>
|
|
<link href="navtree.css" rel="stylesheet" type="text/css"/>
|
|
<script type="text/javascript" src="resize.js"></script>
|
|
<script type="text/javascript" src="navtreedata.js"></script>
|
|
<script type="text/javascript" src="navtree.js"></script>
|
|
<link href="search/search.css" rel="stylesheet" type="text/css"/>
|
|
<script type="text/javascript" src="search/searchdata.js"></script>
|
|
<script type="text/javascript" src="search/search.js"></script>
|
|
<link href="doxygen.css" rel="stylesheet" type="text/css" />
|
|
</head>
|
|
<body>
|
|
<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
|
|
<div id="titlearea">
|
|
<table cellspacing="0" cellpadding="0">
|
|
<tbody>
|
|
<tr style="height: 56px;">
|
|
<td id="projectalign" style="padding-left: 0.5em;">
|
|
<div id="projectname">Mario Kart 64
|
|
</div>
|
|
</td>
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
</div>
|
|
<!-- end header part -->
|
|
<!-- Generated by Doxygen 1.9.1 -->
|
|
<script type="text/javascript">
|
|
/* @license magnet:?xt=urn:btih:cf05388f2679ee054f2beb29a391d25f4e673ac3&dn=gpl-2.0.txt GPL-v2 */
|
|
var searchBox = new SearchBox("searchBox", "search",false,'Search','.html');
|
|
/* @license-end */
|
|
</script>
|
|
<script type="text/javascript" src="menudata.js"></script>
|
|
<script type="text/javascript" src="menu.js"></script>
|
|
<script type="text/javascript">
|
|
/* @license magnet:?xt=urn:btih:cf05388f2679ee054f2beb29a391d25f4e673ac3&dn=gpl-2.0.txt GPL-v2 */
|
|
$(function() {
|
|
initMenu('',true,false,'search.php','Search');
|
|
$(document).ready(function() { init_search(); });
|
|
});
|
|
/* @license-end */</script>
|
|
<div id="main-nav"></div>
|
|
</div><!-- top -->
|
|
<div id="side-nav" class="ui-resizable side-nav-resizable">
|
|
<div id="nav-tree">
|
|
<div id="nav-tree-contents">
|
|
<div id="nav-sync" class="sync"></div>
|
|
</div>
|
|
</div>
|
|
<div id="splitbar" style="-moz-user-select:none;"
|
|
class="ui-resizable-handle">
|
|
</div>
|
|
</div>
|
|
<script type="text/javascript">
|
|
/* @license magnet:?xt=urn:btih:cf05388f2679ee054f2beb29a391d25f4e673ac3&dn=gpl-2.0.txt GPL-v2 */
|
|
$(document).ready(function(){initNavTree('R4300_8h_source.html',''); initResizable(); });
|
|
/* @license-end */
|
|
</script>
|
|
<div id="doc-content">
|
|
<!-- window showing the filter options -->
|
|
<div id="MSearchSelectWindow"
|
|
onmouseover="return searchBox.OnSearchSelectShow()"
|
|
onmouseout="return searchBox.OnSearchSelectHide()"
|
|
onkeydown="return searchBox.OnSearchSelectKey(event)">
|
|
</div>
|
|
|
|
<!-- iframe showing the search results (closed by default) -->
|
|
<div id="MSearchResultsWindow">
|
|
<iframe src="javascript:void(0)" frameborder="0"
|
|
name="MSearchResults" id="MSearchResults">
|
|
</iframe>
|
|
</div>
|
|
|
|
<div class="header">
|
|
<div class="headertitle">
|
|
<div class="title">R4300.h</div> </div>
|
|
</div><!--header-->
|
|
<div class="contents">
|
|
<a href="R4300_8h.html">Go to the documentation of this file.</a><div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno"> 1</span> <span class="comment">/**************************************************************************</span></div>
|
|
<div class="line"><a name="l00002"></a><span class="lineno"> 2</span> <span class="comment"> * *</span></div>
|
|
<div class="line"><a name="l00003"></a><span class="lineno"> 3</span> <span class="comment"> * Copyright (C) 1995, Silicon Graphics, Inc. *</span></div>
|
|
<div class="line"><a name="l00004"></a><span class="lineno"> 4</span> <span class="comment"> * *</span></div>
|
|
<div class="line"><a name="l00005"></a><span class="lineno"> 5</span> <span class="comment"> * These coded instructions, statements, and computer programs contain *</span></div>
|
|
<div class="line"><a name="l00006"></a><span class="lineno"> 6</span> <span class="comment"> * unpublished proprietary information of Silicon Graphics, Inc., and *</span></div>
|
|
<div class="line"><a name="l00007"></a><span class="lineno"> 7</span> <span class="comment"> * are protected by Federal copyright law. They may not be disclosed *</span></div>
|
|
<div class="line"><a name="l00008"></a><span class="lineno"> 8</span> <span class="comment"> * to third parties or copied or duplicated in any form, in whole or *</span></div>
|
|
<div class="line"><a name="l00009"></a><span class="lineno"> 9</span> <span class="comment"> * in part, without the prior written consent of Silicon Graphics, Inc. *</span></div>
|
|
<div class="line"><a name="l00010"></a><span class="lineno"> 10</span> <span class="comment"> * *</span></div>
|
|
<div class="line"><a name="l00011"></a><span class="lineno"> 11</span> <span class="comment"> **************************************************************************/</span></div>
|
|
<div class="line"><a name="l00012"></a><span class="lineno"> 12</span>  </div>
|
|
<div class="line"><a name="l00013"></a><span class="lineno"> 13</span> <span class="comment">/**************************************************************************</span></div>
|
|
<div class="line"><a name="l00014"></a><span class="lineno"> 14</span> <span class="comment"> *</span></div>
|
|
<div class="line"><a name="l00015"></a><span class="lineno"> 15</span> <span class="comment"> * $Revision: 1.13 $</span></div>
|
|
<div class="line"><a name="l00016"></a><span class="lineno"> 16</span> <span class="comment"> * $Date: 1997/02/11 08:15:34 $</span></div>
|
|
<div class="line"><a name="l00017"></a><span class="lineno"> 17</span> <span class="comment"> * $Source: /disk6/Master/cvsmdev2/PR/include/R4300.h,v $</span></div>
|
|
<div class="line"><a name="l00018"></a><span class="lineno"> 18</span> <span class="comment"> *</span></div>
|
|
<div class="line"><a name="l00019"></a><span class="lineno"> 19</span> <span class="comment"> **************************************************************************/</span></div>
|
|
<div class="line"><a name="l00020"></a><span class="lineno"> 20</span>  </div>
|
|
<div class="line"><a name="l00021"></a><span class="lineno"> 21</span> <span class="preprocessor">#ifndef __R4300_H__</span></div>
|
|
<div class="line"><a name="l00022"></a><span class="lineno"> 22</span> <span class="preprocessor">#define __R4300_H__</span></div>
|
|
<div class="line"><a name="l00023"></a><span class="lineno"> 23</span>  </div>
|
|
<div class="line"><a name="l00024"></a><span class="lineno"> 24</span> <span class="preprocessor">#include <<a class="code" href="ultratypes_8h.html">PR/ultratypes.h</a>></span></div>
|
|
<div class="line"><a name="l00025"></a><span class="lineno"> 25</span>  </div>
|
|
<div class="line"><a name="l00026"></a><span class="lineno"> 26</span> <span class="comment">/*</span></div>
|
|
<div class="line"><a name="l00027"></a><span class="lineno"> 27</span> <span class="comment"> * Segment base addresses and sizes</span></div>
|
|
<div class="line"><a name="l00028"></a><span class="lineno"> 28</span> <span class="comment"> */</span></div>
|
|
<div class="line"><a name="l00029"></a><span class="lineno"><a class="line" href="R4300_8h.html#a921a56ca8fba91ce2c187522eb4fa304"> 29</a></span> <span class="preprocessor">#define KUBASE 0</span></div>
|
|
<div class="line"><a name="l00030"></a><span class="lineno"><a class="line" href="R4300_8h.html#a2e400dd26a1afa6e6955b38a23870a8d"> 30</a></span> <span class="preprocessor">#define KUSIZE 0x80000000</span></div>
|
|
<div class="line"><a name="l00031"></a><span class="lineno"><a class="line" href="R4300_8h.html#a3895dc73e1b9343e0a0fd61037f0f887"> 31</a></span> <span class="preprocessor">#define K0BASE 0x80000000</span></div>
|
|
<div class="line"><a name="l00032"></a><span class="lineno"><a class="line" href="R4300_8h.html#afde3fc42d1d3dcf891cadcdb590f8d4b"> 32</a></span> <span class="preprocessor">#define K0SIZE 0x20000000</span></div>
|
|
<div class="line"><a name="l00033"></a><span class="lineno"><a class="line" href="R4300_8h.html#a6633ac67351b3315b65209bd155aa0e2"> 33</a></span> <span class="preprocessor">#define K1BASE 0xA0000000</span></div>
|
|
<div class="line"><a name="l00034"></a><span class="lineno"><a class="line" href="R4300_8h.html#ae7d4257f7050069d35a6e940c45caf12"> 34</a></span> <span class="preprocessor">#define K1SIZE 0x20000000</span></div>
|
|
<div class="line"><a name="l00035"></a><span class="lineno"><a class="line" href="R4300_8h.html#ace9d54246e55a11994c6e3ebe8aff525"> 35</a></span> <span class="preprocessor">#define K2BASE 0xC0000000</span></div>
|
|
<div class="line"><a name="l00036"></a><span class="lineno"><a class="line" href="R4300_8h.html#a6391ea25e673fbb03ac9b5f6337eece7"> 36</a></span> <span class="preprocessor">#define K2SIZE 0x20000000</span></div>
|
|
<div class="line"><a name="l00037"></a><span class="lineno"> 37</span>  </div>
|
|
<div class="line"><a name="l00038"></a><span class="lineno"> 38</span> <span class="comment">/*</span></div>
|
|
<div class="line"><a name="l00039"></a><span class="lineno"> 39</span> <span class="comment"> * Exception vectors</span></div>
|
|
<div class="line"><a name="l00040"></a><span class="lineno"> 40</span> <span class="comment"> */</span></div>
|
|
<div class="line"><a name="l00041"></a><span class="lineno"><a class="line" href="R4300_8h.html#a572047e589d5e539d13ae267bdb91446"> 41</a></span> <span class="preprocessor">#define SIZE_EXCVEC 0x80 </span><span class="comment">/* Size of an exc. vec */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00042"></a><span class="lineno"><a class="line" href="R4300_8h.html#a744b72afff2809906b8c3bf2d5f8f3e5"> 42</a></span> <span class="preprocessor">#define UT_VEC K0BASE </span><span class="comment">/* utlbmiss vector */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00043"></a><span class="lineno"><a class="line" href="R4300_8h.html#a1dc3e3c31c6b117b22818c5dc1391e73"> 43</a></span> <span class="preprocessor">#define R_VEC (K1BASE+0x1fc00000) </span><span class="comment">/* reset vector */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00044"></a><span class="lineno"><a class="line" href="R4300_8h.html#a1288557520f0c6731ec24c82c4afd420"> 44</a></span> <span class="preprocessor">#define XUT_VEC (K0BASE+0x80) </span><span class="comment">/* extended address tlbmiss */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00045"></a><span class="lineno"><a class="line" href="R4300_8h.html#acef472a5500a6295e6e36826a5df5bbb"> 45</a></span> <span class="preprocessor">#define ECC_VEC (K0BASE+0x100) </span><span class="comment">/* Ecc exception vector */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00046"></a><span class="lineno"><a class="line" href="R4300_8h.html#a7ed80f2d449e9df3e693fb6fe675b39a"> 46</a></span> <span class="preprocessor">#define E_VEC (K0BASE+0x180) </span><span class="comment">/* Gen. exception vector */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00047"></a><span class="lineno"> 47</span>  </div>
|
|
<div class="line"><a name="l00048"></a><span class="lineno"> 48</span> <span class="comment">/*</span></div>
|
|
<div class="line"><a name="l00049"></a><span class="lineno"> 49</span> <span class="comment"> * Address conversion macros</span></div>
|
|
<div class="line"><a name="l00050"></a><span class="lineno"> 50</span> <span class="comment"> */</span></div>
|
|
<div class="line"><a name="l00051"></a><span class="lineno"> 51</span> <span class="preprocessor">#ifdef _LANGUAGE_ASSEMBLY</span></div>
|
|
<div class="line"><a name="l00052"></a><span class="lineno"> 52</span>  </div>
|
|
<div class="line"><a name="l00053"></a><span class="lineno"> 53</span> <span class="preprocessor">#define K0_TO_K1(x) ((x)|0xA0000000) </span><span class="comment">/* kseg0 to kseg1 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00054"></a><span class="lineno"> 54</span> <span class="preprocessor">#define K1_TO_K0(x) ((x)&0x9FFFFFFF) </span><span class="comment">/* kseg1 to kseg0 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00055"></a><span class="lineno"> 55</span> <span class="preprocessor">#define K0_TO_PHYS(x) ((x)&0x1FFFFFFF) </span><span class="comment">/* kseg0 to physical */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00056"></a><span class="lineno"> 56</span> <span class="preprocessor">#define K1_TO_PHYS(x) ((x)&0x1FFFFFFF) </span><span class="comment">/* kseg1 to physical */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00057"></a><span class="lineno"> 57</span> <span class="preprocessor">#define KDM_TO_PHYS(x) ((x)&0x1FFFFFFF) </span><span class="comment">/* direct mapped to physical */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00058"></a><span class="lineno"> 58</span> <span class="preprocessor">#define PHYS_TO_K0(x) ((x)|0x80000000) </span><span class="comment">/* physical to kseg0 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00059"></a><span class="lineno"> 59</span> <span class="preprocessor">#define PHYS_TO_K1(x) ((x)|0xA0000000) </span><span class="comment">/* physical to kseg1 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00060"></a><span class="lineno"> 60</span>  </div>
|
|
<div class="line"><a name="l00061"></a><span class="lineno"> 61</span> <span class="preprocessor">#else </span><span class="comment">/* _LANGUAGE_C */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00062"></a><span class="lineno"> 62</span>  </div>
|
|
<div class="line"><a name="l00063"></a><span class="lineno"><a class="line" href="R4300_8h.html#a5ae3334c23012184175345172a0cac1e"> 63</a></span> <span class="preprocessor">#define K0_TO_K1(x) ((u32)(x)|0xA0000000) </span><span class="comment">/* kseg0 to kseg1 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00064"></a><span class="lineno"><a class="line" href="R4300_8h.html#ac3f97b9e95436eb2cd9bf16c8633a230"> 64</a></span> <span class="preprocessor">#define K1_TO_K0(x) ((u32)(x)&0x9FFFFFFF) </span><span class="comment">/* kseg1 to kseg0 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00065"></a><span class="lineno"><a class="line" href="R4300_8h.html#a316c03632d14d84593e9908e473f565e"> 65</a></span> <span class="preprocessor">#define K0_TO_PHYS(x) ((u32)(x)&0x1FFFFFFF) </span><span class="comment">/* kseg0 to physical */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00066"></a><span class="lineno"><a class="line" href="R4300_8h.html#abbba41e07fa4ca0fed97fdeb7185d6ec"> 66</a></span> <span class="preprocessor">#define K1_TO_PHYS(x) ((u32)(x)&0x1FFFFFFF) </span><span class="comment">/* kseg1 to physical */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00067"></a><span class="lineno"><a class="line" href="R4300_8h.html#aad51d21ac47be2f4f39b0a561f61d40c"> 67</a></span> <span class="preprocessor">#define KDM_TO_PHYS(x) ((u32)(x)&0x1FFFFFFF) </span><span class="comment">/* direct mapped to physical */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00068"></a><span class="lineno"><a class="line" href="R4300_8h.html#a60b733c1eb80b686609ce3d9024d7770"> 68</a></span> <span class="preprocessor">#define PHYS_TO_K0(x) ((u32)(x)|0x80000000) </span><span class="comment">/* physical to kseg0 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00069"></a><span class="lineno"><a class="line" href="R4300_8h.html#a3a3f158c25a6f29485d6d493fee38229"> 69</a></span> <span class="preprocessor">#define PHYS_TO_K1(x) ((u32)(x)|0xA0000000) </span><span class="comment">/* physical to kseg1 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00070"></a><span class="lineno"> 70</span>  </div>
|
|
<div class="line"><a name="l00071"></a><span class="lineno"> 71</span> <span class="preprocessor">#endif </span><span class="comment">/* _LANGUAGE_ASSEMBLY */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00072"></a><span class="lineno"> 72</span>  </div>
|
|
<div class="line"><a name="l00073"></a><span class="lineno"> 73</span> <span class="comment">/*</span></div>
|
|
<div class="line"><a name="l00074"></a><span class="lineno"> 74</span> <span class="comment"> * Address predicates</span></div>
|
|
<div class="line"><a name="l00075"></a><span class="lineno"> 75</span> <span class="comment"> */</span></div>
|
|
<div class="line"><a name="l00076"></a><span class="lineno"><a class="line" href="R4300_8h.html#adbd827f7d78b02d483bd814f56d78c38"> 76</a></span> <span class="preprocessor">#define IS_KSEG0(x) ((u32)(x) >= K0BASE && (u32)(x) < K1BASE)</span></div>
|
|
<div class="line"><a name="l00077"></a><span class="lineno"><a class="line" href="R4300_8h.html#a1f86a77a2d3e751c79cd446d2dee3fe8"> 77</a></span> <span class="preprocessor">#define IS_KSEG1(x) ((u32)(x) >= K1BASE && (u32)(x) < K2BASE)</span></div>
|
|
<div class="line"><a name="l00078"></a><span class="lineno"><a class="line" href="R4300_8h.html#a274e7c06ec9f2be2cdea1f1543df461f"> 78</a></span> <span class="preprocessor">#define IS_KSEGDM(x) ((u32)(x) >= K0BASE && (u32)(x) < K2BASE)</span></div>
|
|
<div class="line"><a name="l00079"></a><span class="lineno"><a class="line" href="R4300_8h.html#a5aac74bad20bdb41bec005498a7b4d4a"> 79</a></span> <span class="preprocessor">#define IS_KSEG2(x) ((u32)(x) >= K2BASE && (u32)(x) < KPTE_SHDUBASE)</span></div>
|
|
<div class="line"><a name="l00080"></a><span class="lineno"><a class="line" href="R4300_8h.html#a5294e651c6c49474993588a7a99d866d"> 80</a></span> <span class="preprocessor">#define IS_KPTESEG(x) ((u32)(x) >= KPTE_SHDUBASE)</span></div>
|
|
<div class="line"><a name="l00081"></a><span class="lineno"><a class="line" href="R4300_8h.html#a38e0c2a71d6888ac2c9e0067c8897ec9"> 81</a></span> <span class="preprocessor">#define IS_KUSEG(x) ((u32)(x) < K0BASE)</span></div>
|
|
<div class="line"><a name="l00082"></a><span class="lineno"> 82</span>  </div>
|
|
<div class="line"><a name="l00083"></a><span class="lineno"> 83</span> <span class="comment">/*</span></div>
|
|
<div class="line"><a name="l00084"></a><span class="lineno"> 84</span> <span class="comment"> * TLB size constants</span></div>
|
|
<div class="line"><a name="l00085"></a><span class="lineno"> 85</span> <span class="comment"> */</span></div>
|
|
<div class="line"><a name="l00086"></a><span class="lineno"> 86</span>  </div>
|
|
<div class="line"><a name="l00087"></a><span class="lineno"><a class="line" href="R4300_8h.html#a97d5657006a351cc30fa24f942b014fd"> 87</a></span> <span class="preprocessor">#define NTLBENTRIES 31 </span><span class="comment">/* entry 31 is reserved by rdb */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00088"></a><span class="lineno"> 88</span>  </div>
|
|
<div class="line"><a name="l00089"></a><span class="lineno"><a class="line" href="R4300_8h.html#aa1c42b77c9a4d118702de38c3399a937"> 89</a></span> <span class="preprocessor">#define TLBHI_VPN2MASK 0xffffe000</span></div>
|
|
<div class="line"><a name="l00090"></a><span class="lineno"><a class="line" href="R4300_8h.html#a98345b3141f3d308748e4aa8a629f6fc"> 90</a></span> <span class="preprocessor">#define TLBHI_VPN2SHIFT 13</span></div>
|
|
<div class="line"><a name="l00091"></a><span class="lineno"><a class="line" href="R4300_8h.html#a45b48245ac409eea36b93cf469dc8b3b"> 91</a></span> <span class="preprocessor">#define TLBHI_PIDMASK 0xff</span></div>
|
|
<div class="line"><a name="l00092"></a><span class="lineno"><a class="line" href="R4300_8h.html#ad1f4c9d61568551d0aa2ffd35389a77a"> 92</a></span> <span class="preprocessor">#define TLBHI_PIDSHIFT 0</span></div>
|
|
<div class="line"><a name="l00093"></a><span class="lineno"><a class="line" href="R4300_8h.html#a647f5b4d0b6e5068c19508763b6709d8"> 93</a></span> <span class="preprocessor">#define TLBHI_NPID 255 </span><span class="comment">/* 255 to fit in 8 bits */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00094"></a><span class="lineno"> 94</span>  </div>
|
|
<div class="line"><a name="l00095"></a><span class="lineno"><a class="line" href="R4300_8h.html#a0b05c722c79c54140e3390170f28aff6"> 95</a></span> <span class="preprocessor">#define TLBLO_PFNMASK 0x3fffffc0</span></div>
|
|
<div class="line"><a name="l00096"></a><span class="lineno"><a class="line" href="R4300_8h.html#af31d0a86bb75a3aa63e89040231d9d9b"> 96</a></span> <span class="preprocessor">#define TLBLO_PFNSHIFT 6</span></div>
|
|
<div class="line"><a name="l00097"></a><span class="lineno"><a class="line" href="R4300_8h.html#a937709443837058b04e5cb8a49d69e6f"> 97</a></span> <span class="preprocessor">#define TLBLO_CACHMASK 0x38 </span><span class="comment">/* cache coherency algorithm */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00098"></a><span class="lineno"><a class="line" href="R4300_8h.html#a8125c30586cf94e52bd012a4baa45c5a"> 98</a></span> <span class="preprocessor">#define TLBLO_CACHSHIFT 3</span></div>
|
|
<div class="line"><a name="l00099"></a><span class="lineno"><a class="line" href="R4300_8h.html#aa0030b0e33de1591a7a7de6b52545646"> 99</a></span> <span class="preprocessor">#define TLBLO_UNCACHED 0x10 </span><span class="comment">/* not cached */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00100"></a><span class="lineno"><a class="line" href="R4300_8h.html#ab3e2a118f42190f9c8c2a7f2d32f602e"> 100</a></span> <span class="preprocessor">#define TLBLO_NONCOHRNT 0x18 </span><span class="comment">/* Cacheable non-coherent */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00101"></a><span class="lineno"><a class="line" href="R4300_8h.html#aa8802288fd6ef72ae2387b6cdbaffdce"> 101</a></span> <span class="preprocessor">#define TLBLO_EXLWR 0x28 </span><span class="comment">/* Exclusive write */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00102"></a><span class="lineno"><a class="line" href="R4300_8h.html#a9ea08f6f43b046cd1af4460dabc5c364"> 102</a></span> <span class="preprocessor">#define TLBLO_D 0x4 </span><span class="comment">/* writeable */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00103"></a><span class="lineno"><a class="line" href="R4300_8h.html#adf689e8333f139ef8cd6bc2507771f5e"> 103</a></span> <span class="preprocessor">#define TLBLO_V 0x2 </span><span class="comment">/* valid bit */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00104"></a><span class="lineno"><a class="line" href="R4300_8h.html#aa943993d3944d6a45eee5e23b05eab9a"> 104</a></span> <span class="preprocessor">#define TLBLO_G 0x1 </span><span class="comment">/* global access bit */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00105"></a><span class="lineno"> 105</span>  </div>
|
|
<div class="line"><a name="l00106"></a><span class="lineno"><a class="line" href="R4300_8h.html#ae2ee4fe221768307a7fe34dfba4e7864"> 106</a></span> <span class="preprocessor">#define TLBINX_PROBE 0x80000000</span></div>
|
|
<div class="line"><a name="l00107"></a><span class="lineno"><a class="line" href="R4300_8h.html#afac9125f463992a59b053003a71ad21c"> 107</a></span> <span class="preprocessor">#define TLBINX_INXMASK 0x3f</span></div>
|
|
<div class="line"><a name="l00108"></a><span class="lineno"><a class="line" href="R4300_8h.html#a59b45b39ef103014fcd24d0e32432133"> 108</a></span> <span class="preprocessor">#define TLBINX_INXSHIFT 0</span></div>
|
|
<div class="line"><a name="l00109"></a><span class="lineno"> 109</span>  </div>
|
|
<div class="line"><a name="l00110"></a><span class="lineno"><a class="line" href="R4300_8h.html#a18a791e582244fd76a9bea5032bd0dfb"> 110</a></span> <span class="preprocessor">#define TLBRAND_RANDMASK 0x3f</span></div>
|
|
<div class="line"><a name="l00111"></a><span class="lineno"><a class="line" href="R4300_8h.html#a00b617d5e664c0cdf174a840dd05dda4"> 111</a></span> <span class="preprocessor">#define TLBRAND_RANDSHIFT 0</span></div>
|
|
<div class="line"><a name="l00112"></a><span class="lineno"> 112</span>  </div>
|
|
<div class="line"><a name="l00113"></a><span class="lineno"><a class="line" href="R4300_8h.html#ae6da5bb0eeb6229beecb89e3817e4205"> 113</a></span> <span class="preprocessor">#define TLBWIRED_WIREDMASK 0x3f</span></div>
|
|
<div class="line"><a name="l00114"></a><span class="lineno"> 114</span>  </div>
|
|
<div class="line"><a name="l00115"></a><span class="lineno"><a class="line" href="R4300_8h.html#a5ea2f758df6ff9d4985cdae024504cb4"> 115</a></span> <span class="preprocessor">#define TLBCTXT_BASEMASK 0xff800000</span></div>
|
|
<div class="line"><a name="l00116"></a><span class="lineno"><a class="line" href="R4300_8h.html#afa14da2a75cbe25f310522cb2a7bac27"> 116</a></span> <span class="preprocessor">#define TLBCTXT_BASESHIFT 23</span></div>
|
|
<div class="line"><a name="l00117"></a><span class="lineno"><a class="line" href="R4300_8h.html#a5013370dd7828f0d0d6b73e5e999c5d7"> 117</a></span> <span class="preprocessor">#define TLBCTXT_BASEBITS 9</span></div>
|
|
<div class="line"><a name="l00118"></a><span class="lineno"> 118</span>  </div>
|
|
<div class="line"><a name="l00119"></a><span class="lineno"><a class="line" href="R4300_8h.html#abbaff42dd4c9b905d823b779e1a60403"> 119</a></span> <span class="preprocessor">#define TLBCTXT_VPNMASK 0x7ffff0</span></div>
|
|
<div class="line"><a name="l00120"></a><span class="lineno"><a class="line" href="R4300_8h.html#a66ac24eb11a0c9e404585c17403e1df9"> 120</a></span> <span class="preprocessor">#define TLBCTXT_VPNSHIFT 4</span></div>
|
|
<div class="line"><a name="l00121"></a><span class="lineno"> 121</span>  </div>
|
|
<div class="line"><a name="l00122"></a><span class="lineno"><a class="line" href="R4300_8h.html#add6ece359ce8e781d23064a0ec03c4aa"> 122</a></span> <span class="preprocessor">#define TLBPGMASK_4K 0x0</span></div>
|
|
<div class="line"><a name="l00123"></a><span class="lineno"><a class="line" href="R4300_8h.html#a8e4841bd334eb711afcaa3ce994ca85d"> 123</a></span> <span class="preprocessor">#define TLBPGMASK_16K 0x6000</span></div>
|
|
<div class="line"><a name="l00124"></a><span class="lineno"><a class="line" href="R4300_8h.html#adfa15b23dc8c3c650d336d1eb635e07b"> 124</a></span> <span class="preprocessor">#define TLBPGMASK_64K 0x1e000</span></div>
|
|
<div class="line"><a name="l00125"></a><span class="lineno"> 125</span>  </div>
|
|
<div class="line"><a name="l00126"></a><span class="lineno"> 126</span> <span class="comment">/*</span></div>
|
|
<div class="line"><a name="l00127"></a><span class="lineno"> 127</span> <span class="comment"> * Status register</span></div>
|
|
<div class="line"><a name="l00128"></a><span class="lineno"> 128</span> <span class="comment"> */</span></div>
|
|
<div class="line"><a name="l00129"></a><span class="lineno"><a class="line" href="R4300_8h.html#a4e25dd430254f41e4b24c45e88e077af"> 129</a></span> <span class="preprocessor">#define SR_CUMASK 0xf0000000 </span><span class="comment">/* coproc usable bits */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00130"></a><span class="lineno"> 130</span>  </div>
|
|
<div class="line"><a name="l00131"></a><span class="lineno"><a class="line" href="R4300_8h.html#a731ceb6fcb47fe47def7e6d34413dc28"> 131</a></span> <span class="preprocessor">#define SR_CU3 0x80000000 </span><span class="comment">/* Coprocessor 3 usable */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00132"></a><span class="lineno"><a class="line" href="R4300_8h.html#a77bc5acb6993952e439ca152be8c85e0"> 132</a></span> <span class="preprocessor">#define SR_CU2 0x40000000 </span><span class="comment">/* Coprocessor 2 usable */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00133"></a><span class="lineno"><a class="line" href="R4300_8h.html#a36fb41eeea92db5e2037314c739bd0ed"> 133</a></span> <span class="preprocessor">#define SR_CU1 0x20000000 </span><span class="comment">/* Coprocessor 1 usable */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00134"></a><span class="lineno"><a class="line" href="R4300_8h.html#a0b2518319f012a42ab420b63f536bd25"> 134</a></span> <span class="preprocessor">#define SR_CU0 0x10000000 </span><span class="comment">/* Coprocessor 0 usable */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00135"></a><span class="lineno"><a class="line" href="R4300_8h.html#a55bc6c4aa5750d4103ca3a5ce01fed06"> 135</a></span> <span class="preprocessor">#define SR_RP 0x08000000 </span><span class="comment">/* Reduced power (quarter speed) */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00136"></a><span class="lineno"><a class="line" href="R4300_8h.html#a9e84f30fe5d9fe25c894b030e6a2a9a5"> 136</a></span> <span class="preprocessor">#define SR_FR 0x04000000 </span><span class="comment">/* MIPS III FP register mode */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00137"></a><span class="lineno"><a class="line" href="R4300_8h.html#add9bbf56dc7c865d8a704dcffb0c2978"> 137</a></span> <span class="preprocessor">#define SR_RE 0x02000000 </span><span class="comment">/* Reverse endian */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00138"></a><span class="lineno"><a class="line" href="R4300_8h.html#a356856d06a3e2401032772eb5bd17201"> 138</a></span> <span class="preprocessor">#define SR_ITS 0x01000000 </span><span class="comment">/* Instruction trace support */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00139"></a><span class="lineno"><a class="line" href="R4300_8h.html#ad2a0c9b17ef7c84606a5156fbd8d22b3"> 139</a></span> <span class="preprocessor">#define SR_BEV 0x00400000 </span><span class="comment">/* Use boot exception vectors */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00140"></a><span class="lineno"><a class="line" href="R4300_8h.html#a4acc9c7fbe3d8ac7ad091b3a4a578bbc"> 140</a></span> <span class="preprocessor">#define SR_TS 0x00200000 </span><span class="comment">/* TLB shutdown */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00141"></a><span class="lineno"><a class="line" href="R4300_8h.html#a66b428edce32266f647343b0510b8385"> 141</a></span> <span class="preprocessor">#define SR_SR 0x00100000 </span><span class="comment">/* Soft reset occured */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00142"></a><span class="lineno"><a class="line" href="R4300_8h.html#a3e2b727f4ebe3cf5664697fccd32c5b1"> 142</a></span> <span class="preprocessor">#define SR_CH 0x00040000 </span><span class="comment">/* Cache hit for last 'cache' op */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00143"></a><span class="lineno"><a class="line" href="R4300_8h.html#a817e1877bde3b959f8026cfcb1da5b7b"> 143</a></span> <span class="preprocessor">#define SR_CE 0x00020000 </span><span class="comment">/* Create ECC */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00144"></a><span class="lineno"><a class="line" href="R4300_8h.html#a7d2d1bffe3ab160cbd33a37d0039fb88"> 144</a></span> <span class="preprocessor">#define SR_DE 0x00010000 </span><span class="comment">/* ECC of parity does not cause error */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00145"></a><span class="lineno"> 145</span>  </div>
|
|
<div class="line"><a name="l00146"></a><span class="lineno"> 146</span> <span class="comment">/*</span></div>
|
|
<div class="line"><a name="l00147"></a><span class="lineno"> 147</span> <span class="comment"> * Interrupt enable bits</span></div>
|
|
<div class="line"><a name="l00148"></a><span class="lineno"> 148</span> <span class="comment"> * (NOTE: bits set to 1 enable the corresponding level interrupt)</span></div>
|
|
<div class="line"><a name="l00149"></a><span class="lineno"> 149</span> <span class="comment"> */</span></div>
|
|
<div class="line"><a name="l00150"></a><span class="lineno"><a class="line" href="R4300_8h.html#a035d1cf8a3d7537bb938e8045b9e38e6"> 150</a></span> <span class="preprocessor">#define SR_IMASK 0x0000ff00 </span><span class="comment">/* Interrupt mask */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00151"></a><span class="lineno"><a class="line" href="R4300_8h.html#a0263ec78c2a1889685f58bb63e4ca9f4"> 151</a></span> <span class="preprocessor">#define SR_IMASK8 0x00000000 </span><span class="comment">/* mask level 8 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00152"></a><span class="lineno"><a class="line" href="R4300_8h.html#a98a34e032c898f616b0459a2e7fb55f9"> 152</a></span> <span class="preprocessor">#define SR_IMASK7 0x00008000 </span><span class="comment">/* mask level 7 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00153"></a><span class="lineno"><a class="line" href="R4300_8h.html#a7b945ac8b1c66313283ea5725eb85b20"> 153</a></span> <span class="preprocessor">#define SR_IMASK6 0x0000c000 </span><span class="comment">/* mask level 6 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00154"></a><span class="lineno"><a class="line" href="R4300_8h.html#ae934c9354cc72fa5c975084fdf9e969c"> 154</a></span> <span class="preprocessor">#define SR_IMASK5 0x0000e000 </span><span class="comment">/* mask level 5 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00155"></a><span class="lineno"><a class="line" href="R4300_8h.html#a5729ab8679744379b87c194673d4d88d"> 155</a></span> <span class="preprocessor">#define SR_IMASK4 0x0000f000 </span><span class="comment">/* mask level 4 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00156"></a><span class="lineno"><a class="line" href="R4300_8h.html#ac075bdc32696a07543981480129d3ce1"> 156</a></span> <span class="preprocessor">#define SR_IMASK3 0x0000f800 </span><span class="comment">/* mask level 3 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00157"></a><span class="lineno"><a class="line" href="R4300_8h.html#a30592afdac480cbf4a17f51a32979f1b"> 157</a></span> <span class="preprocessor">#define SR_IMASK2 0x0000fc00 </span><span class="comment">/* mask level 2 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00158"></a><span class="lineno"><a class="line" href="R4300_8h.html#ab0314bdafafd313f32ecadc61c35e9f2"> 158</a></span> <span class="preprocessor">#define SR_IMASK1 0x0000fe00 </span><span class="comment">/* mask level 1 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00159"></a><span class="lineno"><a class="line" href="R4300_8h.html#ab9ba9a4b874d04ac4bcae5f4d7b7dca7"> 159</a></span> <span class="preprocessor">#define SR_IMASK0 0x0000ff00 </span><span class="comment">/* mask level 0 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00160"></a><span class="lineno"> 160</span>  </div>
|
|
<div class="line"><a name="l00161"></a><span class="lineno"><a class="line" href="R4300_8h.html#ac9c1288340817a88964a605cb4d12802"> 161</a></span> <span class="preprocessor">#define SR_IBIT8 0x00008000 </span><span class="comment">/* bit level 8 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00162"></a><span class="lineno"><a class="line" href="R4300_8h.html#a103f9805f7a2e502907ebecbff7257b5"> 162</a></span> <span class="preprocessor">#define SR_IBIT7 0x00004000 </span><span class="comment">/* bit level 7 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00163"></a><span class="lineno"><a class="line" href="R4300_8h.html#a0f90042d241c7217ec4827415a0114a0"> 163</a></span> <span class="preprocessor">#define SR_IBIT6 0x00002000 </span><span class="comment">/* bit level 6 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00164"></a><span class="lineno"><a class="line" href="R4300_8h.html#af2950115ed6fba480f6c5f4f153ed091"> 164</a></span> <span class="preprocessor">#define SR_IBIT5 0x00001000 </span><span class="comment">/* bit level 5 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00165"></a><span class="lineno"><a class="line" href="R4300_8h.html#ab63840ac11ab9f834f5943c0537a22f2"> 165</a></span> <span class="preprocessor">#define SR_IBIT4 0x00000800 </span><span class="comment">/* bit level 4 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00166"></a><span class="lineno"><a class="line" href="R4300_8h.html#a9841420ebef5f62017a6a35dfe446742"> 166</a></span> <span class="preprocessor">#define SR_IBIT3 0x00000400 </span><span class="comment">/* bit level 3 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00167"></a><span class="lineno"><a class="line" href="R4300_8h.html#a6c459c098b08e977f0425a23654d0ae7"> 167</a></span> <span class="preprocessor">#define SR_IBIT2 0x00000200 </span><span class="comment">/* bit level 2 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00168"></a><span class="lineno"><a class="line" href="R4300_8h.html#a5f81c64898b8b43cb0a37db1d1e81b20"> 168</a></span> <span class="preprocessor">#define SR_IBIT1 0x00000100 </span><span class="comment">/* bit level 1 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00169"></a><span class="lineno"> 169</span>  </div>
|
|
<div class="line"><a name="l00170"></a><span class="lineno"><a class="line" href="R4300_8h.html#aae979c6ed256c0f770161b205651e47a"> 170</a></span> <span class="preprocessor">#define SR_IMASKSHIFT 8</span></div>
|
|
<div class="line"><a name="l00171"></a><span class="lineno"> 171</span>  </div>
|
|
<div class="line"><a name="l00172"></a><span class="lineno"><a class="line" href="R4300_8h.html#a1db5aeec66fb182178b2a461e7ab6b05"> 172</a></span> <span class="preprocessor">#define SR_KX 0x00000080 </span><span class="comment">/* extended-addr TLB vec in kernel */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00173"></a><span class="lineno"><a class="line" href="R4300_8h.html#a3d8d231eca1e567ae8186ed28153a633"> 173</a></span> <span class="preprocessor">#define SR_SX 0x00000040 </span><span class="comment">/* xtended-addr TLB vec supervisor */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00174"></a><span class="lineno"><a class="line" href="R4300_8h.html#aae4290665a4c2892503ba18a4b0fd863"> 174</a></span> <span class="preprocessor">#define SR_UX 0x00000020 </span><span class="comment">/* xtended-addr TLB vec in user mode */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00175"></a><span class="lineno"><a class="line" href="R4300_8h.html#a881601059f20ea3afc7ee0360d1ae13b"> 175</a></span> <span class="preprocessor">#define SR_KSU_MASK 0x00000018 </span><span class="comment">/* mode mask */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00176"></a><span class="lineno"><a class="line" href="R4300_8h.html#a1fb26233a735fcf514e32603f912e492"> 176</a></span> <span class="preprocessor">#define SR_KSU_USR 0x00000010 </span><span class="comment">/* user mode */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00177"></a><span class="lineno"><a class="line" href="R4300_8h.html#a53da2c112819b26cf91cc3d920648c8e"> 177</a></span> <span class="preprocessor">#define SR_KSU_SUP 0x00000008 </span><span class="comment">/* supervisor mode */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00178"></a><span class="lineno"><a class="line" href="R4300_8h.html#a23cd7fce58462bfb2aefc87f1abc1b47"> 178</a></span> <span class="preprocessor">#define SR_KSU_KER 0x00000000 </span><span class="comment">/* kernel mode */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00179"></a><span class="lineno"><a class="line" href="R4300_8h.html#ad410419020f06f5d945410007aa82d96"> 179</a></span> <span class="preprocessor">#define SR_ERL 0x00000004 </span><span class="comment">/* Error level, 1=>cache error */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00180"></a><span class="lineno"><a class="line" href="R4300_8h.html#aedbf6f260111a25cf3ddb4b19322507c"> 180</a></span> <span class="preprocessor">#define SR_EXL 0x00000002 </span><span class="comment">/* Exception level, 1=>exception */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00181"></a><span class="lineno"><a class="line" href="R4300_8h.html#aef8e7d6f08ca926c626eacb7a9482e90"> 181</a></span> <span class="preprocessor">#define SR_IE 0x00000001 </span><span class="comment">/* interrupt enable, 1=>enable */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00182"></a><span class="lineno"> 182</span>  </div>
|
|
<div class="line"><a name="l00183"></a><span class="lineno"> 183</span> <span class="comment">/*</span></div>
|
|
<div class="line"><a name="l00184"></a><span class="lineno"> 184</span> <span class="comment"> * Cause Register</span></div>
|
|
<div class="line"><a name="l00185"></a><span class="lineno"> 185</span> <span class="comment"> */</span></div>
|
|
<div class="line"><a name="l00186"></a><span class="lineno"><a class="line" href="R4300_8h.html#af6c84bb63ee6853d26df23dfe327ec8d"> 186</a></span> <span class="preprocessor">#define CAUSE_BD 0x80000000 </span><span class="comment">/* Branch delay slot */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00187"></a><span class="lineno"><a class="line" href="R4300_8h.html#a85f3c710d2ad23a33dd6494dcd5ef98c"> 187</a></span> <span class="preprocessor">#define CAUSE_CEMASK 0x30000000 </span><span class="comment">/* coprocessor error */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00188"></a><span class="lineno"><a class="line" href="R4300_8h.html#a5002e4fac1abb5b8c9b0805b83cd6fec"> 188</a></span> <span class="preprocessor">#define CAUSE_CESHIFT 28</span></div>
|
|
<div class="line"><a name="l00189"></a><span class="lineno"> 189</span>  </div>
|
|
<div class="line"><a name="l00190"></a><span class="lineno"> 190</span> <span class="comment">/* Interrupt pending bits */</span></div>
|
|
<div class="line"><a name="l00191"></a><span class="lineno"><a class="line" href="R4300_8h.html#ae42565e597b8d7445b884c23d07b79be"> 191</a></span> <span class="preprocessor">#define CAUSE_IP8 0x00008000 </span><span class="comment">/* External level 8 pending - COMPARE */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00192"></a><span class="lineno"><a class="line" href="R4300_8h.html#aab5f5738fea4293a8f6c31ff5523839d"> 192</a></span> <span class="preprocessor">#define CAUSE_IP7 0x00004000 </span><span class="comment">/* External level 7 pending - INT4 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00193"></a><span class="lineno"><a class="line" href="R4300_8h.html#a029c9eb01218e833517efcebaf69e760"> 193</a></span> <span class="preprocessor">#define CAUSE_IP6 0x00002000 </span><span class="comment">/* External level 6 pending - INT3 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00194"></a><span class="lineno"><a class="line" href="R4300_8h.html#a82f09d3194aca040d949dab84df5f33f"> 194</a></span> <span class="preprocessor">#define CAUSE_IP5 0x00001000 </span><span class="comment">/* External level 5 pending - INT2 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00195"></a><span class="lineno"><a class="line" href="R4300_8h.html#a0da7b08b395fed03edc0d0131618b052"> 195</a></span> <span class="preprocessor">#define CAUSE_IP4 0x00000800 </span><span class="comment">/* External level 4 pending - INT1 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00196"></a><span class="lineno"><a class="line" href="R4300_8h.html#afc8010dea8d9cb75bcd1d2e51aff0fee"> 196</a></span> <span class="preprocessor">#define CAUSE_IP3 0x00000400 </span><span class="comment">/* External level 3 pending - INT0 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00197"></a><span class="lineno"><a class="line" href="R4300_8h.html#a5993badf32dc290e32ac88b5b3dd4aa9"> 197</a></span> <span class="preprocessor">#define CAUSE_SW2 0x00000200 </span><span class="comment">/* Software level 2 pending */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00198"></a><span class="lineno"><a class="line" href="R4300_8h.html#ad288aa81a67e220dd5905a47884cdc2f"> 198</a></span> <span class="preprocessor">#define CAUSE_SW1 0x00000100 </span><span class="comment">/* Software level 1 pending */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00199"></a><span class="lineno"> 199</span>  </div>
|
|
<div class="line"><a name="l00200"></a><span class="lineno"><a class="line" href="R4300_8h.html#ac67d94f04ddd8ef7d562d60810bb990c"> 200</a></span> <span class="preprocessor">#define CAUSE_IPMASK 0x0000FF00 </span><span class="comment">/* Pending interrupt mask */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00201"></a><span class="lineno"><a class="line" href="R4300_8h.html#a46decdf2d0a01629642bbd6a00e87e31"> 201</a></span> <span class="preprocessor">#define CAUSE_IPSHIFT 8</span></div>
|
|
<div class="line"><a name="l00202"></a><span class="lineno"> 202</span>  </div>
|
|
<div class="line"><a name="l00203"></a><span class="lineno"><a class="line" href="R4300_8h.html#a9b2cd768ba71fe7d4c012c32a21132ac"> 203</a></span> <span class="preprocessor">#define CAUSE_EXCMASK 0x0000007C </span><span class="comment">/* Cause code bits */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00204"></a><span class="lineno"> 204</span>  </div>
|
|
<div class="line"><a name="l00205"></a><span class="lineno"><a class="line" href="R4300_8h.html#a7a3c945a3ca9d7e574fa938ee5ec2f1a"> 205</a></span> <span class="preprocessor">#define CAUSE_EXCSHIFT 2</span></div>
|
|
<div class="line"><a name="l00206"></a><span class="lineno"> 206</span>  </div>
|
|
<div class="line"><a name="l00207"></a><span class="lineno"> 207</span> <span class="comment">/* Cause register exception codes */</span></div>
|
|
<div class="line"><a name="l00208"></a><span class="lineno"> 208</span>  </div>
|
|
<div class="line"><a name="l00209"></a><span class="lineno"><a class="line" href="R4300_8h.html#a56249f71c5d10c9b20bdb52864d59e75"> 209</a></span> <span class="preprocessor">#define EXC_CODE(x) ((x)<<2)</span></div>
|
|
<div class="line"><a name="l00210"></a><span class="lineno"> 210</span>  </div>
|
|
<div class="line"><a name="l00211"></a><span class="lineno"> 211</span> <span class="comment">/* Hardware exception codes */</span></div>
|
|
<div class="line"><a name="l00212"></a><span class="lineno"><a class="line" href="R4300_8h.html#aa83ef072a9ff98cfbc0395eac6b5b9eb"> 212</a></span> <span class="preprocessor">#define EXC_INT EXC_CODE(0) </span><span class="comment">/* interrupt */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00213"></a><span class="lineno"><a class="line" href="R4300_8h.html#a8d9e5778caddc63f3ad5473e3c547247"> 213</a></span> <span class="preprocessor">#define EXC_MOD EXC_CODE(1) </span><span class="comment">/* TLB mod */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00214"></a><span class="lineno"><a class="line" href="R4300_8h.html#aa21bc7a1064c1d2e06450c3ee0667928"> 214</a></span> <span class="preprocessor">#define EXC_RMISS EXC_CODE(2) </span><span class="comment">/* Read TLB Miss */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00215"></a><span class="lineno"><a class="line" href="R4300_8h.html#a0a0abac9f89bd92856e6d846b701db77"> 215</a></span> <span class="preprocessor">#define EXC_WMISS EXC_CODE(3) </span><span class="comment">/* Write TLB Miss */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00216"></a><span class="lineno"><a class="line" href="R4300_8h.html#a1c7b259dd31642d32052c3b3beaec315"> 216</a></span> <span class="preprocessor">#define EXC_RADE EXC_CODE(4) </span><span class="comment">/* Read Address Error */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00217"></a><span class="lineno"><a class="line" href="R4300_8h.html#a07fa74e607648038c2ab0e2a62aac10d"> 217</a></span> <span class="preprocessor">#define EXC_WADE EXC_CODE(5) </span><span class="comment">/* Write Address Error */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00218"></a><span class="lineno"><a class="line" href="R4300_8h.html#a03deddb0b30fbc2cef16b63252051d2f"> 218</a></span> <span class="preprocessor">#define EXC_IBE EXC_CODE(6) </span><span class="comment">/* Instruction Bus Error */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00219"></a><span class="lineno"><a class="line" href="R4300_8h.html#ae769c5189bbd7e36dd5816bb0f6a331a"> 219</a></span> <span class="preprocessor">#define EXC_DBE EXC_CODE(7) </span><span class="comment">/* Data Bus Error */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00220"></a><span class="lineno"><a class="line" href="R4300_8h.html#ab6e3c7c4587ff8dfa1a2241e0066d5dd"> 220</a></span> <span class="preprocessor">#define EXC_SYSCALL EXC_CODE(8) </span><span class="comment">/* SYSCALL */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00221"></a><span class="lineno"><a class="line" href="R4300_8h.html#a515f08b4a8746bc318264bd58a8234b4"> 221</a></span> <span class="preprocessor">#define EXC_BREAK EXC_CODE(9) </span><span class="comment">/* BREAKpoint */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00222"></a><span class="lineno"><a class="line" href="R4300_8h.html#a2046c5eef89bef8b42d0799d3c89c05a"> 222</a></span> <span class="preprocessor">#define EXC_II EXC_CODE(10) </span><span class="comment">/* Illegal Instruction */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00223"></a><span class="lineno"><a class="line" href="R4300_8h.html#af018465829b21f29813cd1a96435d544"> 223</a></span> <span class="preprocessor">#define EXC_CPU EXC_CODE(11) </span><span class="comment">/* CoProcessor Unusable */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00224"></a><span class="lineno"><a class="line" href="R4300_8h.html#a2173fe226c1142c573798db127465501"> 224</a></span> <span class="preprocessor">#define EXC_OV EXC_CODE(12) </span><span class="comment">/* OVerflow */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00225"></a><span class="lineno"><a class="line" href="R4300_8h.html#ae83cefaf5b9c8002251c7716bed0ae5c"> 225</a></span> <span class="preprocessor">#define EXC_TRAP EXC_CODE(13) </span><span class="comment">/* Trap exception */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00226"></a><span class="lineno"><a class="line" href="R4300_8h.html#a546ca841cbd2937bdf1a47956ba49ab5"> 226</a></span> <span class="preprocessor">#define EXC_VCEI EXC_CODE(14) </span><span class="comment">/* Virt. Coherency on Inst. fetch */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00227"></a><span class="lineno"><a class="line" href="R4300_8h.html#a13cc99d32ca71553c2ee58a6594909bc"> 227</a></span> <span class="preprocessor">#define EXC_FPE EXC_CODE(15) </span><span class="comment">/* Floating Point Exception */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00228"></a><span class="lineno"><a class="line" href="R4300_8h.html#ab81d775bd538ca8c3ece3f20e0f9313c"> 228</a></span> <span class="preprocessor">#define EXC_WATCH EXC_CODE(23) </span><span class="comment">/* Watchpoint reference */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00229"></a><span class="lineno"><a class="line" href="R4300_8h.html#a3044bacfe73e56b6006d9418dee87056"> 229</a></span> <span class="preprocessor">#define EXC_VCED EXC_CODE(31) </span><span class="comment">/* Virt. Coherency on data read */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00230"></a><span class="lineno"> 230</span>  </div>
|
|
<div class="line"><a name="l00231"></a><span class="lineno"> 231</span> <span class="comment">/* C0_PRID Defines */</span></div>
|
|
<div class="line"><a name="l00232"></a><span class="lineno"><a class="line" href="R4300_8h.html#ad029265f32eee1728de4e5e2f6196319"> 232</a></span> <span class="preprocessor">#define C0_IMPMASK 0xff00</span></div>
|
|
<div class="line"><a name="l00233"></a><span class="lineno"><a class="line" href="R4300_8h.html#a9212084cea3fe4be13cdc76bfe47442b"> 233</a></span> <span class="preprocessor">#define C0_IMPSHIFT 8</span></div>
|
|
<div class="line"><a name="l00234"></a><span class="lineno"><a class="line" href="R4300_8h.html#a22a1cfef77c480229491985d9686b054"> 234</a></span> <span class="preprocessor">#define C0_REVMASK 0xff</span></div>
|
|
<div class="line"><a name="l00235"></a><span class="lineno"><a class="line" href="R4300_8h.html#a7ca219e703e472f3a4d1decbccc5d235"> 235</a></span> <span class="preprocessor">#define C0_MAJREVMASK 0xf0</span></div>
|
|
<div class="line"><a name="l00236"></a><span class="lineno"><a class="line" href="R4300_8h.html#ade86a9e83a203be3da04118b25697f0a"> 236</a></span> <span class="preprocessor">#define C0_MAJREVSHIFT 4</span></div>
|
|
<div class="line"><a name="l00237"></a><span class="lineno"><a class="line" href="R4300_8h.html#a775f1f442207b5889be8303bf79c201e"> 237</a></span> <span class="preprocessor">#define C0_MINREVMASK 0xf</span></div>
|
|
<div class="line"><a name="l00238"></a><span class="lineno"> 238</span>  </div>
|
|
<div class="line"><a name="l00239"></a><span class="lineno"> 239</span> <span class="comment">/*</span></div>
|
|
<div class="line"><a name="l00240"></a><span class="lineno"> 240</span> <span class="comment"> * Coprocessor 0 operations</span></div>
|
|
<div class="line"><a name="l00241"></a><span class="lineno"> 241</span> <span class="comment"> */</span></div>
|
|
<div class="line"><a name="l00242"></a><span class="lineno"><a class="line" href="R4300_8h.html#a6d63910e1fcd3a9bb86a71900f24918a"> 242</a></span> <span class="preprocessor">#define C0_READI 0x1 </span><span class="comment">/* read ITLB entry addressed by C0_INDEX */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00243"></a><span class="lineno"><a class="line" href="R4300_8h.html#aad2ccd43977ff34748d0039275daf2c1"> 243</a></span> <span class="preprocessor">#define C0_WRITEI 0x2 </span><span class="comment">/* write ITLB entry addressed by C0_INDEX */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00244"></a><span class="lineno"><a class="line" href="R4300_8h.html#ab963df61adc0a38619a2ed5d7c6a9cb8"> 244</a></span> <span class="preprocessor">#define C0_WRITER 0x6 </span><span class="comment">/* write ITLB entry addressed by C0_RAND */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00245"></a><span class="lineno"><a class="line" href="R4300_8h.html#af3dee7af38e7e6747a5efcb55bfa0c7b"> 245</a></span> <span class="preprocessor">#define C0_PROBE 0x8 </span><span class="comment">/* probe for ITLB entry addressed by TLBHI */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00246"></a><span class="lineno"><a class="line" href="R4300_8h.html#ad7e4a55b9046c6bccccf1b1feb61c2ab"> 246</a></span> <span class="preprocessor">#define C0_RFE 0x10 </span><span class="comment">/* restore for exception */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00247"></a><span class="lineno"> 247</span>  </div>
|
|
<div class="line"><a name="l00248"></a><span class="lineno"> 248</span> <span class="comment">/*</span></div>
|
|
<div class="line"><a name="l00249"></a><span class="lineno"> 249</span> <span class="comment"> * 'cache' instruction definitions</span></div>
|
|
<div class="line"><a name="l00250"></a><span class="lineno"> 250</span> <span class="comment"> */</span></div>
|
|
<div class="line"><a name="l00251"></a><span class="lineno"> 251</span>  </div>
|
|
<div class="line"><a name="l00252"></a><span class="lineno"> 252</span> <span class="comment">/* Target cache */</span></div>
|
|
<div class="line"><a name="l00253"></a><span class="lineno"><a class="line" href="R4300_8h.html#add2077199892bdeee5713399b3df7b5a"> 253</a></span> <span class="preprocessor">#define CACH_PI 0x0 </span><span class="comment">/* specifies primary inst. cache */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00254"></a><span class="lineno"><a class="line" href="R4300_8h.html#af3bc52a6c3f07ce7c54b21a7f0b9edfa"> 254</a></span> <span class="preprocessor">#define CACH_PD 0x1 </span><span class="comment">/* primary data cache */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00255"></a><span class="lineno"><a class="line" href="R4300_8h.html#a6e9a57a3df1d486e84ca81d4305e8692"> 255</a></span> <span class="preprocessor">#define CACH_SI 0x2 </span><span class="comment">/* secondary instruction cache */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00256"></a><span class="lineno"><a class="line" href="R4300_8h.html#a67c1191d08e75d161fe069aadab7f474"> 256</a></span> <span class="preprocessor">#define CACH_SD 0x3 </span><span class="comment">/* secondary data cache */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00257"></a><span class="lineno"> 257</span>  </div>
|
|
<div class="line"><a name="l00258"></a><span class="lineno"> 258</span> <span class="comment">/* Cache operations */</span></div>
|
|
<div class="line"><a name="l00259"></a><span class="lineno"><a class="line" href="R4300_8h.html#a7cca9a4ca8a0162f72a2778a7ed7b910"> 259</a></span> <span class="preprocessor">#define C_IINV 0x0 </span><span class="comment">/* index invalidate (inst, 2nd inst) */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00260"></a><span class="lineno"><a class="line" href="R4300_8h.html#aa46f7e2b5f0975ff1a3dbf5faefef71a"> 260</a></span> <span class="preprocessor">#define C_IWBINV 0x0 </span><span class="comment">/* index writeback inval (d, sd) */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00261"></a><span class="lineno"><a class="line" href="R4300_8h.html#a183d26a8c66d8efecad2ede486f9e746"> 261</a></span> <span class="preprocessor">#define C_ILT 0x4 </span><span class="comment">/* index load tag (all) */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00262"></a><span class="lineno"><a class="line" href="R4300_8h.html#a75ac1156041ddc7322f226b2c8ec1c02"> 262</a></span> <span class="preprocessor">#define C_IST 0x8 </span><span class="comment">/* index store tag (all) */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00263"></a><span class="lineno"><a class="line" href="R4300_8h.html#a6ce1062c393a688c586d694c12ed4645"> 263</a></span> <span class="preprocessor">#define C_CDX 0xc </span><span class="comment">/* create dirty exclusive (d, sd) */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00264"></a><span class="lineno"><a class="line" href="R4300_8h.html#a888a71bec61a6d94fd8bd3b2babb7d25"> 264</a></span> <span class="preprocessor">#define C_HINV 0x10 </span><span class="comment">/* hit invalidate (all) */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00265"></a><span class="lineno"><a class="line" href="R4300_8h.html#a87c31c2c1e68dcc34a8cb899a1303d64"> 265</a></span> <span class="preprocessor">#define C_HWBINV 0x14 </span><span class="comment">/* hit writeback inv. (d, sd) */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00266"></a><span class="lineno"><a class="line" href="R4300_8h.html#afc63de94fe0a2df16a538100115adece"> 266</a></span> <span class="preprocessor">#define C_FILL 0x14 </span><span class="comment">/* fill (i) */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00267"></a><span class="lineno"><a class="line" href="R4300_8h.html#a675b24a3697a878133c0791e1fec0b77"> 267</a></span> <span class="preprocessor">#define C_HWB 0x18 </span><span class="comment">/* hit writeback (i, d, sd) */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00268"></a><span class="lineno"><a class="line" href="R4300_8h.html#ab07fd534ba0cb5857bebd6ef0e6b994f"> 268</a></span> <span class="preprocessor">#define C_HSV 0x1c </span><span class="comment">/* hit set virt. (si, sd) */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00269"></a><span class="lineno"> 269</span>  </div>
|
|
<div class="line"><a name="l00270"></a><span class="lineno"> 270</span> <span class="comment">/*</span></div>
|
|
<div class="line"><a name="l00271"></a><span class="lineno"> 271</span> <span class="comment"> * Cache size definitions</span></div>
|
|
<div class="line"><a name="l00272"></a><span class="lineno"> 272</span> <span class="comment"> */</span></div>
|
|
<div class="line"><a name="l00273"></a><span class="lineno"><a class="line" href="R4300_8h.html#a22410cb075a78b53930c854e7964492b"> 273</a></span> <span class="preprocessor">#define ICACHE_SIZE 0x4000 </span><span class="comment">/* 16K */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00274"></a><span class="lineno"><a class="line" href="R4300_8h.html#a9f7bc7faac7832c27e338cd6f8c86de5"> 274</a></span> <span class="preprocessor">#define ICACHE_LINESIZE 32 </span><span class="comment">/* 8 words */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00275"></a><span class="lineno"><a class="line" href="R4300_8h.html#a606dd52e4a35f185c83bb7d84072942f"> 275</a></span> <span class="preprocessor">#define ICACHE_LINEMASK (ICACHE_LINESIZE-1)</span></div>
|
|
<div class="line"><a name="l00276"></a><span class="lineno"> 276</span>  </div>
|
|
<div class="line"><a name="l00277"></a><span class="lineno"><a class="line" href="R4300_8h.html#a11677b965695c567f2802f8cd8f4980f"> 277</a></span> <span class="preprocessor">#define DCACHE_SIZE 0x2000 </span><span class="comment">/* 8K */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00278"></a><span class="lineno"><a class="line" href="R4300_8h.html#a2a239cb79057994714d5761d5aa9edb5"> 278</a></span> <span class="preprocessor">#define DCACHE_LINESIZE 16 </span><span class="comment">/* 4 words */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00279"></a><span class="lineno"><a class="line" href="R4300_8h.html#a8caa773d83d32d4762d5bab7a6011537"> 279</a></span> <span class="preprocessor">#define DCACHE_LINEMASK (DCACHE_LINESIZE-1)</span></div>
|
|
<div class="line"><a name="l00280"></a><span class="lineno"> 280</span>  </div>
|
|
<div class="line"><a name="l00281"></a><span class="lineno"> 281</span> <span class="comment">/*</span></div>
|
|
<div class="line"><a name="l00282"></a><span class="lineno"> 282</span> <span class="comment"> * C0_CONFIG register definitions</span></div>
|
|
<div class="line"><a name="l00283"></a><span class="lineno"> 283</span> <span class="comment"> */</span></div>
|
|
<div class="line"><a name="l00284"></a><span class="lineno"><a class="line" href="R4300_8h.html#a0c06fc83aabbc8361e7f443b509a1654"> 284</a></span> <span class="preprocessor">#define CONFIG_CM 0x80000000 </span><span class="comment">/* 1 == Master-Checker enabled */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00285"></a><span class="lineno"><a class="line" href="R4300_8h.html#aec188a2393f34a14a066cd63c0bc9014"> 285</a></span> <span class="preprocessor">#define CONFIG_EC 0x70000000 </span><span class="comment">/* System Clock ratio */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00286"></a><span class="lineno"><a class="line" href="R4300_8h.html#a97378e884f42b6fc9c8626ca38fb65c6"> 286</a></span> <span class="preprocessor">#define CONFIG_EC_1_1 0x6 </span><span class="comment">/* System Clock ratio 1 :1 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00287"></a><span class="lineno"><a class="line" href="R4300_8h.html#afa14bc61778cfc9059322f94d8e61399"> 287</a></span> <span class="preprocessor">#define CONFIG_EC_3_2 0x7 </span><span class="comment">/* System Clock ratio 1.5 :1 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00288"></a><span class="lineno"><a class="line" href="R4300_8h.html#ab88853f6f1fdb6724b23c3b7106ea327"> 288</a></span> <span class="preprocessor">#define CONFIG_EC_2_1 0x0 </span><span class="comment">/* System Clock ratio 2 :1 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00289"></a><span class="lineno"><a class="line" href="R4300_8h.html#ac710ef5d4fc5ba727016ed8542526d60"> 289</a></span> <span class="preprocessor">#define CONFIG_EC_3_1 0x1 </span><span class="comment">/* System Clock ratio 3 :1 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00290"></a><span class="lineno"><a class="line" href="R4300_8h.html#a34691f4b348e6fb530c72e8aec0bd74f"> 290</a></span> <span class="preprocessor">#define CONFIG_EP 0x0f000000 </span><span class="comment">/* Transmit Data Pattern */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00291"></a><span class="lineno"><a class="line" href="R4300_8h.html#a784f7233461cc055a3a75514b2ffe2c7"> 291</a></span> <span class="preprocessor">#define CONFIG_SB 0x00c00000 </span><span class="comment">/* Secondary cache block size */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00292"></a><span class="lineno"> 292</span>  </div>
|
|
<div class="line"><a name="l00293"></a><span class="lineno"><a class="line" href="R4300_8h.html#ad2fab756595954347e2b692942450554"> 293</a></span> <span class="preprocessor">#define CONFIG_SS 0x00200000 </span><span class="comment">/* Split scache: 0 == I&D combined */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00294"></a><span class="lineno"><a class="line" href="R4300_8h.html#aae3f926fdc154d3c8644125dd912dda3"> 294</a></span> <span class="preprocessor">#define CONFIG_SW 0x00100000 </span><span class="comment">/* scache port: 0==128, 1==64 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00295"></a><span class="lineno"><a class="line" href="R4300_8h.html#a430561654f11bb4f1a096eca0b84af4e"> 295</a></span> <span class="preprocessor">#define CONFIG_EW 0x000c0000 </span><span class="comment">/* System Port width: 0==64, 1==32 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00296"></a><span class="lineno"><a class="line" href="R4300_8h.html#a16be1f36266a0580ec5ecbe64dc6a31d"> 296</a></span> <span class="preprocessor">#define CONFIG_SC 0x00020000 </span><span class="comment">/* 0 -> 2nd cache present */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00297"></a><span class="lineno"><a class="line" href="R4300_8h.html#afabb5c5d19bee6b163fc26c294e3f52d"> 297</a></span> <span class="preprocessor">#define CONFIG_SM 0x00010000 </span><span class="comment">/* 0 -> Dirty Shared Coherency enabled*/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00298"></a><span class="lineno"><a class="line" href="R4300_8h.html#a3ee45d384e4d712e30b5767a26249669"> 298</a></span> <span class="preprocessor">#define CONFIG_BE 0x00008000 </span><span class="comment">/* Endian-ness: 1 --> BE */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00299"></a><span class="lineno"><a class="line" href="R4300_8h.html#ac7c54021f89990d64ad72c147ed79d02"> 299</a></span> <span class="preprocessor">#define CONFIG_EM 0x00004000 </span><span class="comment">/* 1 -> ECC mode, 0 -> parity */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00300"></a><span class="lineno"><a class="line" href="R4300_8h.html#ac1d17ea4afbadd7f23dd886f888e5d25"> 300</a></span> <span class="preprocessor">#define CONFIG_EB 0x00002000 </span><span class="comment">/* Block order:1->sequent,0->subblock */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00301"></a><span class="lineno"> 301</span>  </div>
|
|
<div class="line"><a name="l00302"></a><span class="lineno"><a class="line" href="R4300_8h.html#ac9ba2d562331d35ecacb349807574d22"> 302</a></span> <span class="preprocessor">#define CONFIG_IC 0x00000e00 </span><span class="comment">/* Primary Icache size */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00303"></a><span class="lineno"><a class="line" href="R4300_8h.html#a916e5c50650a2bd24d4c4c642253c810"> 303</a></span> <span class="preprocessor">#define CONFIG_DC 0x000001c0 </span><span class="comment">/* Primary Dcache size */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00304"></a><span class="lineno"><a class="line" href="R4300_8h.html#aebba4dba2ec33c088ef3dc533a01cc35"> 304</a></span> <span class="preprocessor">#define CONFIG_IB 0x00000020 </span><span class="comment">/* Icache block size */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00305"></a><span class="lineno"><a class="line" href="R4300_8h.html#a8ec07be0e5d5642109afe97a2f8851dc"> 305</a></span> <span class="preprocessor">#define CONFIG_DB 0x00000010 </span><span class="comment">/* Dcache block size */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00306"></a><span class="lineno"><a class="line" href="R4300_8h.html#a066d719e63435121f2c085403ddc338d"> 306</a></span> <span class="preprocessor">#define CONFIG_CU 0x00000008 </span><span class="comment">/* Update on Store-conditional */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00307"></a><span class="lineno"><a class="line" href="R4300_8h.html#a9bda55a9db3ae757be1fdcab4d9acef3"> 307</a></span> <span class="preprocessor">#define CONFIG_K0 0x00000007 </span><span class="comment">/* K0SEG Coherency algorithm */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00308"></a><span class="lineno"> 308</span>  </div>
|
|
<div class="line"><a name="l00309"></a><span class="lineno"><a class="line" href="R4300_8h.html#a610d752ef0c84c7493eee4cb9ad907ae"> 309</a></span> <span class="preprocessor">#define CONFIG_UNCACHED 0x00000002 </span><span class="comment">/* K0 is uncached */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00310"></a><span class="lineno"><a class="line" href="R4300_8h.html#ab35ae696dcaa063d116276f11c339bd4"> 310</a></span> <span class="preprocessor">#define CONFIG_NONCOHRNT 0x00000003</span></div>
|
|
<div class="line"><a name="l00311"></a><span class="lineno"><a class="line" href="R4300_8h.html#a4ca12540ed24c96de99518438fb8b5f0"> 311</a></span> <span class="preprocessor">#define CONFIG_COHRNT_EXLWR 0x00000005</span></div>
|
|
<div class="line"><a name="l00312"></a><span class="lineno"><a class="line" href="R4300_8h.html#a247b348c1877ed4f18f3e6da3a1f37d4"> 312</a></span> <span class="preprocessor">#define CONFIG_SB_SHFT 22 </span><span class="comment">/* shift SB to bit position 0 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00313"></a><span class="lineno"><a class="line" href="R4300_8h.html#a4a368b8ae9f9c8bf4f17b1cd10660591"> 313</a></span> <span class="preprocessor">#define CONFIG_IC_SHFT 9 </span><span class="comment">/* shift IC to bit position 0 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00314"></a><span class="lineno"><a class="line" href="R4300_8h.html#a66d94b7aa6890d2e41a4e4ccf4ed5f9f"> 314</a></span> <span class="preprocessor">#define CONFIG_DC_SHFT 6 </span><span class="comment">/* shift DC to bit position 0 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00315"></a><span class="lineno"><a class="line" href="R4300_8h.html#a0ae0db9fbe4a42ea2a4d97e94e6aa2ac"> 315</a></span> <span class="preprocessor">#define CONFIG_BE_SHFT 15 </span><span class="comment">/* shift BE to bit position 0 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00316"></a><span class="lineno"> 316</span>  </div>
|
|
<div class="line"><a name="l00317"></a><span class="lineno"> 317</span> <span class="comment">/*</span></div>
|
|
<div class="line"><a name="l00318"></a><span class="lineno"> 318</span> <span class="comment"> * C0_TAGLO definitions for setting/getting cache states and physaddr bits</span></div>
|
|
<div class="line"><a name="l00319"></a><span class="lineno"> 319</span> <span class="comment"> */</span></div>
|
|
<div class="line"><a name="l00320"></a><span class="lineno"><a class="line" href="R4300_8h.html#ac17e2771e3544211262d7a20a0571c25"> 320</a></span> <span class="preprocessor">#define SADDRMASK 0xFFFFE000 </span><span class="comment">/* 31..13 -> scache paddr bits 35..17 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00321"></a><span class="lineno"><a class="line" href="R4300_8h.html#ae4cdb6453be935a22a7c016f39fdac83"> 321</a></span> <span class="preprocessor">#define SVINDEXMASK 0x00000380 </span><span class="comment">/* 9..7: prim virt index bits 14..12 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00322"></a><span class="lineno"><a class="line" href="R4300_8h.html#a5ecbbeb37774e6290a2040da7d243a7d"> 322</a></span> <span class="preprocessor">#define SSTATEMASK 0x00001c00 </span><span class="comment">/* bits 12..10 hold scache line state */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00323"></a><span class="lineno"><a class="line" href="R4300_8h.html#acc145728c84b52c04e89122b784c8f25"> 323</a></span> <span class="preprocessor">#define SINVALID 0x00000000 </span><span class="comment">/* invalid --> 000 == state 0 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00324"></a><span class="lineno"><a class="line" href="R4300_8h.html#a9ba52bf01d70113e45ab64476de5105e"> 324</a></span> <span class="preprocessor">#define SCLEANEXCL 0x00001000 </span><span class="comment">/* clean exclusive --> 100 == state 4 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00325"></a><span class="lineno"><a class="line" href="R4300_8h.html#adfc73b3fd284c228b5b45802b82b9900"> 325</a></span> <span class="preprocessor">#define SDIRTYEXCL 0x00001400 </span><span class="comment">/* dirty exclusive --> 101 == state 5 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00326"></a><span class="lineno"><a class="line" href="R4300_8h.html#a348169ef3b9dde0ec71157bf941072dc"> 326</a></span> <span class="preprocessor">#define SECC_MASK 0x0000007f </span><span class="comment">/* low 7 bits are ecc for the tag */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00327"></a><span class="lineno"><a class="line" href="R4300_8h.html#a06c1241b2016298bb1c0ea28b4d18684"> 327</a></span> <span class="preprocessor">#define SADDR_SHIFT 4 </span><span class="comment">/* shift STagLo (31..13) to 35..17 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00328"></a><span class="lineno"> 328</span>  </div>
|
|
<div class="line"><a name="l00329"></a><span class="lineno"><a class="line" href="R4300_8h.html#a6da9e8da70adb221842d04da88868bcc"> 329</a></span> <span class="preprocessor">#define PADDRMASK 0xFFFFFF00 </span><span class="comment">/* PTagLo31..8->prim paddr bits35..12 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00330"></a><span class="lineno"><a class="line" href="R4300_8h.html#af5734fb942408b5c4d45d42ab353a803"> 330</a></span> <span class="preprocessor">#define PADDR_SHIFT 4 </span><span class="comment">/* roll bits 35..12 down to 31..8 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00331"></a><span class="lineno"><a class="line" href="R4300_8h.html#ad0c27a63513f6fc708713934e4b3fca8"> 331</a></span> <span class="preprocessor">#define PSTATEMASK 0x00C0 </span><span class="comment">/* bits 7..6 hold primary line state */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00332"></a><span class="lineno"><a class="line" href="R4300_8h.html#ab0af723df73474434be1b220fc36abc7"> 332</a></span> <span class="preprocessor">#define PINVALID 0x0000 </span><span class="comment">/* invalid --> 000 == state 0 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00333"></a><span class="lineno"><a class="line" href="R4300_8h.html#ad58c60513cae907e4291b0f3c801ed7a"> 333</a></span> <span class="preprocessor">#define PCLEANEXCL 0x0080 </span><span class="comment">/* clean exclusive --> 10 == state 2 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00334"></a><span class="lineno"><a class="line" href="R4300_8h.html#a87509525a2c52dd1ee7c4ca741692760"> 334</a></span> <span class="preprocessor">#define PDIRTYEXCL 0x00C0 </span><span class="comment">/* dirty exclusive --> 11 == state 3 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00335"></a><span class="lineno"><a class="line" href="R4300_8h.html#a0744262737f0194aab0bf9da3b266c09"> 335</a></span> <span class="preprocessor">#define PPARITY_MASK 0x0001 </span><span class="comment">/* low bit is parity bit (even). */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00336"></a><span class="lineno"> 336</span>  </div>
|
|
<div class="line"><a name="l00337"></a><span class="lineno"> 337</span> <span class="comment">/*</span></div>
|
|
<div class="line"><a name="l00338"></a><span class="lineno"> 338</span> <span class="comment"> * C0_CACHE_ERR definitions.</span></div>
|
|
<div class="line"><a name="l00339"></a><span class="lineno"> 339</span> <span class="comment"> */</span></div>
|
|
<div class="line"><a name="l00340"></a><span class="lineno"><a class="line" href="R4300_8h.html#a177f2c74667e72604dc35a6b6341171f"> 340</a></span> <span class="preprocessor">#define CACHERR_ER 0x80000000 </span><span class="comment">/* 0: inst ref, 1: data ref */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00341"></a><span class="lineno"><a class="line" href="R4300_8h.html#ae511578a0bfba826ca17325bde7acd13"> 341</a></span> <span class="preprocessor">#define CACHERR_EC 0x40000000 </span><span class="comment">/* 0: primary, 1: secondary */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00342"></a><span class="lineno"><a class="line" href="R4300_8h.html#a9d986173378b48f80beebe7e6f7ec1a1"> 342</a></span> <span class="preprocessor">#define CACHERR_ED 0x20000000 </span><span class="comment">/* 1: data error */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00343"></a><span class="lineno"><a class="line" href="R4300_8h.html#aedace1592ae9f3e8fb0c8c8468b0eb7c"> 343</a></span> <span class="preprocessor">#define CACHERR_ET 0x10000000 </span><span class="comment">/* 1: tag error */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00344"></a><span class="lineno"><a class="line" href="R4300_8h.html#adde8ab26f900c8b6a50e1784fb2c01bd"> 344</a></span> <span class="preprocessor">#define CACHERR_ES 0x08000000 </span><span class="comment">/* 1: external ref, e.g. snoop*/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00345"></a><span class="lineno"><a class="line" href="R4300_8h.html#a939c65f5dae96be897c4d4034c4ed8ae"> 345</a></span> <span class="preprocessor">#define CACHERR_EE 0x04000000 </span><span class="comment">/* error on SysAD bus */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00346"></a><span class="lineno"><a class="line" href="R4300_8h.html#afa6a51d15f8903a25db0bd3f2addeb64"> 346</a></span> <span class="preprocessor">#define CACHERR_EB 0x02000000 </span><span class="comment">/* complicated, see spec. */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00347"></a><span class="lineno"><a class="line" href="R4300_8h.html#a729d1ed19d797a1f54296264277233bf"> 347</a></span> <span class="preprocessor">#define CACHERR_EI 0x01000000 </span><span class="comment">/* complicated, see spec. */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00348"></a><span class="lineno"><a class="line" href="R4300_8h.html#a3f6ff384805c95817d5b2437a2992ea6"> 348</a></span> <span class="preprocessor">#define CACHERR_SIDX_MASK 0x003ffff8 </span><span class="comment">/* secondary cache index */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00349"></a><span class="lineno"><a class="line" href="R4300_8h.html#a3f8722fd84077f2f928e725c8dd04b5f"> 349</a></span> <span class="preprocessor">#define CACHERR_PIDX_MASK 0x00000007 </span><span class="comment">/* primary cache index */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00350"></a><span class="lineno"><a class="line" href="R4300_8h.html#a97419a816a15c45283743c13e6005a41"> 350</a></span> <span class="preprocessor">#define CACHERR_PIDX_SHIFT 12 </span><span class="comment">/* bits 2..0 are paddr14..12 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00351"></a><span class="lineno"> 351</span>  </div>
|
|
<div class="line"><a name="l00352"></a><span class="lineno"> 352</span> <span class="comment">/* R4000 family supports hardware watchpoints:</span></div>
|
|
<div class="line"><a name="l00353"></a><span class="lineno"> 353</span> <span class="comment"> * C0_WATCHLO:</span></div>
|
|
<div class="line"><a name="l00354"></a><span class="lineno"> 354</span> <span class="comment"> * bits 31..3 are bits 31..3 of physaddr to watch</span></div>
|
|
<div class="line"><a name="l00355"></a><span class="lineno"> 355</span> <span class="comment"> * bit 2: reserved; must be written as 0.</span></div>
|
|
<div class="line"><a name="l00356"></a><span class="lineno"> 356</span> <span class="comment"> * bit 1: when set causes a watchpoint trap on load accesses to paddr.</span></div>
|
|
<div class="line"><a name="l00357"></a><span class="lineno"> 357</span> <span class="comment"> * bit 0: when set traps on stores to paddr;</span></div>
|
|
<div class="line"><a name="l00358"></a><span class="lineno"> 358</span> <span class="comment"> * C0_WATCHHI</span></div>
|
|
<div class="line"><a name="l00359"></a><span class="lineno"> 359</span> <span class="comment"> * bits 31..4 are reserved and must be written as zeros.</span></div>
|
|
<div class="line"><a name="l00360"></a><span class="lineno"> 360</span> <span class="comment"> * bits 3..0 are bits 35..32 of the physaddr to watch</span></div>
|
|
<div class="line"><a name="l00361"></a><span class="lineno"> 361</span> <span class="comment"> */</span></div>
|
|
<div class="line"><a name="l00362"></a><span class="lineno"><a class="line" href="R4300_8h.html#a0a8e20512cbeb46cf186698b59425afd"> 362</a></span> <span class="preprocessor">#define WATCHLO_WTRAP 0x00000001</span></div>
|
|
<div class="line"><a name="l00363"></a><span class="lineno"><a class="line" href="R4300_8h.html#a552a19ef457161fb18082a5ff0a44bd6"> 363</a></span> <span class="preprocessor">#define WATCHLO_RTRAP 0x00000002</span></div>
|
|
<div class="line"><a name="l00364"></a><span class="lineno"><a class="line" href="R4300_8h.html#ac976023e5f03d2c48a90e1d3af2cb9da"> 364</a></span> <span class="preprocessor">#define WATCHLO_ADDRMASK 0xfffffff8</span></div>
|
|
<div class="line"><a name="l00365"></a><span class="lineno"><a class="line" href="R4300_8h.html#a55fdad7366f8ba76401505cac62053ce"> 365</a></span> <span class="preprocessor">#define WATCHLO_VALIDMASK 0xfffffffb</span></div>
|
|
<div class="line"><a name="l00366"></a><span class="lineno"><a class="line" href="R4300_8h.html#aaaf948db8a7b7a221d0e56e552a084c3"> 366</a></span> <span class="preprocessor">#define WATCHHI_VALIDMASK 0x0000000f</span></div>
|
|
<div class="line"><a name="l00367"></a><span class="lineno"> 367</span>  </div>
|
|
<div class="line"><a name="l00368"></a><span class="lineno"> 368</span> <span class="comment">/*</span></div>
|
|
<div class="line"><a name="l00369"></a><span class="lineno"> 369</span> <span class="comment"> * Coprocessor 0 registers</span></div>
|
|
<div class="line"><a name="l00370"></a><span class="lineno"> 370</span> <span class="comment"> */</span></div>
|
|
<div class="line"><a name="l00371"></a><span class="lineno"> 371</span> <span class="preprocessor">#ifdef _LANGUAGE_ASSEMBLY</span></div>
|
|
<div class="line"><a name="l00372"></a><span class="lineno"> 372</span> <span class="preprocessor">#define C0_INX $0</span></div>
|
|
<div class="line"><a name="l00373"></a><span class="lineno"> 373</span> <span class="preprocessor">#define C0_RAND $1</span></div>
|
|
<div class="line"><a name="l00374"></a><span class="lineno"> 374</span> <span class="preprocessor">#define C0_ENTRYLO0 $2</span></div>
|
|
<div class="line"><a name="l00375"></a><span class="lineno"> 375</span> <span class="preprocessor">#define C0_ENTRYLO1 $3</span></div>
|
|
<div class="line"><a name="l00376"></a><span class="lineno"> 376</span> <span class="preprocessor">#define C0_CONTEXT $4</span></div>
|
|
<div class="line"><a name="l00377"></a><span class="lineno"> 377</span> <span class="preprocessor">#define C0_PAGEMASK $5 </span><span class="comment">/* page mask */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00378"></a><span class="lineno"> 378</span> <span class="preprocessor">#define C0_WIRED $6 </span><span class="comment">/* # wired entries in tlb */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00379"></a><span class="lineno"> 379</span> <span class="preprocessor">#define C0_BADVADDR $8</span></div>
|
|
<div class="line"><a name="l00380"></a><span class="lineno"> 380</span> <span class="preprocessor">#define C0_COUNT $9 </span><span class="comment">/* free-running counter */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00381"></a><span class="lineno"> 381</span> <span class="preprocessor">#define C0_ENTRYHI $10</span></div>
|
|
<div class="line"><a name="l00382"></a><span class="lineno"> 382</span> <span class="preprocessor">#define C0_SR $12</span></div>
|
|
<div class="line"><a name="l00383"></a><span class="lineno"> 383</span> <span class="preprocessor">#define C0_CAUSE $13</span></div>
|
|
<div class="line"><a name="l00384"></a><span class="lineno"> 384</span> <span class="preprocessor">#define C0_EPC $14</span></div>
|
|
<div class="line"><a name="l00385"></a><span class="lineno"> 385</span> <span class="preprocessor">#define C0_PRID $15 </span><span class="comment">/* revision identifier */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00386"></a><span class="lineno"> 386</span> <span class="preprocessor">#define C0_COMPARE $11 </span><span class="comment">/* counter comparison reg. */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00387"></a><span class="lineno"> 387</span> <span class="preprocessor">#define C0_CONFIG $16 </span><span class="comment">/* hardware configuration */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00388"></a><span class="lineno"> 388</span> <span class="preprocessor">#define C0_LLADDR $17 </span><span class="comment">/* load linked address */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00389"></a><span class="lineno"> 389</span> <span class="preprocessor">#define C0_WATCHLO $18 </span><span class="comment">/* watchpoint */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00390"></a><span class="lineno"> 390</span> <span class="preprocessor">#define C0_WATCHHI $19 </span><span class="comment">/* watchpoint */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00391"></a><span class="lineno"> 391</span> <span class="preprocessor">#define C0_ECC $26 </span><span class="comment">/* S-cache ECC and primary parity */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00392"></a><span class="lineno"> 392</span> <span class="preprocessor">#define C0_CACHE_ERR $27 </span><span class="comment">/* cache error status */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00393"></a><span class="lineno"> 393</span> <span class="preprocessor">#define C0_TAGLO $28 </span><span class="comment">/* cache operations */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00394"></a><span class="lineno"> 394</span> <span class="preprocessor">#define C0_TAGHI $29 </span><span class="comment">/* cache operations */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00395"></a><span class="lineno"> 395</span> <span class="preprocessor">#define C0_ERROR_EPC $30 </span><span class="comment">/* ECC error prg. counter */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00396"></a><span class="lineno"> 396</span>  </div>
|
|
<div class="line"><a name="l00397"></a><span class="lineno"> 397</span> <span class="preprocessor"># else </span><span class="comment">/* ! _LANGUAGE_ASSEMBLY */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00398"></a><span class="lineno"> 398</span>  </div>
|
|
<div class="line"><a name="l00399"></a><span class="lineno"><a class="line" href="R4300_8h.html#adf3ddc1d86fa0d3798e4c01729435382"> 399</a></span> <span class="preprocessor">#define C0_INX 0</span></div>
|
|
<div class="line"><a name="l00400"></a><span class="lineno"><a class="line" href="R4300_8h.html#a9ebb13f27da459fd6c6e2555f8ea0b08"> 400</a></span> <span class="preprocessor">#define C0_RAND 1</span></div>
|
|
<div class="line"><a name="l00401"></a><span class="lineno"><a class="line" href="R4300_8h.html#a97f3f5928e416b3a21678f137289ade2"> 401</a></span> <span class="preprocessor">#define C0_ENTRYLO0 2</span></div>
|
|
<div class="line"><a name="l00402"></a><span class="lineno"><a class="line" href="R4300_8h.html#a513f8301dbcc28a0b131c9485e4fbb3f"> 402</a></span> <span class="preprocessor">#define C0_ENTRYLO1 3</span></div>
|
|
<div class="line"><a name="l00403"></a><span class="lineno"><a class="line" href="R4300_8h.html#a5073ae69d32cbda61fd2ee300a8fab64"> 403</a></span> <span class="preprocessor">#define C0_CONTEXT 4</span></div>
|
|
<div class="line"><a name="l00404"></a><span class="lineno"><a class="line" href="R4300_8h.html#ad3c2f5929086efee5a61d7966717543e"> 404</a></span> <span class="preprocessor">#define C0_PAGEMASK 5 </span><span class="comment">/* page mask */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00405"></a><span class="lineno"><a class="line" href="R4300_8h.html#a18f4486fb4e38f85ab85df53a1bb0161"> 405</a></span> <span class="preprocessor">#define C0_WIRED 6 </span><span class="comment">/* # wired entries in tlb */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00406"></a><span class="lineno"><a class="line" href="R4300_8h.html#ae3a870fd9999348c1704ae15c9f90815"> 406</a></span> <span class="preprocessor">#define C0_BADVADDR 8</span></div>
|
|
<div class="line"><a name="l00407"></a><span class="lineno"><a class="line" href="R4300_8h.html#ab326a844722de29e1696afc52cf9d1b1"> 407</a></span> <span class="preprocessor">#define C0_COUNT 9 </span><span class="comment">/* free-running counter */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00408"></a><span class="lineno"><a class="line" href="R4300_8h.html#ac3941b540b0419788328990d7b8b7342"> 408</a></span> <span class="preprocessor">#define C0_ENTRYHI 10</span></div>
|
|
<div class="line"><a name="l00409"></a><span class="lineno"><a class="line" href="R4300_8h.html#ad08be68adf81675768214e01ca7d1291"> 409</a></span> <span class="preprocessor">#define C0_SR 12</span></div>
|
|
<div class="line"><a name="l00410"></a><span class="lineno"><a class="line" href="R4300_8h.html#abd462e0cd80cc5aa92d65a0f474f6f07"> 410</a></span> <span class="preprocessor">#define C0_CAUSE 13</span></div>
|
|
<div class="line"><a name="l00411"></a><span class="lineno"><a class="line" href="R4300_8h.html#a8bc09513b6b3182942f4aae7e65e2a1d"> 411</a></span> <span class="preprocessor">#define C0_EPC 14</span></div>
|
|
<div class="line"><a name="l00412"></a><span class="lineno"><a class="line" href="R4300_8h.html#a5e0934a901aa42ee96a3deb2dc96bd39"> 412</a></span> <span class="preprocessor">#define C0_PRID 15 </span><span class="comment">/* revision identifier */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00413"></a><span class="lineno"><a class="line" href="R4300_8h.html#a68e611fbdf07ec157e560192ece8744e"> 413</a></span> <span class="preprocessor">#define C0_COMPARE 11 </span><span class="comment">/* counter comparison reg. */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00414"></a><span class="lineno"><a class="line" href="R4300_8h.html#a3a4ee4854636c95eac8d7ce5e7e9328a"> 414</a></span> <span class="preprocessor">#define C0_CONFIG 16 </span><span class="comment">/* hardware configuration */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00415"></a><span class="lineno"><a class="line" href="R4300_8h.html#a4f516a43ceef29cf49fa16514015046b"> 415</a></span> <span class="preprocessor">#define C0_LLADDR 17 </span><span class="comment">/* load linked address */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00416"></a><span class="lineno"><a class="line" href="R4300_8h.html#acca33a10afc5dbc8cc343e124a581fcf"> 416</a></span> <span class="preprocessor">#define C0_WATCHLO 18 </span><span class="comment">/* watchpoint */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00417"></a><span class="lineno"><a class="line" href="R4300_8h.html#a0209ed3f34b354baebbe5e9d61fd1b79"> 417</a></span> <span class="preprocessor">#define C0_WATCHHI 19 </span><span class="comment">/* watchpoint */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00418"></a><span class="lineno"><a class="line" href="R4300_8h.html#a068ee9b11afd8abcefadf6b67d9996ef"> 418</a></span> <span class="preprocessor">#define C0_ECC 26 </span><span class="comment">/* S-cache ECC and primary parity */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00419"></a><span class="lineno"><a class="line" href="R4300_8h.html#a4f4bdde8fbea873e59c27c242f852c24"> 419</a></span> <span class="preprocessor">#define C0_CACHE_ERR 27 </span><span class="comment">/* cache error status */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00420"></a><span class="lineno"><a class="line" href="R4300_8h.html#a83ab1e47995139e649ac7bf8c6909048"> 420</a></span> <span class="preprocessor">#define C0_TAGLO 28 </span><span class="comment">/* cache operations */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00421"></a><span class="lineno"><a class="line" href="R4300_8h.html#a68a61e68b64f7f05e98444463ab7be5e"> 421</a></span> <span class="preprocessor">#define C0_TAGHI 29 </span><span class="comment">/* cache operations */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00422"></a><span class="lineno"><a class="line" href="R4300_8h.html#a5b85b3d016e7ff7cf029672fe60c1a29"> 422</a></span> <span class="preprocessor">#define C0_ERROR_EPC 30 </span><span class="comment">/* ECC error prg. counter */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00423"></a><span class="lineno"> 423</span>  </div>
|
|
<div class="line"><a name="l00424"></a><span class="lineno"> 424</span> <span class="preprocessor">#endif </span><span class="comment">/* _LANGUAGE_ASSEMBLY */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00425"></a><span class="lineno"> 425</span>  </div>
|
|
<div class="line"><a name="l00426"></a><span class="lineno"> 426</span> <span class="comment">/*</span></div>
|
|
<div class="line"><a name="l00427"></a><span class="lineno"> 427</span> <span class="comment"> * floating-point status register </span></div>
|
|
<div class="line"><a name="l00428"></a><span class="lineno"> 428</span> <span class="comment"> */</span></div>
|
|
<div class="line"><a name="l00429"></a><span class="lineno"><a class="line" href="R4300_8h.html#a2a9cc9b28cec2b0310fd9bffa4f7755f"> 429</a></span> <span class="preprocessor">#define FPCSR_FS 0x01000000 </span><span class="comment">/* flush denorm to zero */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00430"></a><span class="lineno"><a class="line" href="R4300_8h.html#afa1b039e956bd2168c223ae5070d65e4"> 430</a></span> <span class="preprocessor">#define FPCSR_C 0x00800000 </span><span class="comment">/* condition bit */</span><span class="preprocessor"> </span></div>
|
|
<div class="line"><a name="l00431"></a><span class="lineno"><a class="line" href="R4300_8h.html#acb314d0fc092524d5250e08ffbc2edfe"> 431</a></span> <span class="preprocessor">#define FPCSR_CE 0x00020000 </span><span class="comment">/* cause: unimplemented operation */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00432"></a><span class="lineno"><a class="line" href="R4300_8h.html#abf5f7ae48948ac9309e1353f3cf4b2cb"> 432</a></span> <span class="preprocessor">#define FPCSR_CV 0x00010000 </span><span class="comment">/* cause: invalid operation */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00433"></a><span class="lineno"><a class="line" href="R4300_8h.html#a2b2800255512c5bb867b18c7e7993f8a"> 433</a></span> <span class="preprocessor">#define FPCSR_CZ 0x00008000 </span><span class="comment">/* cause: division by zero */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00434"></a><span class="lineno"><a class="line" href="R4300_8h.html#a366a8950cb2fe11bf6a75494abaff06f"> 434</a></span> <span class="preprocessor">#define FPCSR_CO 0x00004000 </span><span class="comment">/* cause: overflow */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00435"></a><span class="lineno"><a class="line" href="R4300_8h.html#a9425fdeed938f712fd7e8883dc92a17c"> 435</a></span> <span class="preprocessor">#define FPCSR_CU 0x00002000 </span><span class="comment">/* cause: underflow */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00436"></a><span class="lineno"><a class="line" href="R4300_8h.html#a00087fec1f8753ce2809e02792f67964"> 436</a></span> <span class="preprocessor">#define FPCSR_CI 0x00001000 </span><span class="comment">/* cause: inexact operation */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00437"></a><span class="lineno"><a class="line" href="R4300_8h.html#a43a0570cb4fac927dfa2f46d354d37b0"> 437</a></span> <span class="preprocessor">#define FPCSR_EV 0x00000800 </span><span class="comment">/* enable: invalid operation */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00438"></a><span class="lineno"><a class="line" href="R4300_8h.html#aaee932c3533c2c151cfc56e62cb8f3d3"> 438</a></span> <span class="preprocessor">#define FPCSR_EZ 0x00000400 </span><span class="comment">/* enable: division by zero */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00439"></a><span class="lineno"><a class="line" href="R4300_8h.html#a7de0e4ba6dac66e36ec076c53efde596"> 439</a></span> <span class="preprocessor">#define FPCSR_EO 0x00000200 </span><span class="comment">/* enable: overflow */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00440"></a><span class="lineno"><a class="line" href="R4300_8h.html#a0461cff24b9e4e884b86396497424eab"> 440</a></span> <span class="preprocessor">#define FPCSR_EU 0x00000100 </span><span class="comment">/* enable: underflow */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00441"></a><span class="lineno"><a class="line" href="R4300_8h.html#aedc34df01c6df6a0f61b5a92c7e2d44b"> 441</a></span> <span class="preprocessor">#define FPCSR_EI 0x00000080 </span><span class="comment">/* enable: inexact operation */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00442"></a><span class="lineno"><a class="line" href="R4300_8h.html#acf3f2d222e99d77efe98de2563821b32"> 442</a></span> <span class="preprocessor">#define FPCSR_FV 0x00000040 </span><span class="comment">/* flag: invalid operation */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00443"></a><span class="lineno"><a class="line" href="R4300_8h.html#a2cb640d1a3b12b6c5c73f60145542072"> 443</a></span> <span class="preprocessor">#define FPCSR_FZ 0x00000020 </span><span class="comment">/* flag: division by zero */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00444"></a><span class="lineno"><a class="line" href="R4300_8h.html#a5c0a05faef40fc3d321b4bed7b006305"> 444</a></span> <span class="preprocessor">#define FPCSR_FO 0x00000010 </span><span class="comment">/* flag: overflow */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00445"></a><span class="lineno"><a class="line" href="R4300_8h.html#a058c86aa3774258705ab13ec4e41d8e8"> 445</a></span> <span class="preprocessor">#define FPCSR_FU 0x00000008 </span><span class="comment">/* flag: underflow */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00446"></a><span class="lineno"><a class="line" href="R4300_8h.html#a4c4884579f8be5246d8a2ca5b386a931"> 446</a></span> <span class="preprocessor">#define FPCSR_FI 0x00000004 </span><span class="comment">/* flag: inexact operation */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00447"></a><span class="lineno"><a class="line" href="R4300_8h.html#a29469b1fe9d7b36a9bdf590f062c8834"> 447</a></span> <span class="preprocessor">#define FPCSR_RM_MASK 0x00000003 </span><span class="comment">/* rounding mode mask */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00448"></a><span class="lineno"><a class="line" href="R4300_8h.html#a52e37ceb1757f071350548acabee6707"> 448</a></span> <span class="preprocessor">#define FPCSR_RM_RN 0x00000000 </span><span class="comment">/* round to nearest */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00449"></a><span class="lineno"><a class="line" href="R4300_8h.html#a57a383023950ddc44e2192a63246604b"> 449</a></span> <span class="preprocessor">#define FPCSR_RM_RZ 0x00000001 </span><span class="comment">/* round to zero */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00450"></a><span class="lineno"><a class="line" href="R4300_8h.html#a4f41d7aa952c39826dad887235e9deab"> 450</a></span> <span class="preprocessor">#define FPCSR_RM_RP 0x00000002 </span><span class="comment">/* round to positive infinity */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00451"></a><span class="lineno"><a class="line" href="R4300_8h.html#a09b12d38bb02cac90d9d4b390d917a28"> 451</a></span> <span class="preprocessor">#define FPCSR_RM_RM 0x00000003 </span><span class="comment">/* round to negative infinity */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00452"></a><span class="lineno"> 452</span>  </div>
|
|
<div class="line"><a name="l00453"></a><span class="lineno"> 453</span> <span class="preprocessor">#endif </span><span class="comment">/* __R4300_H */</span><span class="preprocessor"></span></div>
|
|
<div class="ttc" id="aultratypes_8h_html"><div class="ttname"><a href="ultratypes_8h.html">ultratypes.h</a></div></div>
|
|
</div><!-- fragment --></div><!-- contents -->
|
|
</div><!-- doc-content -->
|
|
<!-- start footer part -->
|
|
<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
|
|
<ul>
|
|
<li class="navelem"><a class="el" href="dir_d44c64559bbebec7f509842c48db8b23.html">include</a></li><li class="navelem"><a class="el" href="dir_83efb4269fa89047a37e895c24f65331.html">PR</a></li><li class="navelem"><a class="el" href="R4300_8h.html">R4300.h</a></li>
|
|
<li class="footer">Generated by <a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.9.1 </li>
|
|
</ul>
|
|
</div>
|
|
</body>
|
|
</html>
|