diff --git a/include/PR/hardware.h b/include/PR/hardware.h
index 04fcc50721..d911f8be40 100644
--- a/include/PR/hardware.h
+++ b/include/PR/hardware.h
@@ -3,25 +3,6 @@
 
 // TODO: not real libultra header. Refactor to R4300.h
 
-// Segment Wrapper
-// Uncached RDRAM
-#define KSEG1 0xA0000000 // 0xA0000000 - 0xBFFFFFFF  Physical memory, uncached, unmapped
-#define RDRAM_UNCACHED KSEG1
-
-// Cached RDRAM
-#define KSEG0 0x80000000 // 0x80000000 - 0x9FFFFFFF  Physical memory, cached, unmapped
-#define RDRAM_CACHED KSEG0
-
-#define AI_DRAM_ADDR_REG   0x04500000
-#define AI_LEN_REG         0x04500004
-#define AI_CONTROL_REG     0x04500008
-#define AI_STATUS_REG      0x0450000C
-#define AI_DACRATE_REG     0x04500010
-#define AI_BITRATE_REG     0x04500014
-
-#define AI_STATUS_AI_BUSY  (1 << 30)
-#define AI_STATUS_AI_FULL  (1 << 31)
-
 #define VI_STATUS_REG          0x04400000
 #define VI_CONTROL_REG         0x04400000
 #define VI_ORIGIN_REG          0x04400004
@@ -46,12 +27,6 @@
 #define VI_X_SCALE_REG         0x04400030 //VI x-scale
 #define VI_Y_SCALE_REG         0x04400034 //VI y-scale
 
-#define SP_IMEM_START  0x04001000
-#define SP_IMEM_SIZE   0x1000
-
-#define SP_DMEM_START  0x04000000
-#define SP_DMEM_SIZE   0x1000
-
 #define TMEM_SIZE 0x1000
 
 #define SP_MEM_ADDR_REG   0x04040000
@@ -96,23 +71,4 @@
 #define SI_STATUS_DMA_ERROR     (1 << 3)
 #define SI_STATUS_INTERRUPT     (1 << 12)
 
-#define PIF_RAM_START  0x1FC007C0
-#define PIF_RAM_SIZE   0x40
-
-#define MI_INIT_MODE_REG  0x04300000
-#define MI_MODE_REG       MI_INIT_MODE_REG
-#define MI_VERSION_REG    0x04300004
-#define MI_INTR_REG       0x04300008
-#define MI_INTR_MASK_REG  0x0430000C
-
-/* Interrupt pending bits */
-#define	CAUSE_IP8  0x00008000  /* External level 8 pending - COMPARE */
-#define	CAUSE_IP7  0x00004000  /* External level 7 pending - INT4 */
-#define	CAUSE_IP6  0x00002000  /* External level 6 pending - INT3 */
-#define	CAUSE_IP5  0x00001000  /* External level 5 pending - INT2 */
-#define	CAUSE_IP4  0x00000800  /* External level 4 pending - INT1 */
-#define	CAUSE_IP3  0x00000400  /* External level 3 pending - INT0 */
-#define	CAUSE_SW2  0x00000200  /* Software level 2 pending */
-#define	CAUSE_SW1  0x00000100  /* Software level 1 pending */
-
 #endif
diff --git a/include/PR/rcp.h b/include/PR/rcp.h
index 1c97c64e3f..b8d7720a07 100644
--- a/include/PR/rcp.h
+++ b/include/PR/rcp.h
@@ -1,16 +1,94 @@
 #ifndef PR_RCP_H
 #define PR_RCP_H
 
+/**
+ * PIF Physical memory map (total size = 2 KB)
+ *
+ *            Size      Description     Mode
+ *  1FC007FF    +-------+-----------------+-----+
+ *              |  64 B | JoyChannel RAM  | R/W |
+ *  1FC007C0    +-------+-----------------+-----+
+ *              |1984 B |    Boot ROM     |  *  |  * = Reserved
+ *  1FC00000    +-------+-----------------+-----+
+ */
+#define PIF_ROM_START   0x1FC00000
+#define PIF_ROM_END     0x1FC007BF
+#define PIF_RAM_START   0x1FC007C0
+#define PIF_RAM_END     0x1FC007FF
+
+
 #define VI_NTSC_CLOCK       48681812        /* Hz = 48.681812 MHz */
 #define VI_PAL_CLOCK        49656530        /* Hz = 49.656530 MHz */
 #define VI_MPAL_CLOCK       48628316        /* Hz = 48.628316 MHz */
 
+/**
+ * Audio Interface (AI) Registers
+ */
+#define AI_BASE_REG     0x04500000
+
+/* AI DRAM address (W): [23:0] starting RDRAM address (8B-aligned) */
+#define AI_DRAM_ADDR_REG    (AI_BASE_REG + 0x00)    /* R0: DRAM address */
+
+/* AI length (R/W): [14:0] transfer length (v1.0) - Bottom 3 bits are ignored */
+/*                  [17:0] transfer length (v2.0) - Bottom 3 bits are ignored */
+#define AI_LEN_REG          (AI_BASE_REG + 0x04)    /* R1: Length */
+
+/* AI control (W): [0] DMA enable - if LSB == 1, DMA is enabled */
+#define AI_CONTROL_REG      (AI_BASE_REG + 0x08)    /* R2: DMA Control */
+
+/* Value for control register */
+#define AI_CONTROL_DMA_ON   1   /* LSB = 1: DMA enable*/
+#define AI_CONTROL_DMA_OFF  0   /* LSB = 1: DMA enable*/
+
+/* 
+ * AI status (R): [31]/[0] ai_full (addr & len buffer full), [30] ai_busy 
+ *        Note that a 1->0 transition in ai_full will set interrupt
+ *           (W): clear audio interrupt 
+ */
+#define AI_STATUS_REG       (AI_BASE_REG + 0x0C)    /* R3: Status */
+
+/* Value for status register */
+#define AI_STATUS_FIFO_FULL (1 << 31)
+#define AI_STATUS_DMA_BUSY  (1 << 30)
+
+/* 
+ * AI DAC sample period register (W): [13:0] dac rate 
+ *   - vid_clock/(dperiod + 1) is the DAC sample rate
+ *   - (dperiod + 1) >= 66 * (aclockhp + 1) must be true
+ */
+#define AI_DACRATE_REG      (AI_BASE_REG + 0x10)    /* R4: DAC rate 14-lsb*/
+
+/* DAC rate = video clock / audio frequency
+ *   - DAC rate >= (66 * Bit rate) must be true
+ */
+#define AI_MAX_DAC_RATE 16384   /* 14-bit+1 */
+#define AI_MIN_DAC_RATE 132
+
+/* 
+ * AI bit rate (W): [3:0] bit rate (abus clock half period register - aclockhp)
+ *   - vid_clock/(2 * (aclockhp + 1)) is the DAC clock rate
+ *   - The abus clock stops if aclockhp is zero
+ */
+#define AI_BITRATE_REG      (AI_BASE_REG + 0x14)    /* R5: Bit rate 4-lsb */
+
+/* Bit rate <= (DAC rate / 66) */
+#define AI_MAX_BIT_RATE 16      /* 4-bit+1 */
+#define AI_MIN_BIT_RATE 2
+
 #define DEVICE_TYPE_CART    0   /* ROM cartridge */
 #define DEVICE_TYPE_BULK    1   /* ROM bulk */
 #define DEVICE_TYPE_64DD    2   /* 64 Disk Drive */
 #define DEVICE_TYPE_SRAM    3   /* SRAM */
 #define DEVICE_TYPE_INIT    7   /* initial value */
 
+/**
+ * Signal Processor (SP) Memory
+ */
+#define SP_DMEM_START   0x04000000
+#define SP_DMEM_END     0x04000FFF
+#define SP_IMEM_START   0x04001000
+#define SP_IMEM_END     0x04001FFF
+
 #define CHNL_ERR_NORESP     0x80    /* Bit 7 (Rx): No response error */
 #define CHNL_ERR_OVERRUN    0x40    /* Bit 6 (Rx): Overrun error */
 #define CHNL_ERR_FRAME      0x80    /* Bit 7 (Tx): Frame error */
diff --git a/include/macros.h b/include/macros.h
index 46932a0a64..cda85f6b2c 100644
--- a/include/macros.h
+++ b/include/macros.h
@@ -22,9 +22,9 @@
 #define ARRAY_COUNT_2D(arr) (ARRAY_COUNT(arr) * ARRAY_COUNT(arr[0]))
 
 // TODO: After uintptr_t cast change should have an AVOID_UB target that just toggles the KSEG0 bit in the address rather than add/sub 0x80000000
-#define PHYSICAL_TO_VIRTUAL(addr) ((uintptr_t)(addr) + RDRAM_CACHED)
-#define VIRTUAL_TO_PHYSICAL(addr) (uintptr_t)((u8*)(addr) - RDRAM_CACHED)
-#define SEGMENTED_TO_VIRTUAL(addr) (void*)(PHYSICAL_TO_VIRTUAL(gSegments[SEGMENT_NUMBER(addr)]) + SEGMENT_OFFSET(addr))
+#define PHYSICAL_TO_VIRTUAL(addr) ((uintptr_t)(addr) + K0BASE)
+#define VIRTUAL_TO_PHYSICAL(addr) OS_K0_TO_PHYSICAL(addr)
+#define SEGMENTED_TO_VIRTUAL(addr) (void*)((uintptr_t)PHYSICAL_TO_VIRTUAL(gSegments[SEGMENT_NUMBER(addr)]) + SEGMENT_OFFSET(addr))
 
 #define GET_ACTIVE_CAM(play) ((play)->cameraPtrs[(play)->activeCamId])
 
diff --git a/src/audio/lib/aisetnextbuf.c b/src/audio/lib/aisetnextbuf.c
index 970285e378..57f8ade57a 100644
--- a/src/audio/lib/aisetnextbuf.c
+++ b/src/audio/lib/aisetnextbuf.c
@@ -19,7 +19,7 @@ s32 osAiSetNextBuffer(void* buf, u32 size) {
 
     // Originally a call to __osAiDeviceBusy
     status = IO_READ(AI_STATUS_REG);
-    if (status & AI_STATUS_AI_FULL) {
+    if (status & AI_STATUS_FIFO_FULL) {
         return -1;
     }
 
diff --git a/src/code/z_lib.c b/src/code/z_lib.c
index 553c5d1338..2c65874eda 100644
--- a/src/code/z_lib.c
+++ b/src/code/z_lib.c
@@ -732,6 +732,6 @@ void* Lib_PhysicalToVirtual(void* ptr) {
     if (ptr == NULL) {
         return NULL;
     } else {
-        return (void*)PHYSICAL_TO_VIRTUAL(ptr);
+        return OS_PHYSICAL_TO_K0(ptr);
     }
 }
diff --git a/src/libultra/flash/osFlash.c b/src/libultra/flash/osFlash.c
index 139c1526de..33878f25fa 100644
--- a/src/libultra/flash/osFlash.c
+++ b/src/libultra/flash/osFlash.c
@@ -22,7 +22,7 @@ u32 osFlashGetAddr(u32 pageNum) {
 }
 
 OSPiHandle* osFlashReInit(u8 latency, u8 pulse, u8 pageSize, u8 relDuration, u32 start) {
-    __osFlashHandler.baseAddress = RDRAM_UNCACHED | start;
+    __osFlashHandler.baseAddress = PHYS_TO_K1(start);
     __osFlashHandler.type++;
     __osFlashHandler.latency = latency;
     __osFlashHandler.pulse = pulse;
@@ -34,7 +34,7 @@ OSPiHandle* osFlashReInit(u8 latency, u8 pulse, u8 pageSize, u8 relDuration, u32
 }
 
 void osFlashChange(u32 flashNum) {
-    __osFlashHandler.baseAddress = RDRAM_UNCACHED | (FRAM_STATUS_REGISTER + (flashNum << 17));
+    __osFlashHandler.baseAddress = PHYS_TO_K1(FRAM_STATUS_REGISTER + (flashNum << 17));
     __osFlashHandler.type = 8 + flashNum;
 
     return;
@@ -46,12 +46,12 @@ OSPiHandle* osFlashInit(void) {
 
     osCreateMesgQueue(&__osFlashMessageQ, &__osFlashMsgBuf, 1);
 
-    if (__osFlashHandler.baseAddress == (RDRAM_UNCACHED | FRAM_BASE_ADDRESS)) {
+    if (__osFlashHandler.baseAddress == PHYS_TO_K1(FRAM_BASE_ADDRESS)) {
         return &__osFlashHandler;
     }
 
     __osFlashHandler.type = 8;
-    __osFlashHandler.baseAddress = (RDRAM_UNCACHED | FRAM_BASE_ADDRESS);
+    __osFlashHandler.baseAddress = PHYS_TO_K1(FRAM_BASE_ADDRESS);
     __osFlashHandler.latency = 5;
     __osFlashHandler.pulse = 12;
     __osFlashHandler.pageSize = 15;
diff --git a/src/libultra/os/initialize.c b/src/libultra/os/initialize.c
index 16f5402df5..fdf420ee92 100644
--- a/src/libultra/os/initialize.c
+++ b/src/libultra/os/initialize.c
@@ -74,7 +74,7 @@ void __osInitialize_common(void) {
         while (true) {}
     }
 
-    IO_WRITE(AI_CONTROL_REG, 1);
+    IO_WRITE(AI_CONTROL_REG, AI_CONTROL_DMA_ON);
     IO_WRITE(AI_DACRATE_REG, 0x3FFF);
     IO_WRITE(AI_BITRATE_REG, 0xF);
 }
diff --git a/src/overlays/fbdemos/ovl_fbdemo_wipe5/z_fbdemo_wipe5.c b/src/overlays/fbdemos/ovl_fbdemo_wipe5/z_fbdemo_wipe5.c
index b34dc30d25..ee8aa689f9 100644
--- a/src/overlays/fbdemos/ovl_fbdemo_wipe5/z_fbdemo_wipe5.c
+++ b/src/overlays/fbdemos/ovl_fbdemo_wipe5/z_fbdemo_wipe5.c
@@ -5,6 +5,7 @@
  */
 
 #include "global.h"
+#include "PR/gs2dex.h"
 #include "sys_cfb.h"
 #include "z_fbdemo_wipe5.h"