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Merge remote-tracking branch 'upstream/master' into ultracleanup2

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This commit is contained in:
angie
2023-09-19 14:58:45 -03:00
parent b0c49f51c2 fa71fbeaab
commit 24aea7cafd
150 changed files with 3629 additions and 1439 deletions
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include/PR/os_flash.h
+29
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@@ -4,6 +4,35 @@
#include "ultratypes.h"
#include "os_pi.h"
#define FLASH_START_ADDR 0x08000000 // FRAM Base Address in Cart Memory
#define FLASH_SIZE 0x20000
#define FLASH_LATENCY 0x5
#define FLASH_PULSE 0x0C
#define FLASH_PAGE_SIZE 0xF
#define FLASH_REL_DURATION 0x2
#define DEVICE_TYPE_FLASH 8
/* OLD_FLASH is MX_PROTO_A, MX_A and MX_C */
#define OLD_FLASH 0
/* NEW_FLASH is MX_B_AND_D and MATSUSHITA flash */
#define NEW_FLASH 1
#define FLASH_STATUS_ERASE_BUSY 2
#define FLASH_STATUS_ERASE_OK 0
#define FLASH_STATUS_ERASE_ERROR -1
#define FLASH_STATUS_WRITE_BUSY 1
#define FLASH_STATUS_WRITE_OK 0
#define FLASH_STATUS_WRITE_ERROR -1
#define FLASH_VERSION_MX_PROTO_A 0x00C20000
#define FLASH_VERSION_MX_A 0x00C20001
#define FLASH_VERSION_MX_C 0x00C2001E
#define FLASH_VERSION_MX_B_AND_D 0x00C2001D
#define FLASH_VERSION_MEI 0x003200F1
OSPiHandle* osFlashReInit(u8 latency, u8 pulse, u8 pageSize, u8 relDuration, u32 start);
OSPiHandle* osFlashInit(void);
include/PR/os_internal_flash.h
+27
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@@ -0,0 +1,27 @@
#ifndef PR_OS_INTERNAL_FLASH_H
#define PR_OS_INTERNAL_FLASH_H
#include "os_flash.h"
#define FLASH_BLOCK_SIZE 128
#define FLASH_CMD_REG 0x10000 // Located at 0x08010000 on the Cart
/* set whole chip erase mode */
#define FLASH_CMD_CHIP_ERASE 0x3C000000
/* set sector erase mode */
#define FLASH_CMD_SECTOR_ERASE 0x4B000000
/* do erasure */
#define FLASH_CMD_EXECUTE_ERASE 0x78000000
/* program selected page */
#define FLASH_CMD_PROGRAM_PAGE 0xA5000000
/* set page program mode */
#define FLASH_CMD_PAGE_PROGRAM 0xB4000000
/* set status mode */
#define FLASH_CMD_STATUS 0xD2000000
/* set silicon id mode */
#define FLASH_CMD_ID 0xE1000000
/* set read mode */
#define FLASH_CMD_READ_ARRAY 0xF0000000
#endif
include/PR/os_internal_reg.h
+2 -2
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@@ -1,5 +1,5 @@
#ifndef PR_OS_INTERNAL_REG
#define PR_OS_INTERNAL_REG
#ifndef PR_OS_INTERNAL_REG_H
#define PR_OS_INTERNAL_REG_H
#include "ultratypes.h"
#include "os_exception.h"
include/PR/os_internal_rsp.h
+5 -7
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@@ -1,14 +1,12 @@
#ifndef PR_RSP_H
#define PR_RSP_H
#ifndef PR_OS_INTERNAL_RSP_H
#define PR_OS_INTERNAL_RSP_H
#include "ultratypes.h"
#include "libc/stddef.h"
u32 __osSpGetStatus(void);
void __osSpSetStatus(u32 data);
s32 __osSpSetPc(u32 pc);
s32 __osSpRawStartDma(s32 direction, u32 devAddr, void* dramAddr, size_t size);
s32 __osSpSetPc(void* pc);
s32 __osSpRawStartDma(s32 direction, void* devAddr, void* dramAddr, size_t size);
#endif
include/PR/os_pi.h
-2
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@@ -99,10 +99,8 @@ typedef struct OSDevMgr {
#define PI_DOMAIN1 0
#define PI_DOMAIN2 1
extern OSPiHandle* __osPiTable;
void osCreatePiManager(OSPri pri, OSMesgQueue* cmdQ, OSMesg* cmdBuf, s32 cmdMsgCnt);
OSPiHandle* osCartRomInit(void);
include/PR/os_vi.h
+7 -1
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@@ -122,6 +122,13 @@ extern OSViMode osViModeNtscLan1;
extern OSViMode osViModeMpalLan1;
extern OSViMode osViModeFpalLan1;
extern OSViMode osViModeNtscHpf1;
extern OSViMode osViModePalLan1;
extern OSViMode osViModeNtscHpn1;
extern OSViMode osViModeNtscLan1;
extern OSViMode osViModeMpalLan1;
extern OSViMode osViModeFpalLan1;
void* osViGetCurrentFramebuffer(void);
void* osViGetNextFramebuffer(void);
void osViSetXScale(f32 value);
@@ -134,5 +141,4 @@ void osViSwapBuffer(void* frameBufPtr);
void osViBlack(u8 active);
void osCreateViManager(OSPri pri);
#endif
include/PR/piint.h
-1
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@@ -102,5 +102,4 @@ s32 __osEPiRawReadIo(OSPiHandle* handle, uintptr_t devAddr, u32* data);
s32 __osEPiRawStartDma(OSPiHandle* handle, s32 direction, uintptr_t cartAddr, void* dramAddr, size_t size);
OSMesgQueue* osPiGetCmdQueue(void);
#endif
include/PR/rcp.h
+21 -21
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@@ -203,33 +203,33 @@
#define VI_V_CURRENT_LINE_REG 0x04400010
#define VI_BURST_REG 0x04400014
#define VI_TIMING_REG 0x04400014
#define VI_V_SYNC_REG 0x04400018 //VI vertical sync
#define VI_H_SYNC_REG 0x0440001C //VI horizontal sync
#define VI_LEAP_REG 0x04400020 //VI horizontal sync leap
#define VI_V_SYNC_REG 0x04400018 // VI vertical sync
#define VI_H_SYNC_REG 0x0440001C // VI horizontal sync
#define VI_LEAP_REG 0x04400020 // VI horizontal sync leap
#define VI_H_SYNC_LEAP_REG 0x04400020
#define VI_H_START_REG 0x04400024 //VI horizontal video
#define VI_H_START_REG 0x04400024 // VI horizontal video
#define VI_H_VIDEO_REG 0x04400024
#define VI_V_START_REG 0x04400028 //VI vertical video
#define VI_V_START_REG 0x04400028 // VI vertical video
#define VI_V_VIDEO_REG 0x04400028
#define VI_V_BURST_REG 0x0440002C //VI vertical burst
#define VI_X_SCALE_REG 0x04400030 //VI x-scale
#define VI_Y_SCALE_REG 0x04400034 //VI y-scale
#define VI_V_BURST_REG 0x0440002C // VI vertical burst
#define VI_X_SCALE_REG 0x04400030 // VI x-scale
#define VI_Y_SCALE_REG 0x04400034 // VI y-scale
#define PI_DRAM_ADDR_REG 0x04600000 //PI DRAM address
#define PI_CART_ADDR_REG 0x04600004 //PI pbus (cartridge) address
#define PI_RD_LEN_REG 0x04600008 //PI read length
#define PI_WR_LEN_REG 0x0460000C //PI write length
#define PI_STATUS_REG 0x04600010 //PI status
#define PI_BSD_DOM1_LAT_REG 0x04600014 //PI dom1 latency
#define PI_DRAM_ADDR_REG 0x04600000 // PI DRAM address
#define PI_CART_ADDR_REG 0x04600004 // PI pbus (cartridge) address
#define PI_RD_LEN_REG 0x04600008 // PI read length
#define PI_WR_LEN_REG 0x0460000C // PI write length
#define PI_STATUS_REG 0x04600010 // PI status
#define PI_BSD_DOM1_LAT_REG 0x04600014 // PI dom1 latency
#define PI_DOMAIN1_REG 0x04600014
#define PI_BSD_DOM1_PWD_REG 0x04600018 //PI dom1 pulse width
#define PI_BSD_DOM1_PGS_REG 0x0460001C //PI dom1 page size
#define PI_BSD_DOM1_RLS_REG 0x04600020 //PI dom1 release
#define PI_BSD_DOM2_LAT_REG 0x04600024 //PI dom2 latency
#define PI_BSD_DOM1_PWD_REG 0x04600018 // PI dom1 pulse width
#define PI_BSD_DOM1_PGS_REG 0x0460001C // PI dom1 page size
#define PI_BSD_DOM1_RLS_REG 0x04600020 // PI dom1 release
#define PI_BSD_DOM2_LAT_REG 0x04600024 // PI dom2 latency
#define PI_DOMAIN2_REG 0x04600024
#define PI_BSD_DOM2_PWD_REG 0x04600028 //PI dom2 pulse width
#define PI_BSD_DOM2_PGS_REG 0x0460002C //PI dom2 page size
#define PI_BSD_DOM2_RLS_REG 0x04600030 //PI dom2 release
#define PI_BSD_DOM2_PWD_REG 0x04600028 // PI dom2 pulse width
#define PI_BSD_DOM2_PGS_REG 0x0460002C // PI dom2 page size
#define PI_BSD_DOM2_RLS_REG 0x04600030 // PI dom2 release
#define PI_STATUS_DMA_BUSY (1 << 0)
#define PI_STATUS_IO_BUSY (1 << 1)