From f8719bad7710ffdd7e9877a95e5666a9d0cdb059 Mon Sep 17 00:00:00 2001 From: angie Date: Sun, 3 Sep 2023 19:25:24 -0300 Subject: [PATCH] yeet hardware.h --- include/PR/hardware.h | 74 ----------------------------- include/PR/rcp.h | 89 +++++++++++++++++++++++++++++++++-- include/gfx.h | 2 + include/ultra64.h | 1 - spec | 2 +- src/libultra/io/cartrominit.c | 2 +- src/libultra/io/devmgr.c | 2 +- src/libultra/io/epirawdma.c | 2 +- src/libultra/io/epirawread.c | 2 +- src/libultra/io/epirawwrite.c | 2 +- src/libultra/io/pirawdma.c | 2 +- 11 files changed, 93 insertions(+), 87 deletions(-) delete mode 100644 include/PR/hardware.h diff --git a/include/PR/hardware.h b/include/PR/hardware.h deleted file mode 100644 index d911f8be40..0000000000 --- a/include/PR/hardware.h +++ /dev/null @@ -1,74 +0,0 @@ -#ifndef _ULTRA64_HARDWARE_H_ -#define _ULTRA64_HARDWARE_H_ - -// TODO: not real libultra header. Refactor to R4300.h - -#define VI_STATUS_REG 0x04400000 -#define VI_CONTROL_REG 0x04400000 -#define VI_ORIGIN_REG 0x04400004 -#define VI_DRAM_ADDR_REG 0x04400004 -#define VI_WIDTH_REG 0x04400008 -#define VI_H_WIDTH_REG 0x04400008 -#define VI_INTR_REG 0x0440000C -#define VI_V_INTER_REG 0x0440000C -#define VI_CURRENT_REG 0x04400010 -#define VI_V_CURRENT_LINE_REG 0x04400010 -#define VI_BURST_REG 0x04400014 -#define VI_TIMING_REG 0x04400014 -#define VI_V_SYNC_REG 0x04400018 //VI vertical sync -#define VI_H_SYNC_REG 0x0440001C //VI horizontal sync -#define VI_LEAP_REG 0x04400020 //VI horizontal sync leap -#define VI_H_SYNC_LEAP_REG 0x04400020 -#define VI_H_START_REG 0x04400024 //VI horizontal video -#define VI_H_VIDEO_REG 0x04400024 -#define VI_V_START_REG 0x04400028 //VI vertical video -#define VI_V_VIDEO_REG 0x04400028 -#define VI_V_BURST_REG 0x0440002C //VI vertical burst -#define VI_X_SCALE_REG 0x04400030 //VI x-scale -#define VI_Y_SCALE_REG 0x04400034 //VI y-scale - -#define TMEM_SIZE 0x1000 - -#define SP_MEM_ADDR_REG 0x04040000 -#define SP_DRAM_ADDR_REG 0x04040004 -#define SP_RD_LEN_REG 0x04040008 -#define SP_WR_LEN_REG 0x0404000C -#define SP_STATUS_REG 0x04040010 -#define SP_DMA_FULL_REG 0x04040014 -#define SP_DMA_BUSY_REG 0x04040018 -#define SP_PC_REG 0x04080000 - -#define PI_DRAM_ADDR_REG 0x04600000 //PI DRAM address -#define PI_CART_ADDR_REG 0x04600004 //PI pbus (cartridge) address -#define PI_RD_LEN_REG 0x04600008 //PI read length -#define PI_WR_LEN_REG 0x0460000C //PI write length -#define PI_STATUS_REG 0x04600010 //PI status -#define PI_BSD_DOM1_LAT_REG 0x04600014 //PI dom1 latency -#define PI_DOMAIN1_REG 0x04600014 -#define PI_BSD_DOM1_PWD_REG 0x04600018 //PI dom1 pulse width -#define PI_BSD_DOM1_PGS_REG 0x0460001C //PI dom1 page size -#define PI_BSD_DOM1_RLS_REG 0x04600020 //PI dom1 release -#define PI_BSD_DOM2_LAT_REG 0x04600024 //PI dom2 latency -#define PI_DOMAIN2_REG 0x04600024 -#define PI_BSD_DOM2_PWD_REG 0x04600028 //PI dom2 pulse width -#define PI_BSD_DOM2_PGS_REG 0x0460002C //PI dom2 page size -#define PI_BSD_DOM2_RLS_REG 0x04600030 //PI dom2 release - -#define PI_STATUS_BUSY (1 << 0) -#define PI_STATUS_IOBUSY (1 << 1) -#define PI_STATUS_ERROR (1 << 2) - -#define PI_STATUS_RESET_CONTROLLER (1 << 0) -#define PI_STATUS_CLEAR_INTR (1 << 1) - -#define SI_DRAM_ADDR_REG 0x04800000 -#define SI_PIF_ADDR_RD64B_REG 0x04800004 -#define SI_PIF_ADDR_WR64B_REG 0x04800010 -#define SI_STATUS_REG 0x04800018 - -#define SI_STATUS_DMA_BUSY (1 << 0) -#define SI_STATUS_IO_READ_BUSY (1 << 1) -#define SI_STATUS_DMA_ERROR (1 << 3) -#define SI_STATUS_INTERRUPT (1 << 12) - -#endif diff --git a/include/PR/rcp.h b/include/PR/rcp.h index 919e6e90a1..09549fc1c9 100644 --- a/include/PR/rcp.h +++ b/include/PR/rcp.h @@ -94,6 +94,13 @@ #define AI_MAX_BIT_RATE 16 /* 4-bit+1 */ #define AI_MIN_BIT_RATE 2 +#define CHNL_ERR_NORESP 0x80 /* Bit 7 (Rx): No response error */ +#define CHNL_ERR_OVERRUN 0x40 /* Bit 6 (Rx): Overrun error */ +#define CHNL_ERR_FRAME 0x80 /* Bit 7 (Tx): Frame error */ +#define CHNL_ERR_COLLISION 0x40 /* Bit 6 (Tx): Collision error */ + +#define CHNL_ERR_MASK 0xC0 /* Bit 6-7: channel errors */ + #define DEVICE_TYPE_CART 0 /* ROM cartridge */ #define DEVICE_TYPE_BULK 1 /* ROM bulk */ #define DEVICE_TYPE_64DD 2 /* 64 Disk Drive */ @@ -108,6 +115,15 @@ #define SP_IMEM_START 0x04001000 #define SP_IMEM_END 0x04001FFF +#define SP_MEM_ADDR_REG 0x04040000 +#define SP_DRAM_ADDR_REG 0x04040004 +#define SP_RD_LEN_REG 0x04040008 +#define SP_WR_LEN_REG 0x0404000C +#define SP_STATUS_REG 0x04040010 +#define SP_DMA_FULL_REG 0x04040014 +#define SP_DMA_BUSY_REG 0x04040018 +#define SP_PC_REG 0x04080000 + /** * SP_STATUS_REG: write bits */ @@ -175,12 +191,60 @@ #define SP_SET_CPUSIGNAL SP_SET_SIG4 #define SP_STATUS_CPUSIGNAL SP_STATUS_SIG4 -#define CHNL_ERR_NORESP 0x80 /* Bit 7 (Rx): No response error */ -#define CHNL_ERR_OVERRUN 0x40 /* Bit 6 (Rx): Overrun error */ -#define CHNL_ERR_FRAME 0x80 /* Bit 7 (Tx): Frame error */ -#define CHNL_ERR_COLLISION 0x40 /* Bit 6 (Tx): Collision error */ +#define VI_STATUS_REG 0x04400000 +#define VI_CONTROL_REG 0x04400000 +#define VI_ORIGIN_REG 0x04400004 +#define VI_DRAM_ADDR_REG 0x04400004 +#define VI_WIDTH_REG 0x04400008 +#define VI_H_WIDTH_REG 0x04400008 +#define VI_INTR_REG 0x0440000C +#define VI_V_INTER_REG 0x0440000C +#define VI_CURRENT_REG 0x04400010 +#define VI_V_CURRENT_LINE_REG 0x04400010 +#define VI_BURST_REG 0x04400014 +#define VI_TIMING_REG 0x04400014 +#define VI_V_SYNC_REG 0x04400018 //VI vertical sync +#define VI_H_SYNC_REG 0x0440001C //VI horizontal sync +#define VI_LEAP_REG 0x04400020 //VI horizontal sync leap +#define VI_H_SYNC_LEAP_REG 0x04400020 +#define VI_H_START_REG 0x04400024 //VI horizontal video +#define VI_H_VIDEO_REG 0x04400024 +#define VI_V_START_REG 0x04400028 //VI vertical video +#define VI_V_VIDEO_REG 0x04400028 +#define VI_V_BURST_REG 0x0440002C //VI vertical burst +#define VI_X_SCALE_REG 0x04400030 //VI x-scale +#define VI_Y_SCALE_REG 0x04400034 //VI y-scale -#define CHNL_ERR_MASK 0xC0 /* Bit 6-7: channel errors */ +#define PI_DRAM_ADDR_REG 0x04600000 //PI DRAM address +#define PI_CART_ADDR_REG 0x04600004 //PI pbus (cartridge) address +#define PI_RD_LEN_REG 0x04600008 //PI read length +#define PI_WR_LEN_REG 0x0460000C //PI write length +#define PI_STATUS_REG 0x04600010 //PI status +#define PI_BSD_DOM1_LAT_REG 0x04600014 //PI dom1 latency +#define PI_DOMAIN1_REG 0x04600014 +#define PI_BSD_DOM1_PWD_REG 0x04600018 //PI dom1 pulse width +#define PI_BSD_DOM1_PGS_REG 0x0460001C //PI dom1 page size +#define PI_BSD_DOM1_RLS_REG 0x04600020 //PI dom1 release +#define PI_BSD_DOM2_LAT_REG 0x04600024 //PI dom2 latency +#define PI_DOMAIN2_REG 0x04600024 +#define PI_BSD_DOM2_PWD_REG 0x04600028 //PI dom2 pulse width +#define PI_BSD_DOM2_PGS_REG 0x0460002C //PI dom2 page size +#define PI_BSD_DOM2_RLS_REG 0x04600030 //PI dom2 release + +#define PI_STATUS_DMA_BUSY (1 << 0) +#define PI_STATUS_IO_BUSY (1 << 1) +#define PI_STATUS_ERROR (1 << 2) + +/* + * PI_STATUS_REG: write bits + */ +#define PI_STATUS_RESET (1 << 0) +#define PI_SET_RESET PI_STATUS_RESET + +#define PI_STATUS_CLR_INTR (1 << 1) +#define PI_CLR_INTR PI_STATUS_CLR_INTR + +#define PI_DMA_BUFFER_SIZE 128 #define PI_DOM1_ADDR1 0x06000000 /* to 0x07FFFFFF */ #define PI_DOM1_ADDR2 0x10000000 /* to 0x1FBFFFFF */ @@ -188,6 +252,21 @@ #define PI_DOM2_ADDR1 0x05000000 /* to 0x05FFFFFF */ #define PI_DOM2_ADDR2 0x08000000 /* to 0x0FFFFFFF */ +/** + * Serial Interface (SI) Registers + */ +#define SI_BASE_REG 0x04800000 + +#define SI_DRAM_ADDR_REG (SI_BASE_REG + 0x00) +#define SI_PIF_ADDR_RD64B_REG (SI_BASE_REG + 0x04) +#define SI_PIF_ADDR_WR64B_REG (SI_BASE_REG + 0x10) +#define SI_STATUS_REG (SI_BASE_REG + 0x18) + +#define SI_STATUS_DMA_BUSY (1 << 0) +#define SI_STATUS_IO_READ_BUSY (1 << 1) +#define SI_STATUS_DMA_ERROR (1 << 3) +#define SI_STATUS_INTERRUPT (1 << 12) + #define IO_READ(addr) (*(vu32*)PHYS_TO_K1(addr)) #define IO_WRITE(addr,data) (*(vu32*)PHYS_TO_K1(addr)=(u32)(data)) diff --git a/include/gfx.h b/include/gfx.h index 7902793684..883ddfe301 100644 --- a/include/gfx.h +++ b/include/gfx.h @@ -9,6 +9,8 @@ struct GameState; +#define TMEM_SIZE 0x1000 + typedef enum SetupDL { /* 0x00 */ SETUPDL_0, /* 0x01 */ SETUPDL_1, diff --git a/include/ultra64.h b/include/ultra64.h index e6be91641d..2a834aaa69 100644 --- a/include/ultra64.h +++ b/include/ultra64.h @@ -7,7 +7,6 @@ #include "PR/gu.h" #include "PR/guint.h" #include "PR/controller_voice.h" -#include "PR/hardware.h" #include "PR/os.h" #include "PR/osint.h" #include "PR/piint.h" diff --git a/spec b/spec index 819735946b..05a20da0f1 100644 --- a/spec +++ b/spec @@ -42,7 +42,7 @@ beginseg include "build/src/boot_O2/system_malloc.o" include "build/src/boot_O2/rand.o" include "build/src/boot_O2/__osMalloc.o" - include "build/src/libultra/rmon/sprintf.o" + include "build/src/libultra/libc/sprintf.o" include "build/src/boot_O2/printutils.o" include "build/src/boot_O2/sleep.o" include "build/asm/boot/setcause.text.o" diff --git a/src/libultra/io/cartrominit.c b/src/libultra/io/cartrominit.c index ea90d87280..eeca4b339e 100644 --- a/src/libultra/io/cartrominit.c +++ b/src/libultra/io/cartrominit.c @@ -30,7 +30,7 @@ OSPiHandle* osCartRomInit(void) { bzero(&__CartRomHandle.transferInfo, sizeof(__OSTranxInfo)); /* Uses `status & PI_STATUS_ERROR` in OoT */ - while (status = IO_READ(PI_STATUS_REG), status & (PI_STATUS_BUSY | PI_STATUS_IOBUSY)) { + while (status = IO_READ(PI_STATUS_REG), status & (PI_STATUS_DMA_BUSY | PI_STATUS_IO_BUSY)) { ; } diff --git a/src/libultra/io/devmgr.c b/src/libultra/io/devmgr.c index 9e7220de35..93947e57b5 100644 --- a/src/libultra/io/devmgr.c +++ b/src/libultra/io/devmgr.c @@ -52,7 +52,7 @@ void __osDevMgrMain(void* arg) { __osEPiRawWriteIo(ioMesg->piHandle, LEO_BM_CTL, transfer->bmCtlShadow | LEO_BM_CTL_CLR_MECHANIC_INTR); } block->errStatus = 4; - IO_WRITE(PI_STATUS_REG, PI_STATUS_CLEAR_INTR); + IO_WRITE(PI_STATUS_REG, PI_CLR_INTR); __osSetGlobalIntMask(OS_IM_PI | SR_IBIT4); } osSendMesg(ioMesg->hdr.retQueue, (OSMesg)ioMesg, OS_MESG_NOBLOCK); diff --git a/src/libultra/io/epirawdma.c b/src/libultra/io/epirawdma.c index 2cd543c0e2..737bdce6ea 100644 --- a/src/libultra/io/epirawdma.c +++ b/src/libultra/io/epirawdma.c @@ -4,7 +4,7 @@ s32 __osEPiRawStartDma(OSPiHandle* handle, s32 direction, uintptr_t cartAddr, vo s32 status; OSPiHandle* curHandle; - while (status = IO_READ(PI_STATUS_REG), status & (PI_STATUS_BUSY | PI_STATUS_IOBUSY)) { + while (status = IO_READ(PI_STATUS_REG), status & (PI_STATUS_DMA_BUSY | PI_STATUS_IO_BUSY)) { ; } diff --git a/src/libultra/io/epirawread.c b/src/libultra/io/epirawread.c index 26d85aa8a4..a9379c492c 100644 --- a/src/libultra/io/epirawread.c +++ b/src/libultra/io/epirawread.c @@ -4,7 +4,7 @@ s32 __osEPiRawReadIo(OSPiHandle* handle, uintptr_t devAddr, u32* data) { s32 status; OSPiHandle* curHandle; - while (status = IO_READ(PI_STATUS_REG), status & (PI_STATUS_BUSY | PI_STATUS_IOBUSY)) { + while (status = IO_READ(PI_STATUS_REG), status & (PI_STATUS_DMA_BUSY | PI_STATUS_IO_BUSY)) { ; } diff --git a/src/libultra/io/epirawwrite.c b/src/libultra/io/epirawwrite.c index 65d110a66c..946400ca71 100644 --- a/src/libultra/io/epirawwrite.c +++ b/src/libultra/io/epirawwrite.c @@ -4,7 +4,7 @@ s32 __osEPiRawWriteIo(OSPiHandle* handle, uintptr_t devAddr, u32 data) { s32 status; OSPiHandle* curHandle; - while (status = IO_READ(PI_STATUS_REG), status & (PI_STATUS_BUSY | PI_STATUS_IOBUSY)) {} + while (status = IO_READ(PI_STATUS_REG), status & (PI_STATUS_DMA_BUSY | PI_STATUS_IO_BUSY)) {} if (__osCurrentHandle[handle->domain]->type != handle->type) { curHandle = __osCurrentHandle[handle->domain]; diff --git a/src/libultra/io/pirawdma.c b/src/libultra/io/pirawdma.c index ad2a334dc3..905ab1348c 100644 --- a/src/libultra/io/pirawdma.c +++ b/src/libultra/io/pirawdma.c @@ -3,7 +3,7 @@ s32 __osPiRawStartDma(s32 direction, uintptr_t devAddr, void* dramAddr, size_t size) { register int status = IO_READ(PI_STATUS_REG); - while (status & (PI_STATUS_IOBUSY | PI_STATUS_BUSY)) { + while (status & (PI_STATUS_IO_BUSY | PI_STATUS_DMA_BUSY)) { status = IO_READ(PI_STATUS_REG); }