mirror of
https://github.com/zeldaret/oot
synced 2026-08-16 21:17:48 -04:00
Use IDO for assembling handwritten asm files in src (#2390)
* as0 * Fix ASOPTFLAGS for src/libc, remove unnecessary noreorder region in kanread * Suggested changes * Use %half to load the boot bss size for matching Co-authored-by: cadmic <cadmic24@gmail.com> * Wrap all of __osProbeTLB in noreorder --------- Co-authored-by: cadmic <cadmic24@gmail.com>
This commit is contained in:
Tharo
+229
-229
@@ -10,7 +10,7 @@
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#define C_REG(x) $x
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#endif
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// Segment base addresses and sizes
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/* Segment base addresses and sizes */
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#define KUBASE 0
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#define KUSIZE 0x80000000
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#define K0BASE 0x80000000
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@@ -20,24 +20,24 @@
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#define K2BASE 0xC0000000
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#define K2SIZE 0x20000000
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// Exception vectors
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#define SIZE_EXCVEC 0x80 // Size of an exc. vec
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#define UT_VEC K0BASE // utlbmiss vector
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#define R_VEC (K1BASE + 0x1FC00000) // reset vector
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#define XUT_VEC (K0BASE + 0x80) // extended address tlbmiss
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#define ECC_VEC (K0BASE + 0x100) // Ecc exception vector
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#define E_VEC (K0BASE + 0x180) // Gen. exception vector
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/* Exception vectors */
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#define SIZE_EXCVEC 0x80 /* Size of an exc. vec */
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#define UT_VEC K0BASE /* utlbmiss vector */
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#define R_VEC (K1BASE + 0x1FC00000) /* reset vector */
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#define XUT_VEC (K0BASE + 0x80) /* extended address tlbmiss */
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#define ECC_VEC (K0BASE + 0x100) /* Ecc exception vector */
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#define E_VEC (K0BASE + 0x180) /* Gen. exception vector */
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// Address conversion macros
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#define K0_TO_K1(x) (U32(x) | 0xA0000000) // kseg0 to kseg1
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#define K1_TO_K0(x) (U32(x) & 0x9FFFFFFF) // kseg1 to kseg0
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#define K0_TO_PHYS(x) (U32(x) & 0x1FFFFFFF) // kseg0 to physical
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#define K1_TO_PHYS(x) (U32(x) & 0x1FFFFFFF) // kseg1 to physical
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#define KDM_TO_PHYS(x) (U32(x) & 0x1FFFFFFF) // direct mapped to physical
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#define PHYS_TO_K0(x) (U32(x) | 0x80000000) // physical to kseg0
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#define PHYS_TO_K1(x) (U32(x) | 0xA0000000) // physical to kseg1
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/* Address conversion macros */
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#define K0_TO_K1(x) (U32(x) | 0xA0000000) /* kseg0 to kseg1 */
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#define K1_TO_K0(x) (U32(x) & 0x9FFFFFFF) /* kseg1 to kseg0 */
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#define K0_TO_PHYS(x) (U32(x) & 0x1FFFFFFF) /* kseg0 to physical */
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#define K1_TO_PHYS(x) (U32(x) & 0x1FFFFFFF) /* kseg1 to physical */
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#define KDM_TO_PHYS(x) (U32(x) & 0x1FFFFFFF) /* direct mapped to physical */
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#define PHYS_TO_K0(x) (U32(x) | 0x80000000) /* physical to kseg0 */
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#define PHYS_TO_K1(x) (U32(x) | 0xA0000000) /* physical to kseg1 */
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// Address predicates
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/* Address predicates */
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#define IS_KSEG0(x) (U32(x) >= K0BASE && U32(x) < K1BASE)
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#define IS_KSEG1(x) (U32(x) >= K1BASE && U32(x) < K2BASE)
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#define IS_KSEGDM(x) (U32(x) >= K0BASE && U32(x) < K2BASE)
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@@ -45,25 +45,25 @@
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#define IS_KPTESEG(x) (U32(x) >= KPTE_SHDUBASE)
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#define IS_KUSEG(x) (U32(x) < K0BASE)
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// TLB size constants
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/* TLB size constants */
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#define NTLBENTRIES 31 /* entry 31 is reserved by rdb */
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#define TLBHI_VPN2MASK 0xFFFFE000
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#define TLBHI_VPN2SHIFT 13
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#define TLBHI_PIDMASK 0xFF
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#define TLBHI_PIDSHIFT 0
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#define TLBHI_NPID 255 // 255 to fit in 8 bits
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#define TLBHI_NPID 255 /* 255 to fit in 8 bits */
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#define TLBLO_PFNMASK 0x3FFFFFC0
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#define TLBLO_PFNSHIFT 6
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#define TLBLO_CACHMASK 0x38 // cache coherency algorithm
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#define TLBLO_CACHMASK 0x38 /* cache coherency algorithm */
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#define TLBLO_CACHSHIFT 3
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#define TLBLO_UNCACHED 0x10 // not cached
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#define TLBLO_NONCOHRNT 0x18 // Cacheable non-coherent
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#define TLBLO_EXLWR 0x28 // Exclusive write
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#define TLBLO_D 0x4 // writeable
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#define TLBLO_V 0x2 // valid bit
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#define TLBLO_G 0x1 // global access bit
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#define TLBLO_UNCACHED 0x10 /* not cached */
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#define TLBLO_NONCOHRNT 0x18 /* Cacheable non-coherent */
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#define TLBLO_EXLWR 0x28 /* Exclusive write */
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#define TLBLO_D 0x4 /* writeable */
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#define TLBLO_V 0x2 /* valid bit */
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#define TLBLO_G 0x1 /* global access bit */
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#define TLBINX_PROBE 0x80000000
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#define TLBINX_INXMASK 0x3F
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@@ -88,104 +88,104 @@
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/*
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* Status register
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*/
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#define SR_CUMASK 0xF0000000 // coproc usable bits
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#define SR_CUMASK 0xF0000000 /* coproc usable bits */
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#define SR_CU3 0x80000000 // Coprocessor 3 usable
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#define SR_CU2 0x40000000 // Coprocessor 2 usable
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#define SR_CU1 0x20000000 // Coprocessor 1 usable
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#define SR_CU0 0x10000000 // Coprocessor 0 usable
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#define SR_RP 0x08000000 // Reduced power (quarter speed)
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#define SR_FR 0x04000000 // MIPS III FP register mode
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#define SR_RE 0x02000000 // Reverse endian
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#define SR_ITS 0x01000000 // Instruction trace support
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#define SR_BEV 0x00400000 // Use boot exception vectors
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#define SR_TS 0x00200000 // TLB shutdown
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#define SR_SR 0x00100000 // Soft reset occured
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#define SR_CH 0x00040000 // Cache hit for last 'cache' op
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#define SR_CE 0x00020000 // Create ECC
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#define SR_DE 0x00010000 // ECC of parity does not cause error
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#define SR_CU3 0x80000000 /* Coprocessor 3 usable */
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#define SR_CU2 0x40000000 /* Coprocessor 2 usable */
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#define SR_CU1 0x20000000 /* Coprocessor 1 usable */
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#define SR_CU0 0x10000000 /* Coprocessor 0 usable */
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#define SR_RP 0x08000000 /* Reduced power (quarter speed) */
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#define SR_FR 0x04000000 /* MIPS III FP register mode */
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#define SR_RE 0x02000000 /* Reverse endian */
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#define SR_ITS 0x01000000 /* Instruction trace support */
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#define SR_BEV 0x00400000 /* Use boot exception vectors */
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#define SR_TS 0x00200000 /* TLB shutdown */
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#define SR_SR 0x00100000 /* Soft reset occured */
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#define SR_CH 0x00040000 /* Cache hit for last 'cache' op */
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#define SR_CE 0x00020000 /* Create ECC */
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#define SR_DE 0x00010000 /* ECC of parity does not cause error */
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// Interrupt enable bits
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// (NOTE: bits set to 1 enable the corresponding level interrupt)
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#define SR_IMASK 0x0000FF00 // Interrupt mask
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#define SR_IMASK8 0x00000000 // mask level 8
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#define SR_IMASK7 0x00008000 // mask level 7
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#define SR_IMASK6 0x0000C000 // mask level 6
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#define SR_IMASK5 0x0000E000 // mask level 5
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#define SR_IMASK4 0x0000F000 // mask level 4
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#define SR_IMASK3 0x0000F800 // mask level 3
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#define SR_IMASK2 0x0000FC00 // mask level 2
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#define SR_IMASK1 0x0000FE00 // mask level 1
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#define SR_IMASK0 0x0000FF00 // mask level 0
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/* Interrupt enable bits */
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/* (NOTE: bits set to 1 enable the corresponding level interrupt) */
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#define SR_IMASK 0x0000FF00 /* Interrupt mask */
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#define SR_IMASK8 0x00000000 /* mask level 8 */
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#define SR_IMASK7 0x00008000 /* mask level 7 */
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#define SR_IMASK6 0x0000C000 /* mask level 6 */
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#define SR_IMASK5 0x0000E000 /* mask level 5 */
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#define SR_IMASK4 0x0000F000 /* mask level 4 */
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#define SR_IMASK3 0x0000F800 /* mask level 3 */
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#define SR_IMASK2 0x0000FC00 /* mask level 2 */
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#define SR_IMASK1 0x0000FE00 /* mask level 1 */
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#define SR_IMASK0 0x0000FF00 /* mask level 0 */
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#define SR_IBIT8 0x00008000 // bit level 8
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#define SR_IBIT7 0x00004000 // bit level 7
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#define SR_IBIT6 0x00002000 // bit level 6
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#define SR_IBIT5 0x00001000 // bit level 5
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#define SR_IBIT4 0x00000800 // bit level 4
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#define SR_IBIT3 0x00000400 // bit level 3
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#define SR_IBIT2 0x00000200 // bit level 2
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#define SR_IBIT1 0x00000100 // bit level 1
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#define SR_IBIT8 0x00008000 /* bit level 8 */
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#define SR_IBIT7 0x00004000 /* bit level 7 */
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#define SR_IBIT6 0x00002000 /* bit level 6 */
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#define SR_IBIT5 0x00001000 /* bit level 5 */
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#define SR_IBIT4 0x00000800 /* bit level 4 */
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#define SR_IBIT3 0x00000400 /* bit level 3 */
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#define SR_IBIT2 0x00000200 /* bit level 2 */
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#define SR_IBIT1 0x00000100 /* bit level 1 */
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#define SR_IMASKSHIFT 8
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#define SR_KX 0x00000080 // extended-addr TLB vec in kernel
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#define SR_SX 0x00000040 // xtended-addr TLB vec supervisor
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#define SR_UX 0x00000020 // xtended-addr TLB vec in user mode
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#define SR_KSU_MASK 0x00000018 // mode mask
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#define SR_KSU_USR 0x00000010 // user mode
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#define SR_KSU_SUP 0x00000008 // supervisor mode
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#define SR_KSU_KER 0x00000000 // kernel mode
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#define SR_ERL 0x00000004 // Error level, 1=>cache error
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#define SR_EXL 0x00000002 // Exception level, 1=>exception
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#define SR_IE 0x00000001 // interrupt enable, 1=>enable
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#define SR_KX 0x00000080 /* extended-addr TLB vec in kernel */
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#define SR_SX 0x00000040 /* xtended-addr TLB vec supervisor */
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#define SR_UX 0x00000020 /* xtended-addr TLB vec in user mode */
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#define SR_KSU_MASK 0x00000018 /* mode mask */
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#define SR_KSU_USR 0x00000010 /* user mode */
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#define SR_KSU_SUP 0x00000008 /* supervisor mode */
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#define SR_KSU_KER 0x00000000 /* kernel mode */
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#define SR_ERL 0x00000004 /* Error level, 1=>cache error */
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#define SR_EXL 0x00000002 /* Exception level, 1=>exception */
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#define SR_IE 0x00000001 /* interrupt enable, 1=>enable */
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// Cause Register
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#define CAUSE_BD 0x80000000 // Branch delay slot
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#define CAUSE_CEMASK 0x30000000 // coprocessor error
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/* Cause Register */
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#define CAUSE_BD 0x80000000 /* Branch delay slot */
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#define CAUSE_CEMASK 0x30000000 /* coprocessor error */
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#define CAUSE_CESHIFT 28
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// Interrupt pending bits
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#define CAUSE_IP8 0x00008000 // External level 8 pending - COMPARE
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#define CAUSE_IP7 0x00004000 // External level 7 pending - INT4
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#define CAUSE_IP6 0x00002000 // External level 6 pending - INT3
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#define CAUSE_IP5 0x00001000 // External level 5 pending - INT2
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#define CAUSE_IP4 0x00000800 // External level 4 pending - INT1
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#define CAUSE_IP3 0x00000400 // External level 3 pending - INT0
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#define CAUSE_SW2 0x00000200 // Software level 2 pending
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#define CAUSE_SW1 0x00000100 // Software level 1 pending
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/* Interrupt pending bits */
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#define CAUSE_IP8 0x00008000 /* External level 8 pending - COMPARE */
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#define CAUSE_IP7 0x00004000 /* External level 7 pending - INT4 */
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#define CAUSE_IP6 0x00002000 /* External level 6 pending - INT3 */
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#define CAUSE_IP5 0x00001000 /* External level 5 pending - INT2 */
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#define CAUSE_IP4 0x00000800 /* External level 4 pending - INT1 */
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#define CAUSE_IP3 0x00000400 /* External level 3 pending - INT0 */
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#define CAUSE_SW2 0x00000200 /* Software level 2 pending */
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#define CAUSE_SW1 0x00000100 /* Software level 1 pending */
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#define CAUSE_IPMASK 0x0000FF00 // Pending interrupt mask
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#define CAUSE_IPMASK 0x0000FF00 /* Pending interrupt mask */
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#define CAUSE_IPSHIFT 8
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#define CAUSE_EXCMASK 0x0000007C // Cause code bits
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#define CAUSE_EXCMASK 0x0000007C /* Cause code bits */
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#define CAUSE_EXCSHIFT 2
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// Cause register exception codes
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/* Cause register exception codes */
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#define EXC_CODE(x) ((x) << 2)
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// Hardware exception codes
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#define EXC_INT EXC_CODE(0) // interrupt
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#define EXC_MOD EXC_CODE(1) // TLB mod
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#define EXC_RMISS EXC_CODE(2) // Read TLB Miss
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#define EXC_WMISS EXC_CODE(3) // Write TLB Miss
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#define EXC_RADE EXC_CODE(4) // Read Address Error
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#define EXC_WADE EXC_CODE(5) // Write Address Error
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#define EXC_IBE EXC_CODE(6) // Instruction Bus Error
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#define EXC_DBE EXC_CODE(7) // Data Bus Error
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#define EXC_SYSCALL EXC_CODE(8) // SYSCALL
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#define EXC_BREAK EXC_CODE(9) // BREAKpoint
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#define EXC_II EXC_CODE(10) // Illegal Instruction
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#define EXC_CPU EXC_CODE(11) // CoProcessor Unusable
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#define EXC_OV EXC_CODE(12) // OVerflow
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#define EXC_TRAP EXC_CODE(13) // Trap exception
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#define EXC_VCEI EXC_CODE(14) // Virt. Coherency on Inst. fetch
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#define EXC_FPE EXC_CODE(15) // Floating Point Exception
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#define EXC_WATCH EXC_CODE(23) // Watchpoint reference
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#define EXC_VCED EXC_CODE(31) // Virt. Coherency on data read
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/* Hardware exception codes */
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#define EXC_INT EXC_CODE(0) /* interrupt */
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#define EXC_MOD EXC_CODE(1) /* TLB mod */
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#define EXC_RMISS EXC_CODE(2) /* Read TLB Miss */
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#define EXC_WMISS EXC_CODE(3) /* Write TLB Miss */
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#define EXC_RADE EXC_CODE(4) /* Read Address Error */
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#define EXC_WADE EXC_CODE(5) /* Write Address Error */
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#define EXC_IBE EXC_CODE(6) /* Instruction Bus Error */
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#define EXC_DBE EXC_CODE(7) /* Data Bus Error */
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#define EXC_SYSCALL EXC_CODE(8) /* SYSCALL */
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#define EXC_BREAK EXC_CODE(9) /* BREAKpoint */
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#define EXC_II EXC_CODE(10) /* Illegal Instruction */
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#define EXC_CPU EXC_CODE(11) /* CoProcessor Unusable */
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#define EXC_OV EXC_CODE(12) /* OVerflow */
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#define EXC_TRAP EXC_CODE(13) /* Trap exception */
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#define EXC_VCEI EXC_CODE(14) /* Virt. Coherency on Inst. fetch */
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#define EXC_FPE EXC_CODE(15) /* Floating Point Exception */
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#define EXC_WATCH EXC_CODE(23) /* Watchpoint reference */
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#define EXC_VCED EXC_CODE(31) /* Virt. Coherency on data read */
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// C0_PRID Defines
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/* C0_PRID Defines */
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#define C0_IMPMASK 0xFF00
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#define C0_IMPSHIFT 8
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#define C0_REVMASK 0xFF
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@@ -193,106 +193,106 @@
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#define C0_MAJREVSHIFT 4
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#define C0_MINREVMASK 0xF
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// Coprocessor 0 operations
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#define C0_READI 0x1 // read ITLB entry addressed by C0_INDEX
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#define C0_WRITEI 0x2 // write ITLB entry addressed by C0_INDEX
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#define C0_WRITER 0x6 // write ITLB entry addressed by C0_RAND
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#define C0_PROBE 0x8 // probe for ITLB entry addressed by TLBHI
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#define C0_RFE 0x10 // restore for exception
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/* Coprocessor 0 operations */
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#define C0_READI 0x1 /* read ITLB entry addressed by C0_INDEX */
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#define C0_WRITEI 0x2 /* write ITLB entry addressed by C0_INDEX */
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#define C0_WRITER 0x6 /* write ITLB entry addressed by C0_RAND */
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#define C0_PROBE 0x8 /* probe for ITLB entry addressed by TLBHI */
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#define C0_RFE 0x10 /* restore for exception */
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// 'cache' instruction definitions
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/* 'cache' instruction definitions */
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// Target cache
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#define CACH_PI 0x0 // specifies primary inst. cache
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#define CACH_PD 0x1 // primary data cache
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#define CACH_SI 0x2 // secondary instruction cache
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#define CACH_SD 0x3 // secondary data cache
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/* Target cache */
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#define CACH_PI 0x0 /* specifies primary inst. cache */
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#define CACH_PD 0x1 /* primary data cache */
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#define CACH_SI 0x2 /* secondary instruction cache */
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#define CACH_SD 0x3 /* secondary data cache */
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// Cache operations
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#define C_IINV 0x0 // index invalidate (inst, 2nd inst)
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#define C_IWBINV 0x0 // index writeback inval (d, sd)
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#define C_ILT 0x4 // index load tag (all)
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#define C_IST 0x8 // index store tag (all)
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#define C_CDX 0xC // create dirty exclusive (d, sd)
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#define C_HINV 0x10 // hit invalidate (all)
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#define C_HWBINV 0x14 // hit writeback inv. (d, sd)
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#define C_FILL 0x14 // fill (i)
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#define C_HWB 0x18 // hit writeback (i, d, sd)
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#define C_HSV 0x1C // hit set virt. (si, sd)
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/* Cache operations */
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#define C_IINV 0x0 /* index invalidate (inst, 2nd inst) */
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#define C_IWBINV 0x0 /* index writeback inval (d, sd) */
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#define C_ILT 0x4 /* index load tag (all) */
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#define C_IST 0x8 /* index store tag (all) */
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#define C_CDX 0xC /* create dirty exclusive (d, sd) */
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#define C_HINV 0x10 /* hit invalidate (all) */
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#define C_HWBINV 0x14 /* hit writeback inv. (d, sd) */
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#define C_FILL 0x14 /* fill (i) */
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#define C_HWB 0x18 /* hit writeback (i, d, sd) */
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#define C_HSV 0x1C /* hit set virt. (si, sd) */
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// Cache size definitions
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#define ICACHE_SIZE 0x4000 // 16K
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#define ICACHE_LINESIZE 32 // 8 words
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/* Cache size definitions */
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#define ICACHE_SIZE 0x4000 /* 16K */
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#define ICACHE_LINESIZE 32 /* 8 words */
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#define ICACHE_LINEMASK (ICACHE_LINESIZE - 1)
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#define DCACHE_SIZE 0x2000 // 8K
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#define DCACHE_LINESIZE 16 // 4 words
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#define DCACHE_SIZE 0x2000 /* 8K */
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#define DCACHE_LINESIZE 16 /* 4 words */
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#define DCACHE_LINEMASK (DCACHE_LINESIZE - 1)
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// C0_CONFIG register definitions
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#define CONFIG_CM 0x80000000 // 1 == Master-Checker enabled
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#define CONFIG_EC 0x70000000 // System Clock ratio
|
||||
#define CONFIG_EC_1_1 0x6 // System Clock ratio 1 :1
|
||||
#define CONFIG_EC_3_2 0x7 // System Clock ratio 1.5 :1
|
||||
#define CONFIG_EC_2_1 0x0 // System Clock ratio 2 :1
|
||||
#define CONFIG_EC_3_1 0x1 // System Clock ratio 3 :1
|
||||
#define CONFIG_EP 0x0F000000 // Transmit Data Pattern
|
||||
#define CONFIG_SB 0x00C00000 // Secondary cache block size
|
||||
/* C0_CONFIG register definitions */
|
||||
#define CONFIG_CM 0x80000000 /* 1 == Master-Checker enabled */
|
||||
#define CONFIG_EC 0x70000000 /* System Clock ratio */
|
||||
#define CONFIG_EC_1_1 0x6 /* System Clock ratio 1 :1 */
|
||||
#define CONFIG_EC_3_2 0x7 /* System Clock ratio 1.5 :1 */
|
||||
#define CONFIG_EC_2_1 0x0 /* System Clock ratio 2 :1 */
|
||||
#define CONFIG_EC_3_1 0x1 /* System Clock ratio 3 :1 */
|
||||
#define CONFIG_EP 0x0F000000 /* Transmit Data Pattern */
|
||||
#define CONFIG_SB 0x00C00000 /* Secondary cache block size */
|
||||
|
||||
#define CONFIG_SS 0x00200000 // Split scache: 0 == I&D combined
|
||||
#define CONFIG_SW 0x00100000 // scache port: 0==128, 1==64
|
||||
#define CONFIG_EW 0x000C0000 // System Port width: 0==64, 1==32
|
||||
#define CONFIG_SC 0x00020000 // 0 -> 2nd cache present
|
||||
#define CONFIG_SM 0x00010000 // 0 -> Dirty Shared Coherency enable
|
||||
#define CONFIG_BE 0x00008000 // Endian-ness: 1 --> BE
|
||||
#define CONFIG_EM 0x00004000 // 1 -> ECC mode, 0 -> parity
|
||||
#define CONFIG_EB 0x00002000 // Block order:1->sequent,0->subblock
|
||||
#define CONFIG_SS 0x00200000 /* Split scache: 0 == I&D combined */
|
||||
#define CONFIG_SW 0x00100000 /* scache port: 0==128, 1==64 */
|
||||
#define CONFIG_EW 0x000C0000 /* System Port width: 0==64, 1==32 */
|
||||
#define CONFIG_SC 0x00020000 /* 0 -> 2nd cache present */
|
||||
#define CONFIG_SM 0x00010000 /* 0 -> Dirty Shared Coherency enable */
|
||||
#define CONFIG_BE 0x00008000 /* Endian-ness: 1 --> BE */
|
||||
#define CONFIG_EM 0x00004000 /* 1 -> ECC mode, 0 -> parity */
|
||||
#define CONFIG_EB 0x00002000 /* Block order:1->sequent,0->subblock */
|
||||
|
||||
#define CONFIG_IC 0x00000E00 // Primary Icache size
|
||||
#define CONFIG_DC 0x000001C0 // Primary Dcache size
|
||||
#define CONFIG_IB 0x00000020 // Icache block size
|
||||
#define CONFIG_DB 0x00000010 // Dcache block size
|
||||
#define CONFIG_CU 0x00000008 // Update on Store-conditional
|
||||
#define CONFIG_K0 0x00000007 // K0SEG Coherency algorithm
|
||||
#define CONFIG_IC 0x00000E00 /* Primary Icache size */
|
||||
#define CONFIG_DC 0x000001C0 /* Primary Dcache size */
|
||||
#define CONFIG_IB 0x00000020 /* Icache block size */
|
||||
#define CONFIG_DB 0x00000010 /* Dcache block size */
|
||||
#define CONFIG_CU 0x00000008 /* Update on Store-conditional */
|
||||
#define CONFIG_K0 0x00000007 /* K0SEG Coherency algorithm */
|
||||
|
||||
#define CONFIG_UNCACHED 0x00000002 // K0 is uncached
|
||||
#define CONFIG_UNCACHED 0x00000002 /* K0 is uncached */
|
||||
#define CONFIG_NONCOHRNT 0x00000003
|
||||
#define CONFIG_COHRNT_EXLWR 0x00000005
|
||||
#define CONFIG_SB_SHFT 22 // shift SB to bit position 0
|
||||
#define CONFIG_IC_SHFT 9 // shift IC to bit position 0
|
||||
#define CONFIG_DC_SHFT 6 // shift DC to bit position 0
|
||||
#define CONFIG_BE_SHFT 15 // shift BE to bit position 0
|
||||
#define CONFIG_SB_SHFT 22 /* shift SB to bit position 0 */
|
||||
#define CONFIG_IC_SHFT 9 /* shift IC to bit position 0 */
|
||||
#define CONFIG_DC_SHFT 6 /* shift DC to bit position 0 */
|
||||
#define CONFIG_BE_SHFT 15 /* shift BE to bit position 0 */
|
||||
|
||||
// C0_TAGLO definitions for setting/getting cache states and physaddr bits
|
||||
#define SADDRMASK 0xFFFFE000 // 31..13 -> scache paddr bits 35..17
|
||||
#define SVINDEXMASK 0x00000380 // 9..7: prim virt index bits 14..12
|
||||
#define SSTATEMASK 0x00001C00 // bits 12..10 hold scache line state
|
||||
#define SINVALID 0x00000000 // invalid --> 000 == state 0
|
||||
#define SCLEANEXCL 0x00001000 // clean exclusive --> 100 == state 4
|
||||
#define SDIRTYEXCL 0x00001400 // dirty exclusive --> 101 == state 5
|
||||
#define SECC_MASK 0x0000007F // low 7 bits are ecc for the tag
|
||||
#define SADDR_SHIFT 4 // shift STagLo (31..13) to 35..17
|
||||
/* C0_TAGLO definitions for setting/getting cache states and physaddr bits */
|
||||
#define SADDRMASK 0xFFFFE000 /* 31..13 -> scache paddr bits 35..17 */
|
||||
#define SVINDEXMASK 0x00000380 /* 9..7: prim virt index bits 14..12 */
|
||||
#define SSTATEMASK 0x00001C00 /* bits 12..10 hold scache line state */
|
||||
#define SINVALID 0x00000000 /* invalid --> 000 == state 0 */
|
||||
#define SCLEANEXCL 0x00001000 /* clean exclusive --> 100 == state 4 */
|
||||
#define SDIRTYEXCL 0x00001400 /* dirty exclusive --> 101 == state 5 */
|
||||
#define SECC_MASK 0x0000007F /* low 7 bits are ecc for the tag */
|
||||
#define SADDR_SHIFT 4 /* shift STagLo (31..13) to 35..17 */
|
||||
|
||||
#define PADDRMASK 0xFFFFFF00 // PTagLo31..8->prim paddr bits35..12
|
||||
#define PADDR_SHIFT 4 // roll bits 35..12 down to 31..8
|
||||
#define PSTATEMASK 0x00C0 // bits 7..6 hold primary line state
|
||||
#define PINVALID 0x0000 // invalid --> 000 == state 0
|
||||
#define PCLEANEXCL 0x0080 // clean exclusive --> 10 == state 2
|
||||
#define PDIRTYEXCL 0x00C0 // dirty exclusive --> 11 == state 3
|
||||
#define PPARITY_MASK 0x0001 // low bit is parity bit (even).
|
||||
#define PADDRMASK 0xFFFFFF00 /* PTagLo31..8->prim paddr bits35..12 */
|
||||
#define PADDR_SHIFT 4 /* roll bits 35..12 down to 31..8 */
|
||||
#define PSTATEMASK 0x00C0 /* bits 7..6 hold primary line state */
|
||||
#define PINVALID 0x0000 /* invalid --> 000 == state 0 */
|
||||
#define PCLEANEXCL 0x0080 /* clean exclusive --> 10 == state 2 */
|
||||
#define PDIRTYEXCL 0x00C0 /* dirty exclusive --> 11 == state 3 */
|
||||
#define PPARITY_MASK 0x0001 /* low bit is parity bit (even). */
|
||||
|
||||
// C0_CACHE_ERR definitions.
|
||||
#define CACHERR_ER 0x80000000 // 0: inst ref, 1: data ref
|
||||
#define CACHERR_EC 0x40000000 // 0: primary, 1: secondary
|
||||
#define CACHERR_ED 0x20000000 // 1: data error
|
||||
#define CACHERR_ET 0x10000000 // 1: tag error
|
||||
#define CACHERR_ES 0x08000000 // 1: external ref, e.g. snoo
|
||||
#define CACHERR_EE 0x04000000 // error on SysAD bus
|
||||
#define CACHERR_EB 0x02000000 // complicated, see spec.
|
||||
#define CACHERR_EI 0x01000000 // complicated, see spec.
|
||||
#define CACHERR_SIDX_MASK 0x003FFFF8 // secondary cache index
|
||||
#define CACHERR_PIDX_MASK 0x00000007 // primary cache index
|
||||
#define CACHERR_PIDX_SHIFT 12 // bits 2..0 are paddr14..12
|
||||
/* C0_CACHE_ERR definitions. */
|
||||
#define CACHERR_ER 0x80000000 /* 0: inst ref, 1: data ref */
|
||||
#define CACHERR_EC 0x40000000 /* 0: primary, 1: secondary */
|
||||
#define CACHERR_ED 0x20000000 /* 1: data error */
|
||||
#define CACHERR_ET 0x10000000 /* 1: tag error */
|
||||
#define CACHERR_ES 0x08000000 /* 1: external ref, e.g. snoo */
|
||||
#define CACHERR_EE 0x04000000 /* error on SysAD bus */
|
||||
#define CACHERR_EB 0x02000000 /* complicated, see spec. */
|
||||
#define CACHERR_EI 0x01000000 /* complicated, see spec. */
|
||||
#define CACHERR_SIDX_MASK 0x003FFFF8 /* secondary cache index */
|
||||
#define CACHERR_PIDX_MASK 0x00000007 /* primary cache index */
|
||||
#define CACHERR_PIDX_SHIFT 12 /* bits 2..0 are paddr14..12 */
|
||||
|
||||
/*
|
||||
* R4000 family supports hardware watchpoints:
|
||||
@@ -311,57 +311,57 @@
|
||||
#define WATCHLO_VALIDMASK 0xFFFFFFFB
|
||||
#define WATCHHI_VALIDMASK 0x0000000F
|
||||
|
||||
// Coprocessor 0 registers
|
||||
/* Coprocessor 0 registers */
|
||||
#define C0_INX C_REG(0)
|
||||
#define C0_RAND C_REG(1)
|
||||
#define C0_ENTRYLO0 C_REG(2)
|
||||
#define C0_ENTRYLO1 C_REG(3)
|
||||
#define C0_CONTEXT C_REG(4)
|
||||
#define C0_PAGEMASK C_REG(5) // page mask
|
||||
#define C0_WIRED C_REG(6) // # wired entries in tlb
|
||||
#define C0_PAGEMASK C_REG(5) /* page mask */
|
||||
#define C0_WIRED C_REG(6) /* # wired entries in tlb */
|
||||
#define C0_BADVADDR C_REG(8)
|
||||
#define C0_COUNT C_REG(9) // free-running counter
|
||||
#define C0_COUNT C_REG(9) /* free-running counter */
|
||||
#define C0_ENTRYHI C_REG(10)
|
||||
#define C0_COMPARE C_REG(11) // counter comparison reg.
|
||||
#define C0_COMPARE C_REG(11) /* counter comparison reg. */
|
||||
#define C0_SR C_REG(12)
|
||||
#define C0_CAUSE C_REG(13)
|
||||
#define C0_EPC C_REG(14)
|
||||
#define C0_PRID C_REG(15) // revision identifier
|
||||
#define C0_CONFIG C_REG(16) // hardware configuration
|
||||
#define C0_LLADDR C_REG(17) // load linked address
|
||||
#define C0_WATCHLO C_REG(18) // watchpoint
|
||||
#define C0_WATCHHI C_REG(19) // watchpoint
|
||||
#define C0_ECC C_REG(26) // S-cache ECC and primary parity
|
||||
#define C0_CACHE_ERR C_REG(27) // cache error status
|
||||
#define C0_TAGLO C_REG(28) // cache operations
|
||||
#define C0_TAGHI C_REG(29) // cache operations
|
||||
#define C0_ERROR_EPC C_REG(30) // ECC error prg. counter
|
||||
#define C0_PRID C_REG(15) /* revision identifier */
|
||||
#define C0_CONFIG C_REG(16) /* hardware configuration */
|
||||
#define C0_LLADDR C_REG(17) /* load linked address */
|
||||
#define C0_WATCHLO C_REG(18) /* watchpoint */
|
||||
#define C0_WATCHHI C_REG(19) /* watchpoint */
|
||||
#define C0_ECC C_REG(26) /* S-cache ECC and primary parity */
|
||||
#define C0_CACHE_ERR C_REG(27) /* cache error status */
|
||||
#define C0_TAGLO C_REG(28) /* cache operations */
|
||||
#define C0_TAGHI C_REG(29) /* cache operations */
|
||||
#define C0_ERROR_EPC C_REG(30) /* ECC error prg. counter */
|
||||
|
||||
// floating-point status register
|
||||
/* floating-point status register */
|
||||
#define C1_FPCSR C_REG(31)
|
||||
|
||||
#define FPCSR_FS 0x01000000 // flush denorm to zero
|
||||
#define FPCSR_C 0x00800000 // condition bit
|
||||
#define FPCSR_CE 0x00020000 // cause: unimplemented operation
|
||||
#define FPCSR_CV 0x00010000 // cause: invalid operation
|
||||
#define FPCSR_CZ 0x00008000 // cause: division by zero
|
||||
#define FPCSR_CO 0x00004000 // cause: overflow
|
||||
#define FPCSR_CU 0x00002000 // cause: underflow
|
||||
#define FPCSR_CI 0x00001000 // cause: inexact operation
|
||||
#define FPCSR_EV 0x00000800 // enable: invalid operation
|
||||
#define FPCSR_EZ 0x00000400 // enable: division by zero
|
||||
#define FPCSR_EO 0x00000200 // enable: overflow
|
||||
#define FPCSR_EU 0x00000100 // enable: underflow
|
||||
#define FPCSR_EI 0x00000080 // enable: inexact operation
|
||||
#define FPCSR_FV 0x00000040 // flag: invalid operation
|
||||
#define FPCSR_FZ 0x00000020 // flag: division by zero
|
||||
#define FPCSR_FO 0x00000010 // flag: overflow
|
||||
#define FPCSR_FU 0x00000008 // flag: underflow
|
||||
#define FPCSR_FI 0x00000004 // flag: inexact operation
|
||||
#define FPCSR_RM_MASK 0x00000003 // rounding mode mask
|
||||
#define FPCSR_RM_RN 0x00000000 // round to nearest
|
||||
#define FPCSR_RM_RZ 0x00000001 // round to zero
|
||||
#define FPCSR_RM_RP 0x00000002 // round to positive infinity
|
||||
#define FPCSR_RM_RM 0x00000003 // round to negative infinity
|
||||
#define FPCSR_FS 0x01000000 /* flush denorm to zero */
|
||||
#define FPCSR_C 0x00800000 /* condition bit */
|
||||
#define FPCSR_CE 0x00020000 /* cause: unimplemented operation */
|
||||
#define FPCSR_CV 0x00010000 /* cause: invalid operation */
|
||||
#define FPCSR_CZ 0x00008000 /* cause: division by zero */
|
||||
#define FPCSR_CO 0x00004000 /* cause: overflow */
|
||||
#define FPCSR_CU 0x00002000 /* cause: underflow */
|
||||
#define FPCSR_CI 0x00001000 /* cause: inexact operation */
|
||||
#define FPCSR_EV 0x00000800 /* enable: invalid operation */
|
||||
#define FPCSR_EZ 0x00000400 /* enable: division by zero */
|
||||
#define FPCSR_EO 0x00000200 /* enable: overflow */
|
||||
#define FPCSR_EU 0x00000100 /* enable: underflow */
|
||||
#define FPCSR_EI 0x00000080 /* enable: inexact operation */
|
||||
#define FPCSR_FV 0x00000040 /* flag: invalid operation */
|
||||
#define FPCSR_FZ 0x00000020 /* flag: division by zero */
|
||||
#define FPCSR_FO 0x00000010 /* flag: overflow */
|
||||
#define FPCSR_FU 0x00000008 /* flag: underflow */
|
||||
#define FPCSR_FI 0x00000004 /* flag: inexact operation */
|
||||
#define FPCSR_RM_MASK 0x00000003 /* rounding mode mask */
|
||||
#define FPCSR_RM_RN 0x00000000 /* round to nearest */
|
||||
#define FPCSR_RM_RZ 0x00000001 /* round to zero */
|
||||
#define FPCSR_RM_RP 0x00000002 /* round to positive infinity */
|
||||
#define FPCSR_RM_RM 0x00000003 /* round to negative infinity */
|
||||
|
||||
#endif
|
||||
|
||||
+70
-21
@@ -6,55 +6,104 @@
|
||||
#define _MIPS_ISA_MIPS2 2
|
||||
#define _MIPS_ISA_MIPS3 3
|
||||
#define _MIPS_ISA_MIPS4 4
|
||||
|
||||
#define _MIPS_SIM_ABI32 1 /* MIPS MSIG calling convention */
|
||||
#define _MIPS_SIM_NABI32 2 /* MIPS new 32-bit abi */
|
||||
/* NABI32 is 64bit calling convention but 32bit type sizes) */
|
||||
#define _MIPS_SIM_ABI64 3 /* MIPS 64 calling convention */
|
||||
#endif
|
||||
|
||||
#ifndef _LANGUAGE_C
|
||||
|
||||
#ifdef __GNUC__
|
||||
#define TYPE(x, t) .type x, @t
|
||||
#define SIZE(x) .size x, . - x
|
||||
#else
|
||||
#define TYPE(x, t)
|
||||
#define SIZE(x)
|
||||
#endif
|
||||
|
||||
#define LEAF(x) \
|
||||
.balign 4 ;\
|
||||
.align 2 ;\
|
||||
.globl x ;\
|
||||
.type x, @function ;\
|
||||
TYPE(x, function) ;\
|
||||
.ent x, 0 ;\
|
||||
x: ;\
|
||||
.ent x, 0 ;\
|
||||
.frame $sp, 0, $ra
|
||||
.frame sp, 0, ra
|
||||
|
||||
#define XLEAF(x) \
|
||||
.balign 4 ;\
|
||||
.align 2 ;\
|
||||
.globl x ;\
|
||||
.type x, @function ;\
|
||||
x: ;\
|
||||
.aent x, 0
|
||||
TYPE(x, function) ;\
|
||||
.aent x, 0 ;\
|
||||
x:
|
||||
|
||||
#define NESTED(x, fsize, ra) \
|
||||
.globl x ;\
|
||||
.ent x, 0 ;\
|
||||
x: ;\
|
||||
.ent x, 0 ;\
|
||||
.frame $sp, fsize, ra
|
||||
.frame sp, fsize, ra
|
||||
|
||||
#define XNESTED(x) \
|
||||
.globl x ;\
|
||||
x: ;\
|
||||
.aent x, 0
|
||||
.aent x, 0 ;\
|
||||
x:
|
||||
|
||||
#define END(x) \
|
||||
.size x, . - x ;\
|
||||
SIZE(x) ;\
|
||||
.end x
|
||||
|
||||
#define IMPORT(x, size) \
|
||||
.extern x, size
|
||||
|
||||
#define EXPORT(x) \
|
||||
.globl x ;\
|
||||
x:
|
||||
|
||||
#ifdef __sgi
|
||||
#define IMPORT(sym, size) \
|
||||
.extern sym, size
|
||||
#else
|
||||
#define IMPORT(sym, size)
|
||||
#endif
|
||||
|
||||
#define DATA(x) \
|
||||
.balign 4 ;\
|
||||
.align 2 ;\
|
||||
.globl x ;\
|
||||
.type x, @object ;\
|
||||
TYPE(x, object) ;\
|
||||
x:
|
||||
|
||||
#define ENDDATA(x) \
|
||||
.size x, . - x
|
||||
SIZE(x)
|
||||
|
||||
#define MFC0(dst, src) \
|
||||
.set noreorder; mfc0 dst, src; .set reorder
|
||||
#define MTC0(dst, src) \
|
||||
.set noreorder; mtc0 dst, src; .set reorder
|
||||
|
||||
#define CFC1(dst, src) \
|
||||
.set noreorder; cfc1 dst, src; .set reorder
|
||||
#define CTC1(src, dst) \
|
||||
.set noreorder; ctc1 src, dst; .set reorder
|
||||
|
||||
#define NOP \
|
||||
.set noreorder; nop; .set reorder
|
||||
|
||||
#define TLBWI \
|
||||
.set noreorder; tlbwi; .set reorder
|
||||
|
||||
#define TLBR \
|
||||
.set noreorder; tlbr; .set reorder
|
||||
|
||||
#define TLBP \
|
||||
.set noreorder; tlbp; .set reorder
|
||||
|
||||
#ifdef __sgi
|
||||
#define ABS(x, y) \
|
||||
.globl x; \
|
||||
x = y
|
||||
#else
|
||||
#define ABS(x, y) \
|
||||
.globl x; \
|
||||
.set x, y
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -62,11 +111,11 @@
|
||||
* Stack Alignment
|
||||
*/
|
||||
#if (_MIPS_SIM == _ABIO32)
|
||||
#define NARGSAVE 4 // space for 4 args must be allocated
|
||||
#define NARGSAVE 4 /* space for 4 args must be allocated */
|
||||
#define ALSZ (8-1)
|
||||
#define ALMASK ~(8-1)
|
||||
#elif (_MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64)
|
||||
#define NARGSAVE 0 // no caller responsibilities
|
||||
#define NARGSAVE 0 /* no caller responsibilities */
|
||||
#define ALSZ (16-1)
|
||||
#define ALMASK ~(16-1)
|
||||
#endif
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
#ifndef ULTRA64_EXCEPTION_H
|
||||
#define ULTRA64_EXCEPTION_H
|
||||
|
||||
// Interrupt masks
|
||||
/* Interrupt masks */
|
||||
#define OS_IM_NONE 0x00000001
|
||||
#define OS_IM_RCP 0x00000401
|
||||
#define OS_IM_SW1 0x00000501
|
||||
@@ -23,7 +23,7 @@
|
||||
#define RCP_IMASK 0x003F0000
|
||||
#define RCP_IMASKSHIFT 16
|
||||
|
||||
// OSHWIntr values
|
||||
/* OSHWIntr values */
|
||||
#define OS_INTR_CART 1
|
||||
|
||||
#ifdef _LANGUAGE_C
|
||||
@@ -51,11 +51,11 @@ extern __osHwInt __osHwIntTable[];
|
||||
|
||||
#else
|
||||
|
||||
// __osHwInt struct member offsets
|
||||
/* __osHwInt struct member offsets */
|
||||
#define HWINT_CALLBACK 0x00
|
||||
#define HWINT_SP 0x04
|
||||
|
||||
// __osHwInt struct size
|
||||
/* __osHwInt struct size */
|
||||
#define HWINT_SIZE 0x8
|
||||
|
||||
#endif
|
||||
|
||||
@@ -47,7 +47,7 @@ typedef struct OSMesgQueue {
|
||||
|
||||
#else
|
||||
|
||||
// OSMesgQueue struct member offsets
|
||||
/* OSMesgQueue struct member offsets */
|
||||
|
||||
#define MQ_MTQUEUE 0x00
|
||||
#define MQ_FULLQUEUE 0x04
|
||||
|
||||
+201
-201
@@ -114,13 +114,13 @@
|
||||
/**
|
||||
* External device info
|
||||
*/
|
||||
#define DEVICE_TYPE_CART 0 // ROM cartridge
|
||||
#define DEVICE_TYPE_BULK 1 // ROM bulk
|
||||
#define DEVICE_TYPE_64DD 2 // 64 Disk Drive
|
||||
#define DEVICE_TYPE_SRAM 3 // SRAM
|
||||
// 4-6 are reserved
|
||||
#define DEVICE_TYPE_INIT 7 // initial value
|
||||
// 8-14 are reserved
|
||||
#define DEVICE_TYPE_CART 0 /* ROM cartridge */
|
||||
#define DEVICE_TYPE_BULK 1 /* ROM bulk */
|
||||
#define DEVICE_TYPE_64DD 2 /* 64 Disk Drive */
|
||||
#define DEVICE_TYPE_SRAM 3 /* SRAM */
|
||||
/* 4-6 are reserved */
|
||||
#define DEVICE_TYPE_INIT 7 /* initial value */
|
||||
/* 8-14 are reserved */
|
||||
|
||||
|
||||
/**
|
||||
@@ -138,31 +138,31 @@
|
||||
|
||||
#define SP_BASE_REG 0x04040000
|
||||
|
||||
// SP memory address (R/W): [12] 0=DMEM,1=IMEM, [11:0] DMEM/IMEM address
|
||||
/* SP memory address (R/W): [12] 0=DMEM,1=IMEM, [11:0] DMEM/IMEM address */
|
||||
#define SP_MEM_ADDR_REG (SP_BASE_REG + 0x00)
|
||||
|
||||
// SP DRAM DMA address (R/W): [23:0] RDRAM address
|
||||
/* SP DRAM DMA address (R/W): [23:0] RDRAM address */
|
||||
#define SP_DRAM_ADDR_REG (SP_BASE_REG + 0x04)
|
||||
|
||||
// SP read DMA length (R/W): [31:20] skip, [19:12] count, [11:0] length; RDRAM -> I/DMEM
|
||||
/* SP read DMA length (R/W): [31:20] skip, [19:12] count, [11:0] length; RDRAM -> I/DMEM */
|
||||
#define SP_RD_LEN_REG (SP_BASE_REG + 0x08)
|
||||
|
||||
// SP write DMA length (R/W): [31:20] skip, [19:12] count, [11:0] length; I/DMEM -> RDRAM
|
||||
/* SP write DMA length (R/W): [31:20] skip, [19:12] count, [11:0] length; I/DMEM -> RDRAM */
|
||||
#define SP_WR_LEN_REG (SP_BASE_REG + 0x0C)
|
||||
|
||||
// SP status (R/W): [14:0] valid bits; see below for write/read mode
|
||||
/* SP status (R/W): [14:0] valid bits; see below for write/read mode */
|
||||
#define SP_STATUS_REG (SP_BASE_REG + 0x10)
|
||||
|
||||
// SP DMA full (R): [0] dma full
|
||||
/* SP DMA full (R): [0] dma full */
|
||||
#define SP_DMA_FULL_REG (SP_BASE_REG + 0x14)
|
||||
|
||||
// SP DMA busy (R): [0] dma busy
|
||||
/* SP DMA busy (R): [0] dma busy */
|
||||
#define SP_DMA_BUSY_REG (SP_BASE_REG + 0x18)
|
||||
|
||||
// SP semaphore (R/W): Read: [0] acquire semaphore; Write: [] release semaphore
|
||||
/* SP semaphore (R/W): Read: [0] acquire semaphore; Write: [] release semaphore */
|
||||
#define SP_SEMAPHORE_REG (SP_BASE_REG + 0x1C)
|
||||
|
||||
// SP PC (R/W): [11:0] program counter
|
||||
/* SP PC (R/W): [11:0] program counter */
|
||||
#define SP_PC_REG 0x04080000
|
||||
|
||||
/*
|
||||
@@ -174,31 +174,31 @@
|
||||
/*
|
||||
* SP_STATUS_REG: write bits
|
||||
*/
|
||||
#define SP_CLR_HALT (1 << 0) // clear halt
|
||||
#define SP_SET_HALT (1 << 1) // set halt
|
||||
#define SP_CLR_BROKE (1 << 2) // clear broke
|
||||
#define SP_CLR_INTR (1 << 3) // clear interrupt
|
||||
#define SP_SET_INTR (1 << 4) // set interrupt
|
||||
#define SP_CLR_SSTEP (1 << 5) // clear sstep
|
||||
#define SP_SET_SSTEP (1 << 6) // set sstep
|
||||
#define SP_CLR_INTR_BREAK (1 << 7) // clear interrupt on break
|
||||
#define SP_SET_INTR_BREAK (1 << 8) // set interrupt on break
|
||||
#define SP_CLR_SIG0 (1 << 9) // clear signal 0
|
||||
#define SP_SET_SIG0 (1 << 10) // set signal 0
|
||||
#define SP_CLR_SIG1 (1 << 11) // clear signal 1
|
||||
#define SP_SET_SIG1 (1 << 12) // set signal 1
|
||||
#define SP_CLR_SIG2 (1 << 13) // clear signal 2
|
||||
#define SP_SET_SIG2 (1 << 14) // set signal 2
|
||||
#define SP_CLR_SIG3 (1 << 15) // clear signal 3
|
||||
#define SP_SET_SIG3 (1 << 16) // set signal 3
|
||||
#define SP_CLR_SIG4 (1 << 17) // clear signal 4
|
||||
#define SP_SET_SIG4 (1 << 18) // set signal 4
|
||||
#define SP_CLR_SIG5 (1 << 19) // clear signal 5
|
||||
#define SP_SET_SIG5 (1 << 20) // set signal 5
|
||||
#define SP_CLR_SIG6 (1 << 21) // clear signal 6
|
||||
#define SP_SET_SIG6 (1 << 22) // set signal 6
|
||||
#define SP_CLR_SIG7 (1 << 23) // clear signal 7
|
||||
#define SP_SET_SIG7 (1 << 24) // set signal 7
|
||||
#define SP_CLR_HALT (1 << 0) /* clear halt */
|
||||
#define SP_SET_HALT (1 << 1) /* set halt */
|
||||
#define SP_CLR_BROKE (1 << 2) /* clear broke */
|
||||
#define SP_CLR_INTR (1 << 3) /* clear interrupt */
|
||||
#define SP_SET_INTR (1 << 4) /* set interrupt */
|
||||
#define SP_CLR_SSTEP (1 << 5) /* clear sstep */
|
||||
#define SP_SET_SSTEP (1 << 6) /* set sstep */
|
||||
#define SP_CLR_INTR_BREAK (1 << 7) /* clear interrupt on break */
|
||||
#define SP_SET_INTR_BREAK (1 << 8) /* set interrupt on break */
|
||||
#define SP_CLR_SIG0 (1 << 9) /* clear signal 0 */
|
||||
#define SP_SET_SIG0 (1 << 10) /* set signal 0 */
|
||||
#define SP_CLR_SIG1 (1 << 11) /* clear signal 1 */
|
||||
#define SP_SET_SIG1 (1 << 12) /* set signal 1 */
|
||||
#define SP_CLR_SIG2 (1 << 13) /* clear signal 2 */
|
||||
#define SP_SET_SIG2 (1 << 14) /* set signal 2 */
|
||||
#define SP_CLR_SIG3 (1 << 15) /* clear signal 3 */
|
||||
#define SP_SET_SIG3 (1 << 16) /* set signal 3 */
|
||||
#define SP_CLR_SIG4 (1 << 17) /* clear signal 4 */
|
||||
#define SP_SET_SIG4 (1 << 18) /* set signal 4 */
|
||||
#define SP_CLR_SIG5 (1 << 19) /* clear signal 5 */
|
||||
#define SP_SET_SIG5 (1 << 20) /* set signal 5 */
|
||||
#define SP_CLR_SIG6 (1 << 21) /* clear signal 6 */
|
||||
#define SP_SET_SIG6 (1 << 22) /* set signal 6 */
|
||||
#define SP_CLR_SIG7 (1 << 23) /* clear signal 7 */
|
||||
#define SP_SET_SIG7 (1 << 24) /* set signal 7 */
|
||||
|
||||
/*
|
||||
* SP_STATUS_REG: read bits
|
||||
@@ -238,22 +238,22 @@
|
||||
#define SP_SET_CPUSIGNAL SP_SET_SIG4
|
||||
#define SP_STATUS_CPUSIGNAL SP_STATUS_SIG4
|
||||
|
||||
// SP IMEM BIST REG (R/W): [6:0] BIST status bits; see below for detail
|
||||
/* SP IMEM BIST REG (R/W): [6:0] BIST status bits; see below for detail */
|
||||
#define SP_IBIST_REG 0x04080004
|
||||
|
||||
/*
|
||||
* SP_IBIST_REG: write bits
|
||||
*/
|
||||
#define SP_IBIST_CHECK (1 << 0) // BIST check
|
||||
#define SP_IBIST_GO (1 << 1) // BIST go
|
||||
#define SP_IBIST_CLEAR (1 << 2) // BIST clear
|
||||
#define SP_IBIST_CHECK (1 << 0) /* BIST check */
|
||||
#define SP_IBIST_GO (1 << 1) /* BIST go */
|
||||
#define SP_IBIST_CLEAR (1 << 2) /* BIST clear */
|
||||
|
||||
/*
|
||||
* SP_BIST_REG: read bits
|
||||
* First 2 bits are same as in write mode
|
||||
*/
|
||||
#define SP_IBIST_DONE (1 << 2)
|
||||
#define SP_IBIST_FAILED 0x78 // bits [6:3], BIST fail
|
||||
#define SP_IBIST_FAILED 0x78 /* bits [6:3], BIST fail */
|
||||
|
||||
|
||||
/**
|
||||
@@ -261,28 +261,28 @@
|
||||
*/
|
||||
#define DPC_BASE_REG 0x04100000
|
||||
|
||||
// DP CMD DMA start (R/W): [23:0] DMEM/RDRAM start address
|
||||
/* DP CMD DMA start (R/W): [23:0] DMEM/RDRAM start address */
|
||||
#define DPC_START_REG (DPC_BASE_REG + 0x00)
|
||||
|
||||
// DP CMD DMA end (R/W): [23:0] DMEM/RDRAM end address
|
||||
/* DP CMD DMA end (R/W): [23:0] DMEM/RDRAM end address */
|
||||
#define DPC_END_REG (DPC_BASE_REG + 0x04)
|
||||
|
||||
// DP CMD DMA end (R): [23:0] DMEM/RDRAM current address
|
||||
/* DP CMD DMA end (R): [23:0] DMEM/RDRAM current address */
|
||||
#define DPC_CURRENT_REG (DPC_BASE_REG + 0x08)
|
||||
|
||||
// DP CMD status (R/W): [9:0] valid bits - see below for definitions
|
||||
/* DP CMD status (R/W): [9:0] valid bits - see below for definitions */
|
||||
#define DPC_STATUS_REG (DPC_BASE_REG + 0x0C)
|
||||
|
||||
// DP clock counter (R): [23:0] clock counter
|
||||
/* DP clock counter (R): [23:0] clock counter */
|
||||
#define DPC_CLOCK_REG (DPC_BASE_REG + 0x10)
|
||||
|
||||
// DP buffer busy counter (R): [23:0] clock counter
|
||||
/* DP buffer busy counter (R): [23:0] clock counter */
|
||||
#define DPC_BUFBUSY_REG (DPC_BASE_REG + 0x14)
|
||||
|
||||
// DP pipe busy counter (R): [23:0] clock counter
|
||||
/* DP pipe busy counter (R): [23:0] clock counter */
|
||||
#define DPC_PIPEBUSY_REG (DPC_BASE_REG + 0x18)
|
||||
|
||||
// DP TMEM load counter (R): [23:0] clock counter
|
||||
/* DP TMEM load counter (R): [23:0] clock counter */
|
||||
#define DPC_TMEM_REG (DPC_BASE_REG + 0x1C)
|
||||
|
||||
/*
|
||||
@@ -320,16 +320,16 @@
|
||||
*/
|
||||
#define DPS_BASE_REG 0x04200000
|
||||
|
||||
// DP tmem built-in self-test (R/W): [10:0] BIST status bits
|
||||
/* DP tmem built-in self-test (R/W): [10:0] BIST status bits */
|
||||
#define DPS_TBIST_REG (DPS_BASE_REG + 0x00)
|
||||
|
||||
// DP span test mode (R/W): [0] Span buffer test access enable
|
||||
/* DP span test mode (R/W): [0] Span buffer test access enable */
|
||||
#define DPS_TEST_MODE_REG (DPS_BASE_REG + 0x04)
|
||||
|
||||
// DP span buffer test address (R/W): [6:0] bits
|
||||
/* DP span buffer test address (R/W): [6:0] bits */
|
||||
#define DPS_BUFTEST_ADDR_REG (DPS_BASE_REG + 0x08)
|
||||
|
||||
// DP span buffer test data (R/W): [31:0] span buffer data
|
||||
/* DP span buffer test data (R/W): [31:0] span buffer data */
|
||||
#define DPS_BUFTEST_DATA_REG (DPS_BASE_REG + 0x0C)
|
||||
|
||||
/*
|
||||
@@ -344,7 +344,7 @@
|
||||
* First 2 bits are same as in write mode
|
||||
*/
|
||||
#define DPS_TBIST_DONE (1 << 2)
|
||||
#define DPS_TBIST_FAILED 0x7F8 // bits [10:3], BIST fail
|
||||
#define DPS_TBIST_FAILED 0x7F8 /* bits [10:3], BIST fail */
|
||||
|
||||
|
||||
/**
|
||||
@@ -352,22 +352,22 @@
|
||||
*/
|
||||
#define MI_BASE_REG 0x04300000
|
||||
|
||||
// MI init mode (W): [11] clear DP interrupt, [9/10] clear/set ebus test mode
|
||||
// [8] set init mode, [7] clear init mode, [6:0] init length
|
||||
// (R): [8] ebus test mode, [7] init mode, [6:0] init length
|
||||
/* MI init mode (W): [11] clear DP interrupt, [9/10] clear/set ebus test mode */
|
||||
/* [8] set init mode, [7] clear init mode, [6:0] init length */
|
||||
/* (R): [8] ebus test mode, [7] init mode, [6:0] init length */
|
||||
#define MI_INIT_MODE_REG (MI_BASE_REG + 0x00)
|
||||
#define MI_MODE_REG MI_INIT_MODE_REG
|
||||
|
||||
/*
|
||||
* MI_MODE_REG: write bits
|
||||
*/
|
||||
#define MI_CLR_INIT (1 << 7) // clear init mode
|
||||
#define MI_SET_INIT (1 << 8) // set init mode
|
||||
#define MI_CLR_EBUS (1 << 9) // clear ebus test
|
||||
#define MI_SET_EBUS (1 << 10) // set ebus test mode
|
||||
#define MI_CLR_DP_INTR (1 << 11) // clear dp interrupt
|
||||
#define MI_CLR_RDRAM (1 << 12) // clear RDRAM reg
|
||||
#define MI_SET_RDRAM (1 << 13) // set RDRAM reg mode
|
||||
#define MI_CLR_INIT (1 << 7) /* clear init mode */
|
||||
#define MI_SET_INIT (1 << 8) /* set init mode */
|
||||
#define MI_CLR_EBUS (1 << 9) /* clear ebus test */
|
||||
#define MI_SET_EBUS (1 << 10) /* set ebus test mode */
|
||||
#define MI_CLR_DP_INTR (1 << 11) /* clear dp interrupt */
|
||||
#define MI_CLR_RDRAM (1 << 12) /* clear RDRAM reg */
|
||||
#define MI_SET_RDRAM (1 << 13) /* set RDRAM reg mode */
|
||||
|
||||
/*
|
||||
* MI_MODE_REG: read bits
|
||||
@@ -376,52 +376,52 @@
|
||||
#define MI_MODE_EBUS (1 << 8) /* ebus test mode */
|
||||
#define MI_MODE_RDRAM (1 << 9) /* RDRAM reg mode */
|
||||
|
||||
// MI version (R): [31:24] rsp, [23:16] rdp, [15:8] rac, [7:0] io
|
||||
/* MI version (R): [31:24] rsp, [23:16] rdp, [15:8] rac, [7:0] io */
|
||||
#define MI_VERSION_REG (MI_BASE_REG + 0x04)
|
||||
#define MI_NOOP_REG MI_VERSION_REG
|
||||
|
||||
// MI interrupt (R): [5:0] valid bits - see below for bit patterns
|
||||
/* MI interrupt (R): [5:0] valid bits - see below for bit patterns */
|
||||
#define MI_INTR_REG (MI_BASE_REG + 0x08)
|
||||
|
||||
// MI interrupt mask (R): [5:0] valid bits - see below for bit patterns
|
||||
// (W): [11:0] valid bits - see below for bit patterns
|
||||
/* MI interrupt mask (R): [5:0] valid bits - see below for bit patterns */
|
||||
/* (W): [11:0] valid bits - see below for bit patterns */
|
||||
#define MI_INTR_MASK_REG (MI_BASE_REG + 0x0C)
|
||||
|
||||
/*
|
||||
* MI_INTR_REG: read bits
|
||||
*/
|
||||
#define MI_INTR_SP (1 << 0) // SP intr
|
||||
#define MI_INTR_SI (1 << 1) // SI intr
|
||||
#define MI_INTR_AI (1 << 2) // AI intr
|
||||
#define MI_INTR_VI (1 << 3) // VI intr
|
||||
#define MI_INTR_PI (1 << 4) // PI intr
|
||||
#define MI_INTR_DP (1 << 5) // DP intr
|
||||
#define MI_INTR_SP (1 << 0) /* SP intr */
|
||||
#define MI_INTR_SI (1 << 1) /* SI intr */
|
||||
#define MI_INTR_AI (1 << 2) /* AI intr */
|
||||
#define MI_INTR_VI (1 << 3) /* VI intr */
|
||||
#define MI_INTR_PI (1 << 4) /* PI intr */
|
||||
#define MI_INTR_DP (1 << 5) /* DP intr */
|
||||
|
||||
/*
|
||||
* MI_INTR_MASK_REG: write bits
|
||||
*/
|
||||
#define MI_INTR_MASK_CLR_SP (1 << 0) // clear SP mask
|
||||
#define MI_INTR_MASK_SET_SP (1 << 1) // set SP mask
|
||||
#define MI_INTR_MASK_CLR_SI (1 << 2) // clear SI mask
|
||||
#define MI_INTR_MASK_SET_SI (1 << 3) // set SI mask
|
||||
#define MI_INTR_MASK_CLR_AI (1 << 4) // clear AI mask
|
||||
#define MI_INTR_MASK_SET_AI (1 << 5) // set AI mask
|
||||
#define MI_INTR_MASK_CLR_VI (1 << 6) // clear VI mask
|
||||
#define MI_INTR_MASK_SET_VI (1 << 7) // set VI mask
|
||||
#define MI_INTR_MASK_CLR_PI (1 << 8) // clear PI mask
|
||||
#define MI_INTR_MASK_SET_PI (1 << 9) // set PI mask
|
||||
#define MI_INTR_MASK_CLR_DP (1 << 10) // clear DP mask
|
||||
#define MI_INTR_MASK_SET_DP (1 << 11) // set DP mask
|
||||
#define MI_INTR_MASK_CLR_SP (1 << 0) /* clear SP mask */
|
||||
#define MI_INTR_MASK_SET_SP (1 << 1) /* set SP mask */
|
||||
#define MI_INTR_MASK_CLR_SI (1 << 2) /* clear SI mask */
|
||||
#define MI_INTR_MASK_SET_SI (1 << 3) /* set SI mask */
|
||||
#define MI_INTR_MASK_CLR_AI (1 << 4) /* clear AI mask */
|
||||
#define MI_INTR_MASK_SET_AI (1 << 5) /* set AI mask */
|
||||
#define MI_INTR_MASK_CLR_VI (1 << 6) /* clear VI mask */
|
||||
#define MI_INTR_MASK_SET_VI (1 << 7) /* set VI mask */
|
||||
#define MI_INTR_MASK_CLR_PI (1 << 8) /* clear PI mask */
|
||||
#define MI_INTR_MASK_SET_PI (1 << 9) /* set PI mask */
|
||||
#define MI_INTR_MASK_CLR_DP (1 << 10) /* clear DP mask */
|
||||
#define MI_INTR_MASK_SET_DP (1 << 11) /* set DP mask */
|
||||
|
||||
/*
|
||||
* MI_INTR_MASK_REG: read bits
|
||||
*/
|
||||
#define MI_INTR_MASK_SP (1 << 0) // SP intr mask
|
||||
#define MI_INTR_MASK_SI (1 << 1) // SI intr mask
|
||||
#define MI_INTR_MASK_AI (1 << 2) // AI intr mask
|
||||
#define MI_INTR_MASK_VI (1 << 3) // VI intr mask
|
||||
#define MI_INTR_MASK_PI (1 << 4) // PI intr mask
|
||||
#define MI_INTR_MASK_DP (1 << 5) // DP intr mask
|
||||
#define MI_INTR_MASK_SP (1 << 0) /* SP intr mask */
|
||||
#define MI_INTR_MASK_SI (1 << 1) /* SI intr mask */
|
||||
#define MI_INTR_MASK_AI (1 << 2) /* AI intr mask */
|
||||
#define MI_INTR_MASK_VI (1 << 3) /* VI intr mask */
|
||||
#define MI_INTR_MASK_PI (1 << 4) /* PI intr mask */
|
||||
#define MI_INTR_MASK_DP (1 << 5) /* DP intr mask */
|
||||
|
||||
|
||||
/**
|
||||
@@ -454,90 +454,90 @@
|
||||
#define VI_CONTROL_REG (VI_BASE_REG + 0x00)
|
||||
#define VI_STATUS_REG VI_CONTROL_REG
|
||||
|
||||
// VI origin (R/W): [23:0] frame buffer origin in bytes
|
||||
/* VI origin (R/W): [23:0] frame buffer origin in bytes */
|
||||
#define VI_ORIGIN_REG (VI_BASE_REG + 0x04)
|
||||
#define VI_DRAM_ADDR_REG VI_ORIGIN_REG
|
||||
|
||||
// VI width (R/W): [11:0] frame buffer line width in pixels
|
||||
/* VI width (R/W): [11:0] frame buffer line width in pixels */
|
||||
#define VI_WIDTH_REG (VI_BASE_REG + 0x08)
|
||||
#define VI_H_WIDTH_REG VI_WIDTH_REG
|
||||
|
||||
// VI vertical intr (R/W): [9:0] interrupt when current half-line = V_INTR
|
||||
/* VI vertical intr (R/W): [9:0] interrupt when current half-line = V_INTR */
|
||||
#define VI_INTR_REG (VI_BASE_REG + 0x0C)
|
||||
#define VI_V_INTR_REG VI_INTR_REG
|
||||
|
||||
// VI current vertical line (R/W): [9:0] current half line, sampled once per
|
||||
// line (the lsb of V_CURRENT is constant within a field, and in interlaced
|
||||
// modes gives the field number - which is constant for non-interlaced modes)
|
||||
// - Any write to this register will clear interrupt line
|
||||
/* VI current vertical line (R/W): [9:0] current half line, sampled once per */
|
||||
/* line (the lsb of V_CURRENT is constant within a field, and in interlaced */
|
||||
/* modes gives the field number - which is constant for non-interlaced modes) */
|
||||
/* - Any write to this register will clear interrupt line */
|
||||
#define VI_CURRENT_REG (VI_BASE_REG + 0x10)
|
||||
#define VI_V_CURRENT_LINE_REG VI_CURRENT_REG
|
||||
|
||||
// VI video timing (R/W): [29:20] start of color burst in pixels from h-sync
|
||||
// [19:16] vertical sync width in half lines,
|
||||
// [15: 8] color burst width in pixels,
|
||||
// [ 7: 0] horizontal sync width in pixels,
|
||||
/* VI video timing (R/W): [29:20] start of color burst in pixels from h-sync */
|
||||
/* [19:16] vertical sync width in half lines, */
|
||||
/* [15: 8] color burst width in pixels, */
|
||||
/* [ 7: 0] horizontal sync width in pixels, */
|
||||
#define VI_BURST_REG (VI_BASE_REG + 0x14)
|
||||
#define VI_TIMING_REG VI_BURST_REG
|
||||
|
||||
// VI vertical sync (R/W): [9:0] number of half-lines per field
|
||||
/* VI vertical sync (R/W): [9:0] number of half-lines per field */
|
||||
#define VI_V_SYNC_REG (VI_BASE_REG + 0x18)
|
||||
|
||||
// VI horizontal sync (R/W): [20:16] a 5-bit leap pattern used for PAL only (h_sync_period)
|
||||
// [11: 0] total duration of a line in 1/4 pixel
|
||||
/* VI horizontal sync (R/W): [20:16] a 5-bit leap pattern used for PAL only (h_sync_period) */
|
||||
/* [11: 0] total duration of a line in 1/4 pixel */
|
||||
#define VI_H_SYNC_REG (VI_BASE_REG + 0x1C)
|
||||
|
||||
// VI horizontal sync leap (R/W): [27:16] identical to h_sync_period
|
||||
// [11: 0] identical to h_sync_period
|
||||
/* VI horizontal sync leap (R/W): [27:16] identical to h_sync_period */
|
||||
/* [11: 0] identical to h_sync_period */
|
||||
#define VI_LEAP_REG (VI_BASE_REG + 0x20)
|
||||
#define VI_H_SYNC_LEAP_REG VI_LEAP_REG
|
||||
|
||||
// VI horizontal video (R/W): [25:16] start of active video in screen pixels
|
||||
// [ 9: 0] end of active video in screen pixels
|
||||
/* VI horizontal video (R/W): [25:16] start of active video in screen pixels */
|
||||
/* [ 9: 0] end of active video in screen pixels */
|
||||
#define VI_H_START_REG (VI_BASE_REG + 0x24)
|
||||
#define VI_H_VIDEO_REG VI_H_START_REG
|
||||
|
||||
// VI vertical video (R/W): [25:16] start of active video in screen half-lines
|
||||
// [ 9: 0] end of active video in screen half-lines
|
||||
/* VI vertical video (R/W): [25:16] start of active video in screen half-lines */
|
||||
/* [ 9: 0] end of active video in screen half-lines */
|
||||
#define VI_V_START_REG (VI_BASE_REG + 0x28)
|
||||
#define VI_V_VIDEO_REG VI_V_START_REG
|
||||
|
||||
// VI vertical burst (R/W): [25:16] start of color burst enable in half-lines
|
||||
// [ 9: 0] end of color burst enable in half-lines
|
||||
/* VI vertical burst (R/W): [25:16] start of color burst enable in half-lines */
|
||||
/* [ 9: 0] end of color burst enable in half-lines */
|
||||
#define VI_V_BURST_REG (VI_BASE_REG + 0x2C)
|
||||
|
||||
// VI x-scale (R/W): [27:16] horizontal subpixel offset (2.10 format)
|
||||
// [11: 0] 1/horizontal scale up factor (2.10 format)
|
||||
/* VI x-scale (R/W): [27:16] horizontal subpixel offset (2.10 format) */
|
||||
/* [11: 0] 1/horizontal scale up factor (2.10 format) */
|
||||
#define VI_X_SCALE_REG (VI_BASE_REG + 0x30)
|
||||
|
||||
// VI y-scale (R/W): [27:16] vertical subpixel offset (2.10 format)
|
||||
// [11: 0] 1/vertical scale up factor (2.10 format)
|
||||
/* VI y-scale (R/W): [27:16] vertical subpixel offset (2.10 format) */
|
||||
/* [11: 0] 1/vertical scale up factor (2.10 format) */
|
||||
#define VI_Y_SCALE_REG (VI_BASE_REG + 0x34)
|
||||
|
||||
/*
|
||||
* VI_CONTROL_REG: read bits
|
||||
*/
|
||||
#define VI_CTRL_TYPE_16 0x00002 // [1:0] pixel size: 16 bit
|
||||
#define VI_CTRL_TYPE_32 0x00003 // [1:0] pixel size: 32 bit
|
||||
#define VI_CTRL_GAMMA_DITHER_ON 0x00004 // 2: default = on
|
||||
#define VI_CTRL_GAMMA_ON 0x00008 // 3: default = on
|
||||
#define VI_CTRL_DIVOT_ON 0x00010 // 4: default = on
|
||||
#define VI_CTRL_SERRATE_ON 0x00040 // 6: on if interlaced
|
||||
#define VI_CTRL_ANTIALIAS_MASK 0x00300 // [9:8] anti-alias mode
|
||||
#define VI_CTRL_ANTIALIAS_MODE_0 0x00000 // Bit [9:8] anti-alias mode: AA enabled, resampling enabled, always fetch extra lines
|
||||
#define VI_CTRL_ANTIALIAS_MODE_1 0x00100 // Bit [9:8] anti-alias mode: AA enabled, resampling enabled, fetch extra lines as-needed
|
||||
#define VI_CTRL_ANTIALIAS_MODE_2 0x00200 // Bit [9:8] anti-alias mode: AA disabled, resampling enabled, operate as if everything is covered
|
||||
#define VI_CTRL_ANTIALIAS_MODE_3 0x00300 // Bit [9:8] anti-alias mode: AA disabled, resampling disabled, replicate pixels
|
||||
#define VI_CTRL_PIXEL_ADV_MASK 0x0F000 // [15:12] pixel advance mode
|
||||
#define VI_CTRL_PIXEL_ADV_3 0x03000 // Bit [15:12] pixel advance mode: Always 3 on N64
|
||||
#define VI_CTRL_DITHER_FILTER_ON 0x10000 // 16: dither-filter mode
|
||||
#define VI_CTRL_TYPE_16 0x00002 /* [1:0] pixel size: 16 bit */
|
||||
#define VI_CTRL_TYPE_32 0x00003 /* [1:0] pixel size: 32 bit */
|
||||
#define VI_CTRL_GAMMA_DITHER_ON 0x00004 /* 2: default = on */
|
||||
#define VI_CTRL_GAMMA_ON 0x00008 /* 3: default = on */
|
||||
#define VI_CTRL_DIVOT_ON 0x00010 /* 4: default = on */
|
||||
#define VI_CTRL_SERRATE_ON 0x00040 /* 6: on if interlaced */
|
||||
#define VI_CTRL_ANTIALIAS_MASK 0x00300 /* [9:8] anti-alias mode */
|
||||
#define VI_CTRL_ANTIALIAS_MODE_0 0x00000 /* Bit [9:8] anti-alias mode: AA enabled, resampling enabled, always fetch extra lines */
|
||||
#define VI_CTRL_ANTIALIAS_MODE_1 0x00100 /* Bit [9:8] anti-alias mode: AA enabled, resampling enabled, fetch extra lines as-needed */
|
||||
#define VI_CTRL_ANTIALIAS_MODE_2 0x00200 /* Bit [9:8] anti-alias mode: AA disabled, resampling enabled, operate as if everything is covered */
|
||||
#define VI_CTRL_ANTIALIAS_MODE_3 0x00300 /* Bit [9:8] anti-alias mode: AA disabled, resampling disabled, replicate pixels */
|
||||
#define VI_CTRL_PIXEL_ADV_MASK 0x0F000 /* [15:12] pixel advance mode */
|
||||
#define VI_CTRL_PIXEL_ADV(n) (((n) << 12) & VI_CTRL_PIXEL_ADV_MASK) /* Bit [15:12] pixel advance mode: Always 3 on N64 */
|
||||
#define VI_CTRL_DITHER_FILTER_ON 0x10000 /* 16: dither-filter mode */
|
||||
|
||||
/*
|
||||
* Possible video clocks (NTSC or PAL)
|
||||
*/
|
||||
#define VI_NTSC_CLOCK 48681812 // Hz = 48.681812 MHz
|
||||
#define VI_PAL_CLOCK 49656530 // Hz = 49.656530 MHz
|
||||
#define VI_MPAL_CLOCK 48628316 // Hz = 48.628316 MHz
|
||||
#define VI_NTSC_CLOCK 48681812 /* Hz = 48.681812 MHz */
|
||||
#define VI_PAL_CLOCK 49656530 /* Hz = 49.656530 MHz */
|
||||
#define VI_MPAL_CLOCK 48628316 /* Hz = 48.628316 MHz */
|
||||
|
||||
|
||||
/**
|
||||
@@ -549,25 +549,25 @@
|
||||
*/
|
||||
#define AI_BASE_REG 0x04500000
|
||||
|
||||
// AI DRAM address (W): [23:0] starting RDRAM address (8B-aligned)
|
||||
/* AI DRAM address (W): [23:0] starting RDRAM address (8B-aligned) */
|
||||
#define AI_DRAM_ADDR_REG (AI_BASE_REG + 0x00)
|
||||
|
||||
// AI length (R/W): [14:0] transfer length (v1.0) - Bottom 3 bits are ignored
|
||||
// [17:0] transfer length (v2.0) - Bottom 3 bits are ignored
|
||||
/* AI length (R/W): [14:0] transfer length (v1.0) - Bottom 3 bits are ignored */
|
||||
/* [17:0] transfer length (v2.0) - Bottom 3 bits are ignored */
|
||||
#define AI_LEN_REG (AI_BASE_REG + 0x04)
|
||||
|
||||
// AI control (W): [0] DMA enable - if LSB == 1, DMA is enabled
|
||||
/* AI control (W): [0] DMA enable - if LSB == 1, DMA is enabled */
|
||||
#define AI_CONTROL_REG (AI_BASE_REG + 0x08)
|
||||
|
||||
/*
|
||||
* AI_CONTROL_REG: write bits
|
||||
*/
|
||||
#define AI_CONTROL_DMA_ON 1 // LSB = 1: DMA enable
|
||||
#define AI_CONTROL_DMA_OFF 0 // LSB = 1: DMA enable
|
||||
#define AI_CONTROL_DMA_ON 1 /* LSB = 1: DMA enable */
|
||||
#define AI_CONTROL_DMA_OFF 0 /* LSB = 1: DMA enable */
|
||||
|
||||
// AI status (R): [31]/[0] ai_full (addr & len buffer full), [30] ai_busy
|
||||
// Note that a 1->0 transition in ai_full will set interrupt
|
||||
// (W): clear audio interrupt
|
||||
/* AI status (R): [31]/[0] ai_full (addr & len buffer full), [30] ai_busy */
|
||||
/* Note that a 1->0 transition in ai_full will set interrupt */
|
||||
/* (W): clear audio interrupt */
|
||||
#define AI_STATUS_REG (AI_BASE_REG + 0x0C)
|
||||
|
||||
/*
|
||||
@@ -576,23 +576,23 @@
|
||||
#define AI_STATUS_FIFO_FULL (1 << 31)
|
||||
#define AI_STATUS_DMA_BUSY (1 << 30)
|
||||
|
||||
// AI DAC sample period register (W): [13:0] dac rate
|
||||
// - vid_clock/(dperiod + 1) is the DAC sample rate
|
||||
// - (dperiod + 1) >= 66 * (aclockhp + 1) must be true
|
||||
/* AI DAC sample period register (W): [13:0] dac rate */
|
||||
/* - vid_clock/(dperiod + 1) is the DAC sample rate */
|
||||
/* - (dperiod + 1) >= 66 * (aclockhp + 1) must be true */
|
||||
#define AI_DACRATE_REG (AI_BASE_REG + 0x10)
|
||||
|
||||
// DAC rate = video clock / audio frequency
|
||||
// - DAC rate >= (66 * Bit rate) must be true
|
||||
#define AI_MAX_DAC_RATE 16384 // 14-bit+1
|
||||
/* DAC rate = video clock / audio frequency */
|
||||
/* - DAC rate >= (66 * Bit rate) must be true */
|
||||
#define AI_MAX_DAC_RATE 16384 /* 14-bit+1 */
|
||||
#define AI_MIN_DAC_RATE 132
|
||||
|
||||
// AI bit rate (W): [3:0] bit rate (abus clock half period register - aclockhp)
|
||||
// - vid_clock/(2 * (aclockhp + 1)) is the DAC clock rate
|
||||
// - The abus clock stops if aclockhp is zero
|
||||
/* AI bit rate (W): [3:0] bit rate (abus clock half period register - aclockhp) */
|
||||
/* - vid_clock/(2 * (aclockhp + 1)) is the DAC clock rate */
|
||||
/* - The abus clock stops if aclockhp is zero */
|
||||
#define AI_BITRATE_REG (AI_BASE_REG + 0x14)
|
||||
|
||||
// Bit rate <= (DAC rate / 66)
|
||||
#define AI_MAX_BIT_RATE 16 // 4-bit+1
|
||||
/* Bit rate <= (DAC rate / 66) */
|
||||
#define AI_MAX_BIT_RATE 16 /* 4-bit+1 */
|
||||
#define AI_MIN_BIT_RATE 2
|
||||
|
||||
/*
|
||||
@@ -600,14 +600,14 @@
|
||||
* max frequency = (video clock / min dac rate)
|
||||
* min frequency = (video clock / max dac rate)
|
||||
*/
|
||||
#define AI_NTSC_MAX_FREQ 368000 // 368 KHz
|
||||
#define AI_NTSC_MIN_FREQ 3000 // 3 KHz ~ 2971 Hz
|
||||
#define AI_NTSC_MAX_FREQ 368000 /* 368 KHz */
|
||||
#define AI_NTSC_MIN_FREQ 3000 /* 3 KHz ~ 2971 Hz */
|
||||
|
||||
#define AI_PAL_MAX_FREQ 376000 // 376 KHz
|
||||
#define AI_PAL_MIN_FREQ 3050 // 3 KHz ~ 3031 Hz
|
||||
#define AI_PAL_MAX_FREQ 376000 /* 376 KHz */
|
||||
#define AI_PAL_MIN_FREQ 3050 /* 3 KHz ~ 3031 Hz */
|
||||
|
||||
#define AI_MPAL_MAX_FREQ 368000 // 368 KHz
|
||||
#define AI_MPAL_MIN_FREQ 3000 // 3 KHz ~ 2968 Hz
|
||||
#define AI_MPAL_MAX_FREQ 368000 /* 368 KHz */
|
||||
#define AI_MPAL_MIN_FREQ 3000 /* 3 KHz ~ 2968 Hz */
|
||||
|
||||
|
||||
/**
|
||||
@@ -615,44 +615,44 @@
|
||||
*/
|
||||
#define PI_BASE_REG 0x04600000
|
||||
|
||||
// PI DRAM address (R/W): [23:0] starting RDRAM address
|
||||
/* PI DRAM address (R/W): [23:0] starting RDRAM address */
|
||||
#define PI_DRAM_ADDR_REG (PI_BASE_REG + 0x00)
|
||||
|
||||
// PI pbus (cartridge) address (R/W): [31:0] starting AD16 address
|
||||
/* PI pbus (cartridge) address (R/W): [31:0] starting AD16 address */
|
||||
#define PI_CART_ADDR_REG (PI_BASE_REG + 0x04)
|
||||
|
||||
// PI read length (R/W): [23:0] read data length
|
||||
/* PI read length (R/W): [23:0] read data length */
|
||||
#define PI_RD_LEN_REG (PI_BASE_REG + 0x08)
|
||||
|
||||
// PI write length (R/W): [23:0] write data length
|
||||
/* PI write length (R/W): [23:0] write data length */
|
||||
#define PI_WR_LEN_REG (PI_BASE_REG + 0x0C)
|
||||
|
||||
// PI status (R): [3] interrupt flag, [2] error, [1] IO busy, [0] DMA busy
|
||||
// (W): [1] clear intr, [0] reset controller (and abort current op)
|
||||
/* PI status (R): [3] interrupt flag, [2] error, [1] IO busy, [0] DMA busy */
|
||||
/* (W): [1] clear intr, [0] reset controller (and abort current op) */
|
||||
#define PI_STATUS_REG (PI_BASE_REG + 0x10)
|
||||
|
||||
// PI dom1 latency (R/W): [7:0] domain 1 device latency
|
||||
/* PI dom1 latency (R/W): [7:0] domain 1 device latency */
|
||||
#define PI_BSD_DOM1_LAT_REG (PI_BASE_REG + 0x14)
|
||||
|
||||
// PI dom1 pulse width (R/W): [7:0] domain 1 device R/W strobe pulse width
|
||||
/* PI dom1 pulse width (R/W): [7:0] domain 1 device R/W strobe pulse width */
|
||||
#define PI_BSD_DOM1_PWD_REG (PI_BASE_REG + 0x18)
|
||||
|
||||
// PI dom1 page size (R/W): [3:0] domain 1 device page size
|
||||
/* PI dom1 page size (R/W): [3:0] domain 1 device page size */
|
||||
#define PI_BSD_DOM1_PGS_REG (PI_BASE_REG + 0x1C)
|
||||
|
||||
// PI dom1 release (R/W): [1:0] domain 1 device R/W release duration
|
||||
/* PI dom1 release (R/W): [1:0] domain 1 device R/W release duration */
|
||||
#define PI_BSD_DOM1_RLS_REG (PI_BASE_REG + 0x20)
|
||||
|
||||
// PI dom2 latency (R/W): [7:0] domain 2 device latency
|
||||
/* PI dom2 latency (R/W): [7:0] domain 2 device latency */
|
||||
#define PI_BSD_DOM2_LAT_REG (PI_BASE_REG + 0x24)
|
||||
|
||||
// PI dom2 pulse width (R/W): [7:0] domain 2 device R/W strobe pulse width
|
||||
/* PI dom2 pulse width (R/W): [7:0] domain 2 device R/W strobe pulse width */
|
||||
#define PI_BSD_DOM2_PWD_REG (PI_BASE_REG + 0x28)
|
||||
|
||||
// PI dom2 page size (R/W): [3:0] domain 2 device page size
|
||||
/* PI dom2 page size (R/W): [3:0] domain 2 device page size */
|
||||
#define PI_BSD_DOM2_PGS_REG (PI_BASE_REG + 0x2C)
|
||||
|
||||
// PI dom2 release (R/W): [1:0] domain 2 device R/W release duration
|
||||
/* PI dom2 release (R/W): [1:0] domain 2 device R/W release duration */
|
||||
#define PI_BSD_DOM2_RLS_REG (PI_BASE_REG + 0x30)
|
||||
|
||||
#define PI_DOMAIN1_REG PI_BSD_DOM1_LAT_REG
|
||||
@@ -719,30 +719,30 @@
|
||||
*/
|
||||
#define RI_BASE_REG 0x04700000
|
||||
|
||||
// RI mode (R/W): [3] stop R active, [2] stop T active, [1:0] operating mode
|
||||
/* RI mode (R/W): [3] stop R active, [2] stop T active, [1:0] operating mode */
|
||||
#define RI_MODE_REG (RI_BASE_REG + 0x00)
|
||||
|
||||
// RI config (R/W): [6] current control enable, [5:0] current control input
|
||||
/* RI config (R/W): [6] current control enable, [5:0] current control input */
|
||||
#define RI_CONFIG_REG (RI_BASE_REG + 0x04)
|
||||
|
||||
// RI current load (W): [] any write updates current control register
|
||||
/* RI current load (W): [] any write updates current control register */
|
||||
#define RI_CURRENT_LOAD_REG (RI_BASE_REG + 0x08)
|
||||
|
||||
// RI select (R/W): [3:2] receive select, [1:0] transmit select
|
||||
/* RI select (R/W): [3:2] receive select, [1:0] transmit select */
|
||||
#define RI_SELECT_REG (RI_BASE_REG + 0x0C)
|
||||
|
||||
// RI refresh (R/W): [16] refresh bank, [17] refresh enable, [18] refresh optimize
|
||||
// [7:0] clean refresh delay, [15:8] dirty refresh dela
|
||||
/* RI refresh (R/W): [16] refresh bank, [17] refresh enable, [18] refresh optimize */
|
||||
/* [7:0] clean refresh delay, [15:8] dirty refresh dela */
|
||||
#define RI_REFRESH_REG (RI_BASE_REG + 0x10)
|
||||
#define RI_COUNT_REG RI_REFRESH_REG
|
||||
|
||||
// RI latency (R/W): [3:0] DMA latency/overlap
|
||||
/* RI latency (R/W): [3:0] DMA latency/overlap */
|
||||
#define RI_LATENCY_REG (RI_BASE_REG + 0x14)
|
||||
|
||||
// RI error (R): [1] ack error, [0] nack error
|
||||
/* RI error (R): [1] ack error, [0] nack error */
|
||||
#define RI_RERROR_REG (RI_BASE_REG + 0x18)
|
||||
|
||||
// RI error (W): [] any write clears all error bits
|
||||
/* RI error (W): [] any write clears all error bits */
|
||||
#define RI_WERROR_REG (RI_BASE_REG + 0x1C)
|
||||
|
||||
|
||||
@@ -751,27 +751,27 @@
|
||||
*/
|
||||
#define SI_BASE_REG 0x04800000
|
||||
|
||||
// SI DRAM address (R/W): [23:0] starting RDRAM address
|
||||
/* SI DRAM address (R/W): [23:0] starting RDRAM address */
|
||||
#define SI_DRAM_ADDR_REG (SI_BASE_REG + 0x00)
|
||||
|
||||
// SI address read 64B (W): [] write begins a 64B DMA write PIF RAM -> RDRAM
|
||||
/* SI address read 64B (W): [] write begins a 64B DMA write PIF RAM -> RDRAM */
|
||||
#define SI_PIF_ADDR_RD64B_REG (SI_BASE_REG + 0x04)
|
||||
|
||||
// Address SI_BASE_REG + (0x08, 0x0C, 0x14) are reserved
|
||||
/* Address SI_BASE_REG + (0x08, 0x0C, 0x14) are reserved */
|
||||
|
||||
// SI address write 64B (W): [] write begins a 64B DMA read RDRAM -> PIF RAM */
|
||||
/* SI address write 64B (W): [] write begins a 64B DMA read RDRAM -> PIF RAM */
|
||||
#define SI_PIF_ADDR_WR64B_REG (SI_BASE_REG + 0x10)
|
||||
|
||||
// SI status (R/W): [] any write clears interrupt
|
||||
/* SI status (R/W): [] any write clears interrupt */
|
||||
#define SI_STATUS_REG (SI_BASE_REG + 0x18)
|
||||
|
||||
/*
|
||||
* SI_STATUS_REG: read bits
|
||||
*/
|
||||
#define SI_STATUS_DMA_BUSY (1 << 0) // DMA in progress
|
||||
#define SI_STATUS_RD_BUSY (1 << 1) // IO access in progress
|
||||
#define SI_STATUS_DMA_ERROR (1 << 3) // Overlapping DMA requests
|
||||
#define SI_STATUS_INTERRUPT (1 << 12) // Interrupt is set
|
||||
#define SI_STATUS_DMA_BUSY (1 << 0) /* DMA in progress */
|
||||
#define SI_STATUS_RD_BUSY (1 << 1) /* IO access in progress */
|
||||
#define SI_STATUS_DMA_ERROR (1 << 3) /* Overlapping DMA requests */
|
||||
#define SI_STATUS_INTERRUPT (1 << 12) /* Interrupt is set */
|
||||
|
||||
|
||||
/**
|
||||
@@ -780,13 +780,13 @@
|
||||
|
||||
#define GIO_BASE_REG 0x18000000
|
||||
|
||||
// Game to Host Interrupt
|
||||
/* Game to Host Interrupt */
|
||||
#define GIO_GIO_INTR_REG (GIO_BASE_REG+0x000)
|
||||
|
||||
// Game to Host SYNC
|
||||
/* Game to Host SYNC */
|
||||
#define GIO_GIO_SYNC_REG (GIO_BASE_REG+0x400)
|
||||
|
||||
// Host to Game Interrupt
|
||||
/* Host to Game Interrupt */
|
||||
#define GIO_CART_INTR_REG (GIO_BASE_REG+0x800)
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,164 @@
|
||||
#ifndef REGDEF_H
|
||||
#define REGDEF_H
|
||||
|
||||
#ifdef __GNUC__
|
||||
#define _MIPS_SIM_ABI32 _ABIO32
|
||||
#define _MIPS_SIM_NABI32 _ABIN32
|
||||
#define _MIPS_SIM_ABI64 _ABI64
|
||||
#endif
|
||||
|
||||
#if (_MIPS_SIM == _MIPS_SIM_ABI32)
|
||||
#define zero $0
|
||||
#define AT $at
|
||||
#define v0 $2
|
||||
#define v1 $3
|
||||
#define a0 $4
|
||||
#define a1 $5
|
||||
#define a2 $6
|
||||
#define a3 $7
|
||||
#define t0 $8
|
||||
#define t1 $9
|
||||
#define t2 $10
|
||||
#define t3 $11
|
||||
#define t4 $12
|
||||
#define ta0 $12
|
||||
#define t5 $13
|
||||
#define ta1 $13
|
||||
#define t6 $14
|
||||
#define ta2 $14
|
||||
#define t7 $15
|
||||
#define ta3 $15
|
||||
#define s0 $16
|
||||
#define s1 $17
|
||||
#define s2 $18
|
||||
#define s3 $19
|
||||
#define s4 $20
|
||||
#define s5 $21
|
||||
#define s6 $22
|
||||
#define s7 $23
|
||||
#define t8 $24
|
||||
#define t9 $25
|
||||
#define jp $25
|
||||
#define k0 $26
|
||||
#define k1 $27
|
||||
#define gp $28
|
||||
#define sp $29
|
||||
#define fp $30
|
||||
#define s8 $30
|
||||
#define ra $31
|
||||
#endif
|
||||
|
||||
#if (_MIPS_SIM == _MIPS_SIM_ABI64)
|
||||
#define zero $0
|
||||
#define AT $at
|
||||
#define v0 $2
|
||||
#define v1 $3
|
||||
#define a0 $4
|
||||
#define a1 $5
|
||||
#define a2 $6
|
||||
#define a3 $7
|
||||
#define a4 $8
|
||||
#define ta0 $8
|
||||
#define a5 $9
|
||||
#define ta1 $9
|
||||
#define a6 $10
|
||||
#define ta2 $10
|
||||
#define a7 $11
|
||||
#define ta3 $11
|
||||
#define t0 $12
|
||||
#define t1 $13
|
||||
#define t2 $14
|
||||
#define t3 $15
|
||||
#define s0 $16
|
||||
#define s1 $17
|
||||
#define s2 $18
|
||||
#define s3 $19
|
||||
#define s4 $20
|
||||
#define s5 $21
|
||||
#define s6 $22
|
||||
#define s7 $23
|
||||
#define t8 $24
|
||||
#define t9 $25
|
||||
#define jp $25
|
||||
#define k0 $26
|
||||
#define k1 $27
|
||||
#define gp $28
|
||||
#define sp $29
|
||||
#define fp $30
|
||||
#define s8 $30
|
||||
#define ra $31
|
||||
#endif
|
||||
|
||||
#if (_MIPS_SIM == _MIPS_SIM_ABI32)
|
||||
#define fv0 $f0
|
||||
#define fv0f $f1
|
||||
#define fv1 $f2
|
||||
#define fv1f $f3
|
||||
#define fa0 $f12
|
||||
#define fa0f $f13
|
||||
#define fa1 $f14
|
||||
#define fa1f $f15
|
||||
#define ft0 $f4
|
||||
#define ft0f $f5
|
||||
#define ft1 $f6
|
||||
#define ft1f $f7
|
||||
#define ft2 $f8
|
||||
#define ft2f $f9
|
||||
#define ft3 $f10
|
||||
#define ft3f $f11
|
||||
#define ft4 $f16
|
||||
#define ft4f $f17
|
||||
#define ft5 $f18
|
||||
#define ft5f $f19
|
||||
#define fs0 $f20
|
||||
#define fs0f $f21
|
||||
#define fs1 $f22
|
||||
#define fs1f $f23
|
||||
#define fs2 $f24
|
||||
#define fs2f $f25
|
||||
#define fs3 $f26
|
||||
#define fs3f $f27
|
||||
#define fs4 $f28
|
||||
#define fs4f $f29
|
||||
#define fs5 $f30
|
||||
#define fs5f $f31
|
||||
#endif
|
||||
|
||||
#if (_MIPS_SIM == _MIPS_SIM_ABI64)
|
||||
#define fv0 $f0
|
||||
#define fv1 $f2
|
||||
#define fa0 $f12
|
||||
#define fa1 $f13
|
||||
#define fa2 $f14
|
||||
#define fa3 $f15
|
||||
#define fa4 $f16
|
||||
#define fa5 $f17
|
||||
#define fa6 $f18
|
||||
#define fa7 $f19
|
||||
#define ft0 $f4
|
||||
#define ft1 $f5
|
||||
#define ft2 $f6
|
||||
#define ft3 $f7
|
||||
#define ft4 $f8
|
||||
#define ft5 $f9
|
||||
#define ft6 $f10
|
||||
#define ft7 $f11
|
||||
#define ft8 $f20
|
||||
#define ft9 $f21
|
||||
#define ft10 $f22
|
||||
#define ft11 $f23
|
||||
#define ft12 $f1
|
||||
#define ft13 $f3
|
||||
#define fs0 $f24
|
||||
#define fs1 $f25
|
||||
#define fs2 $f26
|
||||
#define fs3 $f27
|
||||
#define fs4 $f28
|
||||
#define fs5 $f29
|
||||
#define fs6 $f30
|
||||
#define fs7 $f31
|
||||
#endif
|
||||
|
||||
#define fcr31 $31
|
||||
|
||||
#endif
|
||||
@@ -73,7 +73,7 @@ typedef struct __OSThreadTail {
|
||||
|
||||
#else
|
||||
|
||||
// OSThread struct member offsets
|
||||
/* OSThread struct member offsets */
|
||||
|
||||
#define THREAD_NEXT 0x00
|
||||
#define THREAD_PRI 0x04
|
||||
|
||||
Reference in New Issue
Block a user