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libultra files and directories restructure (#1038)

Browse Source 
* Restructure files, begin header restructure

* Format

* us2dex

* Fix parallel spelling

Co-authored-by: JoshDuMan <40190173+JoshDuMan@users.noreply.github.com>

* Use OS_K0_TO_PHYSICAL in place of VIRTUAL_TO_PHYSICAL in osAiSetNextBuffer

* Uppercase hex, exception vector address defines

* Interrupt flags 1

Co-authored-by: Dragorn421 <Dragorn421@users.noreply.github.com>

* Interrupt flags 2

Co-authored-by: Dragorn421 <Dragorn421@users.noreply.github.com>

Co-authored-by: JoshDuMan <40190173+JoshDuMan@users.noreply.github.com>
Co-authored-by: Dragorn421 <Dragorn421@users.noreply.github.com>
This commit is contained in:
Tharo
2021-12-01 00:08:57 +00:00
committed by GitHub
parent eabc918817
commit f1d183d6fe
164 changed files with 1171 additions and 738 deletions
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include/functions.h
+6 -15
View File
@@ -66,7 +66,6 @@ void LogUtils_CheckValidPointer(const char* exp, void* ptr, const char* file, s3
void LogUtils_LogThreadId(const char* name, s32 line);
void LogUtils_HungupThread(const char* name, s32 line);
void LogUtils_ResetHungup(void);
void* proutSprintf(void* dst, const char* fmt, u32 size);
s32 vsprintf(char* dst, const char* fmt, va_list args);
s32 sprintf(char* dst, const char* fmt, ...);
void __osPiCreateAccessQueue(void);
@@ -76,7 +75,6 @@ s32 osSendMesg(OSMesgQueue* mq, OSMesg mesg, s32 flag);
void osStopThread(OSThread* thread);
void osViExtendVStart(u32 arg0);
s32 osRecvMesg(OSMesgQueue* mq, OSMesg* msg, s32 flag);
void __createSpeedParam(void);
void __osInitialize_common(void);
void __osInitialize_autodetect(void);
void __osExceptionPreamble();
@@ -100,9 +98,8 @@ void __osDevMgrMain(void* arg);
s32 __osPiRawStartDma(s32 dir, u32 cartAddr, void* dramAddr, size_t size);
u32 osVirtualToPhysical(void* vaddr);
void osViBlack(u8 active);
s32 __osSiRawReadIo(void* a0, u32* a1);
s32 __osSiRawReadIo(void* devAddr, u32* dst);
OSId osGetThreadId(OSThread* thread);
OSIntMask osSetIntMask(OSIntMask);
void osViSetMode(OSViMode* mode);
u32 __osProbeTLB(void*);
u32 osGetMemSize(void);
@@ -130,10 +127,10 @@ void __osTimerInterrupt(void);
void __osSetTimerIntr(OSTime time);
OSTime __osInsertTimer(OSTimer* timer);
u32 osGetCount(void);
void __osSetGlobalIntMask(u32 mask);
void __osSetGlobalIntMask(OSHWIntr mask);
void __osSetCompare(u32);
void* bcopy(void* __src, void* __dest, u32 __n);
void __osResetGlobalIntMask(u32 mask);
void __osResetGlobalIntMask(OSHWIntr mask);
s32 __osDisableInt(void);
void __osRestoreInt(s32);
void __osViInit(void);
@@ -153,15 +150,12 @@ void _Litob(_Pft* args, u8 type);
ldiv_t ldiv(s32 num, s32 denom);
lldiv_t lldiv(s64 num, s64 denom);
void _Ldtob(_Pft* args, u8 type);
s32 __osSiRawWriteIo(void* a0, u32 a1);
s32 __osSiRawWriteIo(void* devAddr, u32 val);
void osCreateViManager(OSPri pri);
void viMgrMain(void* vargs);
OSViContext* __osViGetCurrentContext(void);
void osStartThread(OSThread* thread);
void osViSetYScale(f32 scale);
void osViSetXScale(f32 value);
void __osSetHWIntrRoutine(OSHWIntr interrupt, s32 (*handler)(void), void* sp);
void __osGetHWIntrRoutine(OSHWIntr interrupt, s32 (**handlerOut)(void), void** spOut);
void __osSetWatchLo(u32);
EnItem00* Item_DropCollectible(GlobalContext* globalCtx, Vec3f* spawnPos, s16 params);
@@ -1956,8 +1950,8 @@ void Audio_PreNMIInternal(void);
s32 func_800E6680(void);
u32 Audio_NextRandom(void);
void Audio_InitMesgQueues(void);
void Audio_osInvalDCache(void* buf, s32 size);
void Audio_osWritebackDCache(void* mem, s32 size);
void Audio_InvalDCache(void* buf, s32 size);
void Audio_WritebackDCache(void* mem, s32 size);
s32 osAiSetNextBuffer(void*, u32);
void Audio_InitNoteSub(Note* note, NoteSubEu* sub, NoteSubAttributes* attrs);
void Audio_NoteSetResamplingRate(NoteSubEu* noteSubEu, f32 resamplingRateInput);
@@ -2265,9 +2259,6 @@ s16 sins(u16);
OSTask* _VirtualToPhysicalTask(OSTask* intp);
void osSpTaskLoad(OSTask* task);
void osSpTaskStartGo(OSTask* task);
s32 osSetRumble(OSPfs* pfs, u32 vibrate);
void osSetUpMempakWrite(s32 channel, OSPifRam* buf);
s32 osProbeRumblePak(OSMesgQueue* ctrlrqueue, OSPfs* pfs, u32 channel);
void __osSiCreateAccessQueue(void);
void __osSiGetAccess(void);
void __osSiRelAccess(void);
include/math.h → include/libc/math.h
View File
include/stdarg.h → include/libc/stdarg.h
View File
include/stdbool.h → include/libc/stdbool.h
View File
include/stddef.h → include/libc/stddef.h
View File
include/stdlib.h → include/libc/stdlib.h
View File
include/ultra64.h
+10 -6
View File
@@ -1,13 +1,16 @@
#ifndef ULTRA64_H
#define ULTRA64_H
#include "stddef.h"
#include "stdbool.h"
#include "math.h"
#include "ultra64/types.h"
#include "unk.h"
#include "ultra64/types.h"
#include "ultra64/interrupt.h"
#include "libc/stdarg.h"
#include "libc/stdbool.h"
#include "libc/stddef.h"
#include "libc/stdlib.h"
#include "libc/math.h"
#include "ultra64/exception.h"
#include "ultra64/rcp.h"
#include "ultra64/rdp.h"
#include "ultra64/rsp.h"
@@ -19,10 +22,11 @@
#include "ultra64/gu.h"
#include "ultra64/vi.h"
#include "ultra64/pi.h"
#include "ultra64/hardware.h"
#include "ultra64/controller.h"
#include "ultra64/printf.h"
#include "ultra64/mbi.h"
#include "ultra64/pfs.h"
#include "ultra64/motor.h"
#include "ultra64/r4300.h"
#endif
include/ultra64/abi.h
+300 -340
View File
@@ -2,249 +2,212 @@
#define ULTRA64_ABI_H
/* Audio commands: */
/*
#define A_SPNOOP 0
#define A_ADPCM 1
#define A_CLEARBUFF 2
#define A_ENVMIXER 3
#define A_LOADBUFF 4
#define A_RESAMPLE 5
#define A_SAVEBUFF 6
#define A_SEGMENT 7
#define A_SETBUFF 8
#define A_SETVOL 9
#define A_DMEMMOVE 10
#define A_LOADADPCM 11
#define A_MIXER 12
#define A_INTERLEAVE 13
#define A_POLEF 14
#define A_SETLOOP 15
*/
#define A_SPNOOP 0
#define A_ADPCM 1
#define A_CLEARBUFF 2
#define A_UNK3 3
#define A_ADDMIXER 4
#define A_RESAMPLE 5
#define A_RESAMPLE_ZOH 6
#define A_FILTER 7
#define A_SETBUFF 8
#define A_DUPLICATE 9
#define A_DMEMMOVE 10
#define A_LOADADPCM 11
#define A_MIXER 12
#define A_INTERLEAVE 13
#define A_HILOGAIN 14
#define A_SETLOOP 15
#define A_INTERL 17
#define A_ENVSETUP1 18
#define A_ENVMIXER 19
#define A_LOADBUFF 20
#define A_SAVEBUFF 21
#define A_ENVSETUP2 22
#define A_S8DEC 23
#define A_UNK19 25
#define A_SPNOOP 0
#define A_ADPCM 1
#define A_CLEARBUFF 2
#define A_UNK3 3
#define A_ADDMIXER 4
#define A_RESAMPLE 5
#define A_RESAMPLE_ZOH 6
#define A_FILTER 7
#define A_SETBUFF 8
#define A_DUPLICATE 9
#define A_DMEMMOVE 10
#define A_LOADADPCM 11
#define A_MIXER 12
#define A_INTERLEAVE 13
#define A_HILOGAIN 14
#define A_SETLOOP 15
#define A_INTERL 17
#define A_ENVSETUP1 18
#define A_ENVMIXER 19
#define A_LOADBUFF 20
#define A_SAVEBUFF 21
#define A_ENVSETUP2 22
#define A_S8DEC 23
#define A_UNK19 25
#define ACMD_SIZE 32
/*
* Audio flags
*/
#define A_INIT 0x01
#define A_CONTINUE 0x00
#define A_LOOP 0x02
#define A_OUT 0x02
#define A_LEFT 0x02
#define A_RIGHT 0x00
#define A_VOL 0x04
#define A_RATE 0x00
#define A_AUX 0x08
#define A_NOAUX 0x00
#define A_MAIN 0x00
#define A_MIX 0x10
#define A_INIT 0x01
#define A_CONTINUE 0x00
#define A_LOOP 0x02
#define A_OUT 0x02
#define A_LEFT 0x02
#define A_RIGHT 0x00
#define A_VOL 0x04
#define A_RATE 0x00
#define A_AUX 0x08
#define A_NOAUX 0x00
#define A_MAIN 0x00
#define A_MIX 0x10
/*
* Data Structures.
*/
typedef struct
{
unsigned int cmd : 8;
unsigned int flags : 8;
unsigned int gain : 16;
unsigned int addr;
typedef struct {
u32 cmd : 8;
u32 flags : 8;
u32 gain : 16;
u32 addr;
} Aadpcm;
typedef struct
{
unsigned int cmd : 8;
unsigned int flags : 8;
unsigned int gain : 16;
unsigned int addr;
typedef struct {
u32 cmd : 8;
u32 flags : 8;
u32 gain : 16;
u32 addr;
} Apolef;
typedef struct
{
unsigned int cmd : 8;
unsigned int flags : 8;
unsigned int pad1 : 16;
unsigned int addr;
typedef struct {
u32 cmd : 8;
u32 flags : 8;
u32 pad1 : 16;
u32 addr;
} Aenvelope;
typedef struct
{
unsigned int cmd : 8;
unsigned int pad1 : 8;
unsigned int dmem : 16;
unsigned int pad2 : 16;
unsigned int count : 16;
typedef struct {
u32 cmd : 8;
u32 pad1 : 8;
u32 dmem : 16;
u32 pad2 : 16;
u32 count : 16;
} Aclearbuff;
typedef struct
{
unsigned int cmd : 8;
unsigned int pad1 : 8;
unsigned int pad2 : 16;
unsigned int inL : 16;
unsigned int inR : 16;
typedef struct {
u32 cmd : 8;
u32 pad1 : 8;
u32 pad2 : 16;
u32 inL : 16;
u32 inR : 16;
} Ainterleave;
typedef struct
{
unsigned int cmd : 8;
unsigned int pad1 : 24;
unsigned int addr;
typedef struct {
u32 cmd : 8;
u32 pad1 : 24;
u32 addr;
} Aloadbuff;
typedef struct
{
unsigned int cmd : 8;
unsigned int flags : 8;
unsigned int pad1 : 16;
unsigned int addr;
typedef struct {
u32 cmd : 8;
u32 flags : 8;
u32 pad1 : 16;
u32 addr;
} Aenvmixer;
typedef struct
{
unsigned int cmd : 8;
unsigned int flags : 8;
unsigned int gain : 16;
unsigned int dmemi : 16;
unsigned int dmemo : 16;
typedef struct {
u32 cmd : 8;
u32 flags : 8;
u32 gain : 16;
u32 dmemi : 16;
u32 dmemo : 16;
} Amixer;
typedef struct
{
unsigned int cmd : 8;
unsigned int flags : 8;
unsigned int dmem2 : 16;
unsigned int addr;
typedef struct {
u32 cmd : 8;
u32 flags : 8;
u32 dmem2 : 16;
u32 addr;
} Apan;
typedef struct
{
unsigned int cmd : 8;
unsigned int flags : 8;
unsigned int pitch : 16;
unsigned int addr;
typedef struct {
u32 cmd : 8;
u32 flags : 8;
u32 pitch : 16;
u32 addr;
} Aresample;
typedef struct
{
unsigned int cmd : 8;
unsigned int flags : 8;
unsigned int pad1 : 16;
unsigned int addr;
typedef struct {
u32 cmd : 8;
u32 flags : 8;
u32 pad1 : 16;
u32 addr;
} Areverb;
typedef struct
{
unsigned int cmd : 8;
unsigned int pad1 : 24;
unsigned int addr;
typedef struct {
u32 cmd : 8;
u32 pad1 : 24;
u32 addr;
} Asavebuff;
typedef struct
{
unsigned int cmd : 8;
unsigned int pad1 : 24;
unsigned int pad2 : 2;
unsigned int number : 4;
unsigned int base : 24;
typedef struct {
u32 cmd : 8;
u32 pad1 : 24;
u32 pad2 : 2;
u32 number : 4;
u32 base : 24;
} Asegment;
typedef struct
{
unsigned int cmd : 8;
unsigned int flags : 8;
unsigned int dmemin : 16;
unsigned int dmemout : 16;
unsigned int count : 16;
typedef struct {
u32 cmd : 8;
u32 flags : 8;
u32 dmemin : 16;
u32 dmemout : 16;
u32 count : 16;
} Asetbuff;
typedef struct
{
unsigned int cmd : 8;
unsigned int flags : 8;
unsigned int vol : 16;
unsigned int voltgt : 16;
unsigned int volrate : 16;
typedef struct {
u32 cmd : 8;
u32 flags : 8;
u32 vol : 16;
u32 voltgt : 16;
u32 volrate : 16;
} Asetvol;
typedef struct
{
unsigned int cmd : 8;
unsigned int pad1 : 8;
unsigned int dmemin : 16;
unsigned int dmemout : 16;
unsigned int count : 16;
typedef struct {
u32 cmd : 8;
u32 pad1 : 8;
u32 dmemin : 16;
u32 dmemout : 16;
u32 count : 16;
} Admemmove;
typedef struct
{
unsigned int cmd : 8;
unsigned int pad1 : 8;
unsigned int count : 16;
unsigned int addr;
typedef struct {
u32 cmd : 8;
u32 pad1 : 8;
u32 count : 16;
u32 addr;
} Aloadadpcm;
typedef struct
{
unsigned int cmd : 8;
unsigned int pad1 : 8;
unsigned int pad2 : 16;
unsigned int addr;
typedef struct {
u32 cmd : 8;
u32 pad1 : 8;
u32 pad2 : 16;
u32 addr;
} Asetloop;
/*
* Generic Acmd Packet
*/
typedef struct
{
unsigned int w0;
unsigned int w1;
typedef struct {
u32 w0;
u32 w1;
} Awords;
typedef union {
Awords words;
Aadpcm adpcm;
Apolef polef;
Aclearbuff clearbuff;
Aenvelope envelope;
Awords words;
Aadpcm adpcm;
Apolef polef;
Aclearbuff clearbuff;
Aenvelope envelope;
Ainterleave interleave;
Aloadbuff loadbuff;
Aenvmixer envmixer;
Aresample resample;
Areverb reverb;
Asavebuff savebuff;
Asegment segment;
Asetbuff setbuff;
Asetvol setvol;
Admemmove dmemmove;
Aloadadpcm loadadpcm;
Amixer mixer;
Asetloop setloop;
Aloadbuff loadbuff;
Aenvmixer envmixer;
Aresample resample;
Areverb reverb;
Asavebuff savebuff;
Asegment segment;
Asetbuff setbuff;
Asetvol setvol;
Admemmove dmemmove;
Aloadadpcm loadadpcm;
Amixer mixer;
Asetloop setloop;
long long int force_union_align; /* dummy, force alignment */
} Acmd;
@@ -280,55 +243,55 @@ typedef short ENVMIX_STATE[40];
* Macros to assemble the audio command list
*/
#define aADPCMdec(pkt, f, s) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = _SHIFTL(A_ADPCM, 24, 8) | _SHIFTL(f, 16, 8); \
_a->words.w1 = (unsigned int)(s); \
#define aADPCMdec(pkt, f, s) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = _SHIFTL(A_ADPCM, 24, 8) | _SHIFTL(f, 16, 8); \
_a->words.w1 = (u32)(s); \
}
#define aPoleFilter(pkt, f, g, s) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (_SHIFTL(A_POLEF, 24, 8) | _SHIFTL(f, 16, 8) | \
_SHIFTL(g, 0, 16)); \
_a->words.w1 = (unsigned int)(s); \
#define aPoleFilter(pkt, f, g, s) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (_SHIFTL(A_POLEF, 24, 8) | _SHIFTL(f, 16, 8) | \
_SHIFTL(g, 0, 16)); \
_a->words.w1 = (u32)(s); \
}
#define aHiLoGain(pkt, gain, count, dmem, a4) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (_SHIFTL(A_HILOGAIN, 24, 8) | \
_SHIFTL(gain, 16, 8) | _SHIFTL(count, 0, 16)); \
_a->words.w1 = _SHIFTL(dmem, 16, 16) | _SHIFTL(a4, 0, 16); \
#define aHiLoGain(pkt, gain, count, dmem, a4) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (_SHIFTL(A_HILOGAIN, 24, 8) | \
_SHIFTL(gain, 16, 8) | _SHIFTL(count, 0, 16)); \
_a->words.w1 = _SHIFTL(dmem, 16, 16) | _SHIFTL(a4, 0, 16); \
}
#define aUnkCmd3(pkt, a1, a2, a3) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = _SHIFTL(A_UNK3, 24, 8) | _SHIFTL(a3, 0, 16); \
_a->words.w1 = _SHIFTL(a1, 16, 16) | _SHIFTL(a2, 0, 16); \
#define aUnkCmd3(pkt, a1, a2, a3) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = _SHIFTL(A_UNK3, 24, 8) | _SHIFTL(a3, 0, 16); \
_a->words.w1 = _SHIFTL(a1, 16, 16) | _SHIFTL(a2, 0, 16); \
}
#define aUnkCmd19(pkt, a1, a2, a3, a4) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (_SHIFTL(A_UNK19, 24, 8) | _SHIFTL(a1, 16, 8) | \
_SHIFTL(a2, 0, 16)); \
_a->words.w1 = _SHIFTL(a3, 16, 16) | _SHIFTL(a4, 0, 16); \
#define aUnkCmd19(pkt, a1, a2, a3, a4) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (_SHIFTL(A_UNK19, 24, 8) | _SHIFTL(a1, 16, 8) | \
_SHIFTL(a2, 0, 16)); \
_a->words.w1 = _SHIFTL(a3, 16, 16) | _SHIFTL(a4, 0, 16); \
}
#define aS8Dec(pkt, a1, a2) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = _SHIFTL(A_S8DEC, 24, 8) | _SHIFTL(a1, 16, 8); \
_a->words.w1 = (unsigned int)(a2); \
#define aS8Dec(pkt, a1, a2) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = _SHIFTL(A_S8DEC, 24, 8) | _SHIFTL(a1, 16, 8); \
_a->words.w1 = (u32)(a2); \
}
#define aClearBuffer(pkt, d, c) \
@@ -336,89 +299,88 @@ typedef short ENVMIX_STATE[40];
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = _SHIFTL(A_CLEARBUFF, 24, 8) | _SHIFTL(d, 0, 24); \
_a->words.w1 = (unsigned int)(c); \
_a->words.w1 = (u32)(c); \
}
#define aEnvMixer(pkt, dmemi, count, swapLR, x0, x1, x2, x3, m, bits) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (bits | _SHIFTL(dmemi >> 4, 16, 8) | \
_SHIFTL(count, 8, 8) | _SHIFTL(swapLR, 4, 1) | \
_SHIFTL(x0, 3, 1) | _SHIFTL(x1, 2, 1) | \
_SHIFTL(x2, 1, 1) | _SHIFTL(x3, 0, 1)); \
_a->words.w1 = (unsigned int)(m); \
#define aEnvMixer(pkt, dmemi, count, swapLR, x0, x1, x2, x3, m, bits) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (bits | _SHIFTL(dmemi >> 4, 16, 8) | \
_SHIFTL(count, 8, 8) | _SHIFTL(swapLR, 4, 1) | \
_SHIFTL(x0, 3, 1) | _SHIFTL(x1, 2, 1) | \
_SHIFTL(x2, 1, 1) | _SHIFTL(x3, 0, 1)); \
_a->words.w1 = (u32)(m); \
}
#define aInterleave(pkt, o, l, r, c) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (_SHIFTL(A_INTERLEAVE, 24, 8) | \
_SHIFTL(c >> 4, 16, 8) | _SHIFTL(o, 0, 16)); \
_a->words.w1 = _SHIFTL(l, 16, 16) | _SHIFTL(r, 0, 16); \
#define aInterleave(pkt, o, l, r, c) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (_SHIFTL(A_INTERLEAVE, 24, 8) | \
_SHIFTL(c >> 4, 16, 8) | _SHIFTL(o, 0, 16)); \
_a->words.w1 = _SHIFTL(l, 16, 16) | _SHIFTL(r, 0, 16); \
}
#define aInterl(pkt, dmemi, dmemo, count) \
{ \
Acmd *_a = (Acmd*)pkt; \
\
_a->words.w0 = (_SHIFTL(A_INTERL, 24, 8) | \
_SHIFTL(count, 0, 16)); \
_a->words.w1 = _SHIFTL(dmemi, 16, 16) | _SHIFTL(dmemo, 0, 16); \
#define aInterl(pkt, dmemi, dmemo, count) \
{ \
Acmd *_a = (Acmd*)pkt; \
\
_a->words.w0 = (_SHIFTL(A_INTERL, 24, 8) | _SHIFTL(count, 0, 16)); \
_a->words.w1 = _SHIFTL(dmemi, 16, 16) | _SHIFTL(dmemo, 0, 16); \
}
#define aLoadBuffer(pkt, s, d, c) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = _SHIFTL(A_LOADBUFF, 24, 8) | \
_SHIFTL((c) >> 4, 16, 8) | _SHIFTL(d, 0, 16); \
_a->words.w1 = (unsigned int)(s); \
#define aLoadBuffer(pkt, s, d, c) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (_SHIFTL(A_LOADBUFF, 24, 8) | \
_SHIFTL((c) >> 4, 16, 8) | _SHIFTL(d, 0, 16)); \
_a->words.w1 = (u32)(s); \
}
#define aMix(pkt, f, g, i, o) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (_SHIFTL(A_MIXER, 24, 8) | _SHIFTL(f, 16, 8) | \
_SHIFTL(g, 0, 16)); \
_a->words.w1 = _SHIFTL(i, 16, 16) | _SHIFTL(o, 0, 16); \
#define aMix(pkt, f, g, i, o) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (_SHIFTL(A_MIXER, 24, 8) | _SHIFTL(f, 16, 8) | \
_SHIFTL(g, 0, 16)); \
_a->words.w1 = _SHIFTL(i, 16, 16) | _SHIFTL(o, 0, 16); \
}
#define aPan(pkt, f, d, s) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (_SHIFTL(A_PAN, 24, 8) | _SHIFTL(f, 16, 8) | \
_SHIFTL(d, 0, 16)); \
_a->words.w1 = (unsigned int)(s); \
#define aPan(pkt, f, d, s) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (_SHIFTL(A_PAN, 24, 8) | _SHIFTL(f, 16, 8) | \
_SHIFTL(d, 0, 16)); \
_a->words.w1 = (u32)(s); \
}
#define aResample(pkt, f, p, s) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (_SHIFTL(A_RESAMPLE, 24, 8) | \
_SHIFTL(f, 16, 8) | _SHIFTL(p, 0, 16)); \
_a->words.w1 = (unsigned int)(s); \
#define aResample(pkt, f, p, s) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (_SHIFTL(A_RESAMPLE, 24, 8) | \
_SHIFTL(f, 16, 8) | _SHIFTL(p, 0, 16)); \
_a->words.w1 = (u32)(s); \
}
#define aSaveBuffer(pkt, s, d, c) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = _SHIFTL(A_SAVEBUFF, 24, 8) | \
_SHIFTL((c) >> 4, 16, 8) | _SHIFTL(s, 0, 16); \
_a->words.w1 = (unsigned int)(d); \
#define aSaveBuffer(pkt, s, d, c) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (_SHIFTL(A_SAVEBUFF, 24, 8) | \
_SHIFTL((c) >> 4, 16, 8) | _SHIFTL(s, 0, 16)); \
_a->words.w1 = (u32)(d); \
}
#define aSegment(pkt, s, b) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = _SHIFTL(A_SEGMENT, 24, 8); \
_a->words.w1 = _SHIFTL(s, 24, 8) | _SHIFTL(b, 0, 24); \
#define aSegment(pkt, s, b) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = _SHIFTL(A_SEGMENT, 24, 8); \
_a->words.w1 = _SHIFTL(s, 24, 8) | _SHIFTL(b, 0, 24); \
}
#define aSetBuffer(pkt, f, i, o, c) \
@@ -445,23 +407,23 @@ typedef short ENVMIX_STATE[40];
\
_a->words.w0 = (_SHIFTL(A_SETVOL, 24, 8) | _SHIFTL(f, 16, 16) | \
_SHIFTL(v, 0, 16)); \
_a->words.w1 = (unsigned int)(tr); \
_a->words.w1 = (u32)(tr); \
}
#define aSetLoop(pkt, a) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = _SHIFTL(A_SETLOOP, 24, 8); \
_a->words.w1 = (unsigned int)(a); \
#define aSetLoop(pkt, a) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = _SHIFTL(A_SETLOOP, 24, 8); \
_a->words.w1 = (u32)(a); \
}
#define aDMEMMove(pkt, i, o, c) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = _SHIFTL(A_DMEMMOVE, 24, 8) | _SHIFTL(i, 0, 24); \
_a->words.w1 = _SHIFTL(o, 16, 16) | _SHIFTL(c, 0, 16); \
#define aDMEMMove(pkt, i, o, c) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = _SHIFTL(A_DMEMMOVE, 24, 8) | _SHIFTL(i, 0, 24); \
_a->words.w1 = _SHIFTL(o, 16, 16) | _SHIFTL(c, 0, 16); \
}
#define aLoadADPCM(pkt, c, d) \
@@ -469,36 +431,34 @@ typedef short ENVMIX_STATE[40];
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = _SHIFTL(A_LOADADPCM, 24, 8) | _SHIFTL(c, 0, 24); \
_a->words.w1 = (unsigned int)d; \
_a->words.w1 = (u32)d; \
}
#define aEnvSetup1(pkt, a, b, c, d) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (_SHIFTL(A_ENVSETUP1, 24, 8) | \
_SHIFTL(a, 16, 8) | _SHIFTL(b, 0, 16)); \
_a->words.w1 = _SHIFTL(c, 16, 16) | _SHIFTL(d, 0, 16); \
#define aEnvSetup1(pkt, a, b, c, d) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (_SHIFTL(A_ENVSETUP1, 24, 8) | \
_SHIFTL(a, 16, 8) | _SHIFTL(b, 0, 16)); \
_a->words.w1 = _SHIFTL(c, 16, 16) | _SHIFTL(d, 0, 16); \
}
#define aEnvSetup2(pkt, volLeft, volRight) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = _SHIFTL(A_ENVSETUP2, 24, 8); \
_a->words.w1 = _SHIFTL(volLeft, 16, 16) | \
_SHIFTL(volRight, 0, 16); \
#define aEnvSetup2(pkt, volLeft, volRight) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = _SHIFTL(A_ENVSETUP2, 24, 8); \
_a->words.w1 = (_SHIFTL(volLeft, 16, 16) | \
_SHIFTL(volRight, 0, 16)); \
}
#define aFilter(pkt, f, countOrBuf, addr) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = _SHIFTL(A_FILTER, 24, 8) | _SHIFTL(f, 16, 8) | \
_SHIFTL(countOrBuf, 0, 16); \
_a->words.w1 = (unsigned int)(addr); \
_a->words.w0 = (_SHIFTL(A_FILTER, 24, 8) | _SHIFTL(f, 16, 8) | \
_SHIFTL(countOrBuf, 0, 16)); \
_a->words.w1 = (u32)(addr); \
}
#define aDuplicate(pkt, count, dmemi, dmemo, a4) \
@@ -506,26 +466,26 @@ typedef short ENVMIX_STATE[40];
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (_SHIFTL(A_DUPLICATE, 24, 8) | \
_SHIFTL(count, 16, 8) | _SHIFTL(dmemi, 0, 16)); \
_SHIFTL(count, 16, 8) | _SHIFTL(dmemi, 0, 16)); \
_a->words.w1 = _SHIFTL(dmemo, 16, 16) | _SHIFTL(a4, 0, 16); \
}
#define aAddMixer(pkt, count, dmemi, dmemo, a4) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (_SHIFTL(A_ADDMIXER, 24, 8) | \
_SHIFTL(count >> 4, 16, 8) | _SHIFTL(a4, 0, 16)); \
_a->words.w1 = _SHIFTL(dmemi, 16, 16) | _SHIFTL(dmemo, 0, 16); \
#define aAddMixer(pkt, count, dmemi, dmemo, a4) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (_SHIFTL(A_ADDMIXER, 24, 8) | \
_SHIFTL(count >> 4, 16, 8) | _SHIFTL(a4, 0, 16)); \
_a->words.w1 = _SHIFTL(dmemi, 16, 16) | _SHIFTL(dmemo, 0, 16); \
}
#define aResampleZoh(pkt, pitch, pitchAccu) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (_SHIFTL(A_RESAMPLE_ZOH, 24, 8) | \
_SHIFTL(pitch, 0, 16)); \
_a->words.w1 = _SHIFTL(pitchAccu, 0, 16); \
#define aResampleZoh(pkt, pitch, pitchAccu) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (_SHIFTL(A_RESAMPLE_ZOH, 24, 8) | \
_SHIFTL(pitch, 0, 16)); \
_a->words.w1 = _SHIFTL(pitchAccu, 0, 16); \
}
#endif /* ULTRA64_ABI_H */
include/ultra64/controller.h
+1 -2
View File
@@ -1,8 +1,7 @@
#ifndef ULTRA64_CONTROLLER_H
#define ULTRA64_CONTROLLER_H
#include "ultra64.h"
#include "ultra64/message.h"
#include "message.h"
#define SIAccessQueueSize 2
#define BLOCKSIZE 32
include/ultra64/exception.h
+45
View File
@@ -0,0 +1,45 @@
#ifndef ULTRA64_EXCEPTION_H
#define ULTRA64_EXCEPTION_H
#include "types.h"
// Interrupt masks
#define OS_IM_NONE 0x00000001
#define OS_IM_SW1 0x00000501
#define OS_IM_SW2 0x00000601
#define OS_IM_CART 0x00000C01
#define OS_IM_PRENMI 0x00001401
#define OS_IM_RDBWRITE 0x00002401
#define OS_IM_RDBREAD 0x00004401
#define OS_IM_COUNTER 0x00008401
#define OS_IM_CPU 0x0000FF01
#define OS_IM_SP 0x00010401
#define OS_IM_SI 0x00020401
#define OS_IM_AI 0x00040401
#define OS_IM_VI 0x00080401
#define OS_IM_PI 0x00100401
#define OS_IM_DP 0x00200401
#define OS_IM_ALL 0x003FFF01
#define RCP_IMASK 0x003F0000
#define RCP_IMASKSHIFT 16
typedef u32 OSIntMask;
typedef u32 OSHWIntr;
typedef struct {
/* 0x00 */ void* callback;
/* 0x04 */ void* sp;
} __osHwInt; // size = 0x08
OSIntMask osSetIntMask(OSIntMask);
void __osSetHWIntrRoutine(OSHWIntr interrupt, s32 (*callback)(void), void *sp);
void __osGetHWIntrRoutine(OSHWIntr interrupt, s32 (**callbackOut)(void), void **spOut);
void __osSetGlobalIntMask(OSHWIntr mask);
void __osResetGlobalIntMask(OSHWIntr mask);
extern __osHwInt __osHwIntTable[];
#endif
include/ultra64/gbi.h
+1 -1
View File
@@ -1,4 +1,4 @@
#include "ultra64/mbi.h"
#include "mbi.h"
#ifndef ULTRA64_GBI_H
#define ULTRA64_GBI_H
include/ultra64/hardware.h
-90
View File
@@ -1,90 +0,0 @@
#ifndef ULTRA64_HARDWARE_H
#define ULTRA64_HARDWARE_H
#define HW_REG(reg, type) *(volatile type*)((reg) | 0xa0000000)
#define AI_DRAM_ADDR_REG 0x04500000
#define AI_LEN_REG 0x04500004
#define AI_CONTROL_REG 0x04500008
#define AI_STATUS_REG 0x0450000C
#define AI_STATUS_AI_FULL (1 << 31)
#define AI_STATUS_AI_BUSY (1 << 30)
#define AI_DACRATE_REG 0x04500010
#define AI_BITRATE_REG 0x04500014
#define VI_STATUS_REG 0x04400000
#define VI_CONTROL_REG 0x04400000
#define VI_ORIGIN_REG 0x04400004
#define VI_DRAM_ADDR_REG 0x04400004
#define VI_WIDTH_REG 0x04400008
#define VI_H_WIDTH_REG 0x04400008
#define VI_INTR_REG 0x0440000C
#define VI_V_INTER_REG 0x0440000C
#define VI_CURRENT_REG 0x04400010
#define VI_V_CURRENT_LINE_REG 0x04400010
#define VI_BURST_REG 0x04400014
#define VI_TIMING_REG 0x04400014
#define VI_V_SYNC_REG 0x04400018 //VI vertical sync
#define VI_H_SYNC_REG 0x0440001C //VI horizontal sync
#define VI_LEAP_REG 0x04400020 //VI horizontal sync leap
#define VI_H_SYNC_LEAP_REG 0x04400020
#define VI_H_START_REG 0x04400024 //VI horizontal video
#define VI_H_VIDEO_REG 0x04400024
#define VI_V_START_REG 0x04400028 //VI vertical video
#define VI_V_VIDEO_REG 0x04400028
#define VI_V_BURST_REG 0x0440002C //VI vertical burst
#define VI_X_SCALE_REG 0x04400030 //VI x-scale
#define VI_Y_SCALE_REG 0x04400034 //VI y-scale
#define SP_IMEM_START 0x04001000
#define SP_DMEM_START 0x04000000
#define SP_MEM_ADDR_REG 0x04040000
#define SP_DRAM_ADDR_REG 0x04040004
#define SP_RD_LEN_REG 0x04040008
#define SP_WR_LEN_REG 0x0404000C
#define SP_STATUS_REG 0x04040010
#define SP_PC_REG 0x04080000
#define PI_DRAM_ADDR_REG 0x04600000 //PI DRAM address
#define PI_CART_ADDR_REG 0x04600004 //PI pbus (cartridge) address
#define PI_RD_LEN_REG 0x04600008 //PI read length
#define PI_WR_LEN_REG 0x0460000C //PI write length
#define PI_STATUS_REG 0x04600010 //PI status
#define PI_BSD_DOM1_LAT_REG 0x04600014 //PI dom1 latency
#define PI_DOMAIN1_REG 0x04600014
#define PI_BSD_DOM1_PWD_REG 0x04600018 //PI dom1 pulse width
#define PI_BSD_DOM1_PGS_REG 0x0460001C //PI dom1 page size
#define PI_BSD_DOM1_RLS_REG 0x04600020 //PI dom1 release
#define PI_BSD_DOM2_LAT_REG 0x04600024 //PI dom2 latency
#define PI_DOMAIN2_REG 0x04600024
#define PI_BSD_DOM2_PWD_REG 0x04600028 //PI dom2 pulse width
#define PI_BSD_DOM2_PGS_REG 0x0460002C //PI dom2 page size
#define PI_BSD_DOM2_RLS_REG 0x04600030 //PI dom2 release
#define PI_STATUS_BUSY 0x1
#define PI_STATUS_IOBUSY 0x2
#define PI_STATUS_ERROR 0x4
#define PI_STATUS_RESET_CONTROLLER 0x1
#define PI_STATUS_CLEAR_INTR 0x2
#define SI_DRAM_ADDR_REG 0x04800000
#define SI_PIF_ADDR_RD64B_REG 0x04800004
#define SI_PIF_ADDR_WR64B_REG 0x04800010
#define SI_STATUS_REG 0x04800018
#define SI_STATUS_DMA_BUSY 0x1
#define SI_STATUS_IO_READ_BUSY 0x2
#define SI_STATUS_DMA_ERROR 0x8
#define SI_STATUS_INTERRUPT (1 << 12)
#define PIF_RAM_START 0x1FC007C0
#define MI_INIT_MODE_REG 0x04300000
#define MI_MODE_REG MI_INIT_MODE_REG
#define MI_VERSION_REG 0x04300004
#define MI_INTR_REG 0x04300008
#define MI_INTR_MASK_REG 0x0430000C
#endif
include/ultra64/internal.h
+2 -6
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@@ -1,6 +1,8 @@
#ifndef ULTRA64_INTERNAL_H
#define ULTRA64_INTERNAL_H
#include "pi.h"
typedef struct {
/* 0x00 */ u32 initialized;
/* 0x04 */ OSThread* mgrThread;
@@ -11,18 +13,12 @@ typedef struct {
/* 0x18 */ s32 (*epiDmaCallback)(OSPiHandle*, s32, u32, void*, size_t);
} OSMgrArgs; // size = 0x1C
typedef struct {
/* 0x00 */ s32 (*handler)(void);
/* 0x04 */ void* sp;
} __osHwInt; // size = 0x08
typedef struct {
/* 0x00 */ OSMesgQueue* queue;
/* 0x04 */ OSMesg msg;
} __OSEventState; // size = 0x08
extern OSMgrArgs __osPiDevMgr;
extern __osHwInt __osHwIntTable[];
extern __OSEventState __osEventStateTab[];
#endif
include/ultra64/interrupt.h
-7
View File
@@ -1,7 +0,0 @@
#ifndef ULTRA64_INTERRUPT_H
#define ULTRA64_INTERRUPT_H
typedef u32 OSIntMask;
typedef u32 OSHWIntr;
#endif
include/ultra64/mbi.h
+3 -3
View File
@@ -32,11 +32,11 @@
#define G_ON (1)
#define G_OFF (0)
#include "ultra64/gbi.h"
#include "ultra64/abi.h"
#include "gbi.h"
#include "abi.h"
#define NUM_SEGMENTS (16)
#define SEGMENT_OFFSET(a) ((u32)(a) & 0x00ffffff)
#define SEGMENT_OFFSET(a) ((u32)(a) & 0x00FFFFFF)
#define SEGMENT_NUMBER(a) (((u32)(a) << 4) >> 28)
#define SEGMENT_ADDR(num, off) (((num) << 24) + (off))
include/ultra64/message.h
+1 -1
View File
@@ -1,7 +1,7 @@
#ifndef ULTRA64_MESSAGE_H
#define ULTRA64_MESSAGE_H
#include "ultra64/types.h"
#include "thread.h"
#define OS_MESG_NOBLOCK 0
#define OS_MESG_BLOCK 1
include/ultra64/motor.h
+15
View File
@@ -0,0 +1,15 @@
#ifndef ULTRA64_MOTOR_H
#define ULTRA64_MOTOR_H
#include "pfs.h"
#define MOTOR_START 1
#define MOTOR_STOP 0
#define osMotorStart(x) __osMotorAccess((x), MOTOR_START)
#define osMotorStop(x) __osMotorAccess((x), MOTOR_STOP)
s32 __osMotorAccess(OSPfs* pfs, u32 vibrate);
s32 osMotorInit(OSMesgQueue* ctrlrqueue, OSPfs* pfs, s32 channel);
#endif
include/ultra64/pfs.h
+1 -1
View File
@@ -1,7 +1,7 @@
#ifndef ULTRA64_PFS_H
#define ULTRA64_PFS_H
#include "ultra64.h"
#include "message.h"
/* File System size */
#define OS_PFS_VERSION 0x0200
include/ultra64/pi.h
+21 -1
View File
@@ -1,6 +1,8 @@
#ifndef ULTRA64_PI_H
#define ULTRA64_PI_H
#include "message.h"
typedef struct {
/* 0x00 */ u32 errStatus;
/* 0x04 */ void* dramAddr;
@@ -54,10 +56,28 @@ typedef struct {
/* 0x14 */ OSPiHandle* piHandle;
} OSIoMesg; // size = 0x18
#define OS_READ 0 // device -> RDRAM
#define OS_READ 0 // device -> RDRAM
#define OS_WRITE 1 // device <- RDRAM
#define OS_OTHERS 2 // for disk drive transfers
#define PI_DOMAIN1 0
#define PI_DOMAIN2 1
#define OS_MESG_TYPE_LOOPBACK 10
#define OS_MESG_TYPE_DMAREAD 11
#define OS_MESG_TYPE_DMAWRITE 12
#define OS_MESG_TYPE_VRETRACE 13
#define OS_MESG_TYPE_COUNTER 14
#define OS_MESG_TYPE_EDMAREAD 15
#define OS_MESG_TYPE_EDMAWRITE 16
#define OS_MESG_PRI_NORMAL 0
#define OS_MESG_PRI_HIGH 1
#define DEVICE_TYPE_CART 0 /* ROM cartridge */
#define DEVICE_TYPE_BULK 1 /* ROM bulk */
#define DEVICE_TYPE_64DD 2 /* 64 Disk Drive */
#define DEVICE_TYPE_SRAM 3 /* SRAM */
#define DEVICE_TYPE_INIT 7 /* initial value */
#endif
include/ultra64/printf.h
+2 -1
View File
@@ -1,6 +1,7 @@
#ifndef ULTRA64_PRINTF_H
#define ULTRA64_PRINTF_H
#include "stdarg.h"
#include "types.h"
typedef struct {
/* 0x0 */ union {
include/ultra64/r4300.h
+367
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@@ -0,0 +1,367 @@
#ifndef ULTRA64_R4300_H
#define ULTRA64_R4300_H
#ifdef _LANGUAGE_C
#include "types.h"
#define U32(x) ((u32)x)
#define C_REG(x) (x)
#else
#define U32(x) (x)
#define C_REG(x) $x
#endif
// Segment base addresses and sizes
#define KUBASE 0
#define KUSIZE 0x80000000
#define K0BASE 0x80000000
#define K0SIZE 0x20000000
#define K1BASE 0xA0000000
#define K1SIZE 0x20000000
#define K2BASE 0xC0000000
#define K2SIZE 0x20000000
// Exception vectors
#define SIZE_EXCVEC 0x80 // Size of an exc. vec
#define UT_VEC K0BASE // utlbmiss vector
#define R_VEC (K1BASE + 0x1FC00000) // reset vector
#define XUT_VEC (K0BASE + 0x80) // extended address tlbmiss
#define ECC_VEC (K0BASE + 0x100) // Ecc exception vector
#define E_VEC (K0BASE + 0x180) // Gen. exception vector
// Address conversion macros
#define K0_TO_K1(x) (U32(x) | 0xA0000000) // kseg0 to kseg1
#define K1_TO_K0(x) (U32(x) & 0x9FFFFFFF) // kseg1 to kseg0
#define K0_TO_PHYS(x) (U32(x) & 0x1FFFFFFF) // kseg0 to physical
#define K1_TO_PHYS(x) (U32(x) & 0x1FFFFFFF) // kseg1 to physical
#define KDM_TO_PHYS(x) (U32(x) & 0x1FFFFFFF) // direct mapped to physical
#define PHYS_TO_K0(x) (U32(x) | 0x80000000) // physical to kseg0
#define PHYS_TO_K1(x) (U32(x) | 0xA0000000) // physical to kseg1
// Address predicates
#define IS_KSEG0(x) (U32(x) >= K0BASE && U32(x) < K1BASE)
#define IS_KSEG1(x) (U32(x) >= K1BASE && U32(x) < K2BASE)
#define IS_KSEGDM(x) (U32(x) >= K0BASE && U32(x) < K2BASE)
#define IS_KSEG2(x) (U32(x) >= K2BASE && U32(x) < KPTE_SHDUBASE)
#define IS_KPTESEG(x) (U32(x) >= KPTE_SHDUBASE)
#define IS_KUSEG(x) (U32(x) < K0BASE)
// TLB size constants
#define NTLBENTRIES 31 /* entry 31 is reserved by rdb */
#define TLBHI_VPN2MASK 0xFFFFE000
#define TLBHI_VPN2SHIFT 13
#define TLBHI_PIDMASK 0xFF
#define TLBHI_PIDSHIFT 0
#define TLBHI_NPID 255 // 255 to fit in 8 bits
#define TLBLO_PFNMASK 0x3FFFFFC0
#define TLBLO_PFNSHIFT 6
#define TLBLO_CACHMASK 0x38 // cache coherency algorithm
#define TLBLO_CACHSHIFT 3
#define TLBLO_UNCACHED 0x10 // not cached
#define TLBLO_NONCOHRNT 0x18 // Cacheable non-coherent
#define TLBLO_EXLWR 0x28 // Exclusive write
#define TLBLO_D 0x4 // writeable
#define TLBLO_V 0x2 // valid bit
#define TLBLO_G 0x1 // global access bit
#define TLBINX_PROBE 0x80000000
#define TLBINX_INXMASK 0x3F
#define TLBINX_INXSHIFT 0
#define TLBRAND_RANDMASK 0x3F
#define TLBRAND_RANDSHIFT 0
#define TLBWIRED_WIREDMASK 0x3F
#define TLBCTXT_BASEMASK 0xFF800000
#define TLBCTXT_BASESHIFT 23
#define TLBCTXT_BASEBITS 9
#define TLBCTXT_VPNMASK 0x7FFFF0
#define TLBCTXT_VPNSHIFT 4
#define TLBPGMASK_4K 0x0
#define TLBPGMASK_16K 0x6000
#define TLBPGMASK_64K 0x1E000
/*
* Status register
*/
#define SR_CUMASK 0xF0000000 // coproc usable bits
#define SR_CU3 0x80000000 // Coprocessor 3 usable
#define SR_CU2 0x40000000 // Coprocessor 2 usable
#define SR_CU1 0x20000000 // Coprocessor 1 usable
#define SR_CU0 0x10000000 // Coprocessor 0 usable
#define SR_RP 0x08000000 // Reduced power (quarter speed)
#define SR_FR 0x04000000 // MIPS III FP register mode
#define SR_RE 0x02000000 // Reverse endian
#define SR_ITS 0x01000000 // Instruction trace support
#define SR_BEV 0x00400000 // Use boot exception vectors
#define SR_TS 0x00200000 // TLB shutdown
#define SR_SR 0x00100000 // Soft reset occured
#define SR_CH 0x00040000 // Cache hit for last 'cache' op
#define SR_CE 0x00020000 // Create ECC
#define SR_DE 0x00010000 // ECC of parity does not cause error
// Interrupt enable bits
// (NOTE: bits set to 1 enable the corresponding level interrupt)
#define SR_IMASK 0x0000FF00 // Interrupt mask
#define SR_IMASK8 0x00000000 // mask level 8
#define SR_IMASK7 0x00008000 // mask level 7
#define SR_IMASK6 0x0000C000 // mask level 6
#define SR_IMASK5 0x0000E000 // mask level 5
#define SR_IMASK4 0x0000F000 // mask level 4
#define SR_IMASK3 0x0000F800 // mask level 3
#define SR_IMASK2 0x0000FC00 // mask level 2
#define SR_IMASK1 0x0000FE00 // mask level 1
#define SR_IMASK0 0x0000FF00 // mask level 0
#define SR_IBIT8 0x00008000 // bit level 8
#define SR_IBIT7 0x00004000 // bit level 7
#define SR_IBIT6 0x00002000 // bit level 6
#define SR_IBIT5 0x00001000 // bit level 5
#define SR_IBIT4 0x00000800 // bit level 4
#define SR_IBIT3 0x00000400 // bit level 3
#define SR_IBIT2 0x00000200 // bit level 2
#define SR_IBIT1 0x00000100 // bit level 1
#define SR_IMASKSHIFT 8
#define SR_KX 0x00000080 // extended-addr TLB vec in kernel
#define SR_SX 0x00000040 // xtended-addr TLB vec supervisor
#define SR_UX 0x00000020 // xtended-addr TLB vec in user mode
#define SR_KSU_MASK 0x00000018 // mode mask
#define SR_KSU_USR 0x00000010 // user mode
#define SR_KSU_SUP 0x00000008 // supervisor mode
#define SR_KSU_KER 0x00000000 // kernel mode
#define SR_ERL 0x00000004 // Error level, 1=>cache error
#define SR_EXL 0x00000002 // Exception level, 1=>exception
#define SR_IE 0x00000001 // interrupt enable, 1=>enable
// Cause Register
#define CAUSE_BD 0x80000000 // Branch delay slot
#define CAUSE_CEMASK 0x30000000 // coprocessor error
#define CAUSE_CESHIFT 28
// Interrupt pending bits
#define CAUSE_IP8 0x00008000 // External level 8 pending - COMPARE
#define CAUSE_IP7 0x00004000 // External level 7 pending - INT4
#define CAUSE_IP6 0x00002000 // External level 6 pending - INT3
#define CAUSE_IP5 0x00001000 // External level 5 pending - INT2
#define CAUSE_IP4 0x00000800 // External level 4 pending - INT1
#define CAUSE_IP3 0x00000400 // External level 3 pending - INT0
#define CAUSE_SW2 0x00000200 // Software level 2 pending
#define CAUSE_SW1 0x00000100 // Software level 1 pending
#define CAUSE_IPMASK 0x0000FF00 // Pending interrupt mask
#define CAUSE_IPSHIFT 8
#define CAUSE_EXCMASK 0x0000007C // Cause code bits
#define CAUSE_EXCSHIFT 2
// Cause register exception codes
#define EXC_CODE(x) ((x) << 2)
// Hardware exception codes
#define EXC_INT EXC_CODE(0) // interrupt
#define EXC_MOD EXC_CODE(1) // TLB mod
#define EXC_RMISS EXC_CODE(2) // Read TLB Miss
#define EXC_WMISS EXC_CODE(3) // Write TLB Miss
#define EXC_RADE EXC_CODE(4) // Read Address Error
#define EXC_WADE EXC_CODE(5) // Write Address Error
#define EXC_IBE EXC_CODE(6) // Instruction Bus Error
#define EXC_DBE EXC_CODE(7) // Data Bus Error
#define EXC_SYSCALL EXC_CODE(8) // SYSCALL
#define EXC_BREAK EXC_CODE(9) // BREAKpoint
#define EXC_II EXC_CODE(10) // Illegal Instruction
#define EXC_CPU EXC_CODE(11) // CoProcessor Unusable
#define EXC_OV EXC_CODE(12) // OVerflow
#define EXC_TRAP EXC_CODE(13) // Trap exception
#define EXC_VCEI EXC_CODE(14) // Virt. Coherency on Inst. fetch
#define EXC_FPE EXC_CODE(15) // Floating Point Exception
#define EXC_WATCH EXC_CODE(23) // Watchpoint reference
#define EXC_VCED EXC_CODE(31) // Virt. Coherency on data read
// C0_PRID Defines
#define C0_IMPMASK 0xFF00
#define C0_IMPSHIFT 8
#define C0_REVMASK 0xFF
#define C0_MAJREVMASK 0xF0
#define C0_MAJREVSHIFT 4
#define C0_MINREVMASK 0xF
// Coprocessor 0 operations
#define C0_READI 0x1 // read ITLB entry addressed by C0_INDEX
#define C0_WRITEI 0x2 // write ITLB entry addressed by C0_INDEX
#define C0_WRITER 0x6 // write ITLB entry addressed by C0_RAND
#define C0_PROBE 0x8 // probe for ITLB entry addressed by TLBHI
#define C0_RFE 0x10 // restore for exception
// 'cache' instruction definitions
// Target cache
#define CACH_PI 0x0 // specifies primary inst. cache
#define CACH_PD 0x1 // primary data cache
#define CACH_SI 0x2 // secondary instruction cache
#define CACH_SD 0x3 // secondary data cache
// Cache operations
#define C_IINV 0x0 // index invalidate (inst, 2nd inst)
#define C_IWBINV 0x0 // index writeback inval (d, sd)
#define C_ILT 0x4 // index load tag (all)
#define C_IST 0x8 // index store tag (all)
#define C_CDX 0xC // create dirty exclusive (d, sd)
#define C_HINV 0x10 // hit invalidate (all)
#define C_HWBINV 0x14 // hit writeback inv. (d, sd)
#define C_FILL 0x14 // fill (i)
#define C_HWB 0x18 // hit writeback (i, d, sd)
#define C_HSV 0x1C // hit set virt. (si, sd)
// Cache size definitions
#define ICACHE_SIZE 0x4000 // 16K
#define ICACHE_LINESIZE 32 // 8 words
#define ICACHE_LINEMASK (ICACHE_LINESIZE - 1)
#define DCACHE_SIZE 0x2000 // 8K
#define DCACHE_LINESIZE 16 // 4 words
#define DCACHE_LINEMASK (DCACHE_LINESIZE - 1)
// C0_CONFIG register definitions
#define CONFIG_CM 0x80000000 // 1 == Master-Checker enabled
#define CONFIG_EC 0x70000000 // System Clock ratio
#define CONFIG_EC_1_1 0x6 // System Clock ratio 1 :1
#define CONFIG_EC_3_2 0x7 // System Clock ratio 1.5 :1
#define CONFIG_EC_2_1 0x0 // System Clock ratio 2 :1
#define CONFIG_EC_3_1 0x1 // System Clock ratio 3 :1
#define CONFIG_EP 0x0F000000 // Transmit Data Pattern
#define CONFIG_SB 0x00C00000 // Secondary cache block size
#define CONFIG_SS 0x00200000 // Split scache: 0 == I&D combined
#define CONFIG_SW 0x00100000 // scache port: 0==128, 1==64
#define CONFIG_EW 0x000C0000 // System Port width: 0==64, 1==32
#define CONFIG_SC 0x00020000 // 0 -> 2nd cache present
#define CONFIG_SM 0x00010000 // 0 -> Dirty Shared Coherency enable
#define CONFIG_BE 0x00008000 // Endian-ness: 1 --> BE
#define CONFIG_EM 0x00004000 // 1 -> ECC mode, 0 -> parity
#define CONFIG_EB 0x00002000 // Block order:1->sequent,0->subblock
#define CONFIG_IC 0x00000E00 // Primary Icache size
#define CONFIG_DC 0x000001C0 // Primary Dcache size
#define CONFIG_IB 0x00000020 // Icache block size
#define CONFIG_DB 0x00000010 // Dcache block size
#define CONFIG_CU 0x00000008 // Update on Store-conditional
#define CONFIG_K0 0x00000007 // K0SEG Coherency algorithm
#define CONFIG_UNCACHED 0x00000002 // K0 is uncached
#define CONFIG_NONCOHRNT 0x00000003
#define CONFIG_COHRNT_EXLWR 0x00000005
#define CONFIG_SB_SHFT 22 // shift SB to bit position 0
#define CONFIG_IC_SHFT 9 // shift IC to bit position 0
#define CONFIG_DC_SHFT 6 // shift DC to bit position 0
#define CONFIG_BE_SHFT 15 // shift BE to bit position 0
// C0_TAGLO definitions for setting/getting cache states and physaddr bits
#define SADDRMASK 0xFFFFE000 // 31..13 -> scache paddr bits 35..17
#define SVINDEXMASK 0x00000380 // 9..7: prim virt index bits 14..12
#define SSTATEMASK 0x00001C00 // bits 12..10 hold scache line state
#define SINVALID 0x00000000 // invalid --> 000 == state 0
#define SCLEANEXCL 0x00001000 // clean exclusive --> 100 == state 4
#define SDIRTYEXCL 0x00001400 // dirty exclusive --> 101 == state 5
#define SECC_MASK 0x0000007F // low 7 bits are ecc for the tag
#define SADDR_SHIFT 4 // shift STagLo (31..13) to 35..17
#define PADDRMASK 0xFFFFFF00 // PTagLo31..8->prim paddr bits35..12
#define PADDR_SHIFT 4 // roll bits 35..12 down to 31..8
#define PSTATEMASK 0x00C0 // bits 7..6 hold primary line state
#define PINVALID 0x0000 // invalid --> 000 == state 0
#define PCLEANEXCL 0x0080 // clean exclusive --> 10 == state 2
#define PDIRTYEXCL 0x00C0 // dirty exclusive --> 11 == state 3
#define PPARITY_MASK 0x0001 // low bit is parity bit (even).
// C0_CACHE_ERR definitions.
#define CACHERR_ER 0x80000000 // 0: inst ref, 1: data ref
#define CACHERR_EC 0x40000000 // 0: primary, 1: secondary
#define CACHERR_ED 0x20000000 // 1: data error
#define CACHERR_ET 0x10000000 // 1: tag error
#define CACHERR_ES 0x08000000 // 1: external ref, e.g. snoo
#define CACHERR_EE 0x04000000 // error on SysAD bus
#define CACHERR_EB 0x02000000 // complicated, see spec.
#define CACHERR_EI 0x01000000 // complicated, see spec.
#define CACHERR_SIDX_MASK 0x003FFFF8 // secondary cache index
#define CACHERR_PIDX_MASK 0x00000007 // primary cache index
#define CACHERR_PIDX_SHIFT 12 // bits 2..0 are paddr14..12
/*
* R4000 family supports hardware watchpoints:
* C0_WATCHLO:
* bits 31..3 are bits 31..3 of physaddr to watch
* bit 2: reserved; must be written as 0.
* bit 1: when set causes a watchpoint trap on load accesses to paddr.
* bit 0: when set traps on stores to paddr;
* C0_WATCHHI
* bits 31..4 are reserved and must be written as zeros.
* bits 3..0 are bits 35..32 of the physaddr to watch
*/
#define WATCHLO_WTRAP 0x00000001
#define WATCHLO_RTRAP 0x00000002
#define WATCHLO_ADDRMASK 0xFFFFFFF8
#define WATCHLO_VALIDMASK 0xFFFFFFFB
#define WATCHHI_VALIDMASK 0x0000000F
// Coprocessor 0 registers
#define C0_INX C_REG(0)
#define C0_RAND C_REG(1)
#define C0_ENTRYLO0 C_REG(2)
#define C0_ENTRYLO1 C_REG(3)
#define C0_CONTEXT C_REG(4)
#define C0_PAGEMASK C_REG(5) // page mask
#define C0_WIRED C_REG(6) // # wired entries in tlb
#define C0_BADVADDR C_REG(8)
#define C0_COUNT C_REG(9) // free-running counter
#define C0_ENTRYHI C_REG(10)
#define C0_COMPARE C_REG(11) // counter comparison reg.
#define C0_SR C_REG(12)
#define C0_CAUSE C_REG(13)
#define C0_EPC C_REG(14)
#define C0_PRID C_REG(15) // revision identifier
#define C0_CONFIG C_REG(16) // hardware configuration
#define C0_LLADDR C_REG(17) // load linked address
#define C0_WATCHLO C_REG(18) // watchpoint
#define C0_WATCHHI C_REG(19) // watchpoint
#define C0_ECC C_REG(26) // S-cache ECC and primary parity
#define C0_CACHE_ERR C_REG(27) // cache error status
#define C0_TAGLO C_REG(28) // cache operations
#define C0_TAGHI C_REG(29) // cache operations
#define C0_ERROR_EPC C_REG(30) // ECC error prg. counter
// floating-point status register
#define C1_FPCSR C_REG(31)
#define FPCSR_FS 0x01000000 // flush denorm to zero
#define FPCSR_C 0x00800000 // condition bit
#define FPCSR_CE 0x00020000 // cause: unimplemented operation
#define FPCSR_CV 0x00010000 // cause: invalid operation
#define FPCSR_CZ 0x00008000 // cause: division by zero
#define FPCSR_CO 0x00004000 // cause: overflow
#define FPCSR_CU 0x00002000 // cause: underflow
#define FPCSR_CI 0x00001000 // cause: inexact operation
#define FPCSR_EV 0x00000800 // enable: invalid operation
#define FPCSR_EZ 0x00000400 // enable: division by zero
#define FPCSR_EO 0x00000200 // enable: overflow
#define FPCSR_EU 0x00000100 // enable: underflow
#define FPCSR_EI 0x00000080 // enable: inexact operation
#define FPCSR_FV 0x00000040 // flag: invalid operation
#define FPCSR_FZ 0x00000020 // flag: division by zero
#define FPCSR_FO 0x00000010 // flag: overflow
#define FPCSR_FU 0x00000008 // flag: underflow
#define FPCSR_FI 0x00000004 // flag: inexact operation
#define FPCSR_RM_MASK 0x00000003 // rounding mode mask
#define FPCSR_RM_RN 0x00000000 // round to nearest
#define FPCSR_RM_RZ 0x00000001 // round to zero
#define FPCSR_RM_RP 0x00000002 // round to positive infinity
#define FPCSR_RM_RM 0x00000003 // round to negative infinity
#endif
include/ultra64/rcp.h
+89 -8
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@@ -1,14 +1,95 @@
#ifndef ULTRA64_RCP_H
#define ULTRA64_RCP_H
#define VI_NTSC_CLOCK 48681812 /* Hz = 48.681812 MHz */
#define VI_PAL_CLOCK 49656530 /* Hz = 49.656530 MHz */
#define VI_MPAL_CLOCK 48628316 /* Hz = 48.628316 MHz */
#define HW_REG(reg, type) *(volatile type*)((reg) | 0xA0000000)
#define DEVICE_TYPE_CART 0 /* ROM cartridge */
#define DEVICE_TYPE_BULK 1 /* ROM bulk */
#define DEVICE_TYPE_64DD 2 /* 64 Disk Drive */
#define DEVICE_TYPE_SRAM 3 /* SRAM */
#define DEVICE_TYPE_INIT 7 /* initial value */
#define AI_DRAM_ADDR_REG 0x04500000
#define AI_LEN_REG 0x04500004
#define AI_CONTROL_REG 0x04500008
#define AI_STATUS_REG 0x0450000C
#define AI_DACRATE_REG 0x04500010
#define AI_BITRATE_REG 0x04500014
#define AI_STATUS_AI_FULL (1 << 31)
#define AI_STATUS_AI_BUSY (1 << 30)
#define VI_STATUS_REG 0x04400000
#define VI_CONTROL_REG VI_STATUS_REG
#define VI_ORIGIN_REG 0x04400004
#define VI_DRAM_ADDR_REG VI_ORIGIN_REG
#define VI_WIDTH_REG 0x04400008
#define VI_H_WIDTH_REG VI_WIDTH_REG
#define VI_INTR_REG 0x0440000C
#define VI_V_INTER_REG VI_H_WIDTH_REG
#define VI_CURRENT_REG 0x04400010
#define VI_V_CURRENT_LINE_REG VI_CURRENT_REG
#define VI_BURST_REG 0x04400014
#define VI_TIMING_REG VI_BURST_REG
#define VI_V_SYNC_REG 0x04400018 //VI vertical sync
#define VI_H_SYNC_REG 0x0440001C //VI horizontal sync
#define VI_LEAP_REG 0x04400020 //VI horizontal sync leap
#define VI_H_SYNC_LEAP_REG VI_LEAP_REG
#define VI_H_START_REG 0x04400024 //VI horizontal video
#define VI_H_VIDEO_REG VI_H_START_REG
#define VI_V_START_REG 0x04400028 //VI vertical video
#define VI_V_VIDEO_REG VI_V_START_REG
#define VI_V_BURST_REG 0x0440002C //VI vertical burst
#define VI_X_SCALE_REG 0x04400030 //VI x-scale
#define VI_Y_SCALE_REG 0x04400034 //VI y-scale
#define SP_IMEM_START 0x04001000
#define SP_DMEM_START 0x04000000
#define SP_MEM_ADDR_REG 0x04040000
#define SP_DRAM_ADDR_REG 0x04040004
#define SP_RD_LEN_REG 0x04040008
#define SP_WR_LEN_REG 0x0404000C
#define SP_STATUS_REG 0x04040010
#define SP_PC_REG 0x04080000
#define PI_DRAM_ADDR_REG 0x04600000 //PI DRAM address
#define PI_CART_ADDR_REG 0x04600004 //PI pbus (cartridge) address
#define PI_RD_LEN_REG 0x04600008 //PI read length
#define PI_WR_LEN_REG 0x0460000C //PI write length
#define PI_STATUS_REG 0x04600010 //PI status
#define PI_BSD_DOM1_LAT_REG 0x04600014 //PI dom1 latency
#define PI_DOMAIN1_REG 0x04600014
#define PI_BSD_DOM1_PWD_REG 0x04600018 //PI dom1 pulse width
#define PI_BSD_DOM1_PGS_REG 0x0460001C //PI dom1 page size
#define PI_BSD_DOM1_RLS_REG 0x04600020 //PI dom1 release
#define PI_BSD_DOM2_LAT_REG 0x04600024 //PI dom2 latency
#define PI_DOMAIN2_REG 0x04600024
#define PI_BSD_DOM2_PWD_REG 0x04600028 //PI dom2 pulse width
#define PI_BSD_DOM2_PGS_REG 0x0460002C //PI dom2 page size
#define PI_BSD_DOM2_RLS_REG 0x04600030 //PI dom2 release
#define PI_STATUS_BUSY 0x1
#define PI_STATUS_IOBUSY 0x2
#define PI_STATUS_ERROR 0x4
#define PI_STATUS_RESET_CONTROLLER 0x1
#define PI_STATUS_CLEAR_INTR 0x2
#define SI_DRAM_ADDR_REG 0x04800000
#define SI_PIF_ADDR_RD64B_REG 0x04800004
#define SI_PIF_ADDR_WR64B_REG 0x04800010
#define SI_STATUS_REG 0x04800018
#define SI_STATUS_DMA_BUSY 0x1
#define SI_STATUS_IO_READ_BUSY 0x2
#define SI_STATUS_DMA_ERROR 0x8
#define SI_STATUS_INTERRUPT (1 << 12)
#define PIF_RAM_START 0x1FC007C0
#define MI_INIT_MODE_REG 0x04300000
#define MI_MODE_REG MI_INIT_MODE_REG
#define MI_VERSION_REG 0x04300004
#define MI_INTR_REG 0x04300008
#define MI_INTR_MASK_REG 0x0430000C
#define VI_NTSC_CLOCK 48681812 /* Hz = 48.681812 MHz */
#define VI_PAL_CLOCK 49656530 /* Hz = 49.656530 MHz */
#define VI_MPAL_CLOCK 48628316 /* Hz = 48.628316 MHz */
#endif
include/ultra64/rdp.h
+9 -10
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@@ -5,19 +5,18 @@
#define DPC_REG_BASE 0xA4100000
#define DPC_START_REG (*(vu32*)(DPC_REG_BASE + 0x00))
#define DPC_END_REG (*(vu32*)(DPC_REG_BASE + 0x04))
#define DPC_CURRENT_REG (*(vu32*)(DPC_REG_BASE + 0x08))
#define DPC_STATUS_REG (*(vu32*)(DPC_REG_BASE + 0x0C))
#define DPC_CLOCK_REG (*(vu32*)(DPC_REG_BASE + 0x10))
#define DPC_BUFBUSY_REG (*(vu32*)(DPC_REG_BASE + 0x14))
#define DPC_PIPEBUSY_REG (*(vu32*)(DPC_REG_BASE + 0x18))
#define DPC_TMEM_REG (*(vu32*)(DPC_REG_BASE + 0x1C))
#define DPC_START_REG (*(vu32*)(DPC_REG_BASE + 0x00))
#define DPC_END_REG (*(vu32*)(DPC_REG_BASE + 0x04))
#define DPC_CURRENT_REG (*(vu32*)(DPC_REG_BASE + 0x08))
#define DPC_STATUS_REG (*(vu32*)(DPC_REG_BASE + 0x0C))
#define DPC_CLOCK_REG (*(vu32*)(DPC_REG_BASE + 0x10))
#define DPC_BUFBUSY_REG (*(vu32*)(DPC_REG_BASE + 0x14))
#define DPC_PIPEBUSY_REG (*(vu32*)(DPC_REG_BASE + 0x18))
#define DPC_TMEM_REG (*(vu32*)(DPC_REG_BASE + 0x1C))
/* DP Span Registers */
#define DPS_REG_BASE 0xA4200000
#define DPS_REG_BASE 0xA4200000
#define DPS_TBIST_REG (*(vu32*)(DPS_REG_BASE + 0x00))
#define DPS_TEST_MODE_REG (*(vu32*)(DPS_REG_BASE + 0x04))
include/ultra64/sptask.h
+9 -8
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@@ -1,14 +1,16 @@
#ifndef ULTRA64_SPTASK_H
#define ULTRA64_SPTASK_H
#include "types.h"
/* Task Types */
#define M_NULTASK 0
#define M_GFXTASK 1
#define M_AUDTASK 2
#define M_VIDTASK 3
#define M_NULTASK 0
#define M_GFXTASK 1
#define M_AUDTASK 2
#define M_VIDTASK 3
#define M_NJPEGTASK 4
#define M_HVQTASK 6
#define M_HVQMTASK 7
#define M_HVQTASK 6
#define M_HVQMTASK 7
/* Task Flags */
#define M_TASK_FLAG0 1
@@ -52,8 +54,7 @@ typedef struct {
/* 0x3C */ u32 yield_data_size;
} OSTask_t; // size = 0x40
typedef union
{
typedef union {
OSTask_t t;
long long int force_structure_alignment;
} OSTask;
include/ultra64/thread.h
+5
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@@ -1,6 +1,8 @@
#ifndef ULTRA64_THREAD_H
#define ULTRA64_THREAD_H
#include "types.h"
#define OS_PRIORITY_MAX 255
#define OS_PRIORITY_VIMGR 254
#define OS_PRIORITY_RMON 250
@@ -15,6 +17,9 @@
#define OS_STATE_RUNNING 4
#define OS_STATE_WAITING 8
#define OS_FLAG_CPU_BREAK 1
#define OS_FLAG_FAULT 2
typedef s32 OSPri;
typedef s32 OSId;
include/ultra64/time.h
+1 -1
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@@ -1,7 +1,7 @@
#ifndef ULTRA64_TIME_H
#define ULTRA64_TIME_H
#include "ultra64/message.h"
#include "message.h"
typedef u64 OSTime;
include/ultra64/vi.h
+33 -1
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@@ -1,6 +1,8 @@
#ifndef ULTRA64_VI_H
#define ULTRA64_VI_H
#include "message.h"
/* Special Features */
#define OS_VI_GAMMA_ON 0x0001
#define OS_VI_GAMMA_OFF 0x0002
@@ -60,7 +62,7 @@ typedef struct {
/* 0x02 */ u16 retraceCount;
/* 0x04 */ void* buffer;
/* 0x08 */ OSViMode* modep;
/* 0x0c */ u32 features;
/* 0x0C */ u32 features;
/* 0x10 */ OSMesgQueue* mq;
/* 0x14 */ OSMesg* msg;
/* 0x18 */ __OSViScale x;
@@ -97,6 +99,36 @@ typedef struct {
#define OS_VI_PAL_HPN2 26
#define OS_VI_PAL_HPF2 27
#define OS_VI_MPAL_LPN1 28 /* MPAL - mainly Brazil */
#define OS_VI_MPAL_LPF1 29
#define OS_VI_MPAL_LAN1 30
#define OS_VI_MPAL_LAF1 31
#define OS_VI_MPAL_LPN2 32
#define OS_VI_MPAL_LPF2 33
#define OS_VI_MPAL_LAN2 34
#define OS_VI_MPAL_LAF2 35
#define OS_VI_MPAL_HPN1 36
#define OS_VI_MPAL_HPF1 37
#define OS_VI_MPAL_HAN1 38
#define OS_VI_MPAL_HAF1 39
#define OS_VI_MPAL_HPN2 40
#define OS_VI_MPAL_HPF2 41
#define OS_VI_FPAL_LPN1 42 /* FPAL - Full screen PAL */
#define OS_VI_FPAL_LPF1 43
#define OS_VI_FPAL_LAN1 44
#define OS_VI_FPAL_LAF1 45
#define OS_VI_FPAL_LPN2 46
#define OS_VI_FPAL_LPF2 47
#define OS_VI_FPAL_LAN2 48
#define OS_VI_FPAL_LAF2 49
#define OS_VI_FPAL_HPN1 50
#define OS_VI_FPAL_HPF1 51
#define OS_VI_FPAL_HAN1 52
#define OS_VI_FPAL_HAF1 53
#define OS_VI_FPAL_HPN2 54
#define OS_VI_FPAL_HPF2 55
#define OS_TV_PAL 0
#define OS_TV_NTSC 1
#define OS_TV_MPAL 2
include/variables.h
+1 -1
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@@ -37,7 +37,7 @@ extern OSViMode osViModePalLan1;
extern u64 osClockRate;
extern s32 osViClock;
extern u32 __osShutdown;
extern u32 __OSGlobalIntMask;
extern OSHWIntr __OSGlobalIntMask;
extern OSThread* __osThreadTail[];
extern OSThread* __osRunQueue;
extern OSThread* __osActiveQueue;
include/z64.h
-2
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@@ -27,8 +27,6 @@
#include "sfx.h"
#include "color.h"
#include "ichain.h"
#include "stdarg.h"
#include "stdlib.h"
#include "regs.h"
#define SCREEN_WIDTH 320