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Common: Switch simd integer bitwise instructions to auto SSE/AVX

This commit is contained in:
TellowKrinkle 2025-06-01 23:52:41 -05:00 committed by TellowKrinkle
parent 86b5de8785
commit 1222270e44
3 changed files with 22 additions and 10 deletions
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10
common/emitter/instructions.h
View File

@ -516,16 +516,16 @@ namespace x86Emitter
// ------------------------------------------------------------------------
extern const xImplSimd_DestRegEither xPAND;
extern const xImplSimd_DestRegEither xPANDN;
extern const xImplSimd_DestRegEither xPOR;
extern const xImplSimd_DestRegEither xPXOR;
extern const xImplSimd_3Arg xPAND;
extern const xImplSimd_3Arg xPANDN;
extern const xImplSimd_3Arg xPOR;
extern const xImplSimd_3Arg xPXOR;
extern const xImplSimd_Shuffle xSHUF;
// ------------------------------------------------------------------------
extern const xImplSimd_DestRegSSE xPTEST;
extern const xImplSimd_2Arg xPTEST;
extern const xImplSimd_MinMax xMIN;
extern const xImplSimd_MinMax xMAX;

10
common/emitter/simd.cpp
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@ -214,15 +214,15 @@ namespace x86Emitter
// clang-format off
const xImplSimd_DestRegEither xPAND = {0x66, 0xdb};
const xImplSimd_DestRegEither xPANDN = {0x66, 0xdf};
const xImplSimd_DestRegEither xPOR = {0x66, 0xeb};
const xImplSimd_DestRegEither xPXOR = {0x66, 0xef};
const xImplSimd_3Arg xPAND = {SIMDInstructionInfo(0xdb).i().p66().commutative()};
const xImplSimd_3Arg xPANDN = {SIMDInstructionInfo(0xdf).i().p66()};
const xImplSimd_3Arg xPOR = {SIMDInstructionInfo(0xeb).i().p66().commutative()};
const xImplSimd_3Arg xPXOR = {SIMDInstructionInfo(0xef).i().p66().commutative()};
// [SSE-4.1] Performs a bitwise AND of dest against src, and sets the ZF flag
// only if all bits in the result are 0. PTEST also sets the CF flag according
// to the following condition: (xmm2/m128 AND NOT xmm1) == 0;
const xImplSimd_DestRegSSE xPTEST = {0x66, 0x1738};
const xImplSimd_2Arg xPTEST = {SIMDInstructionInfo(0x17).p66().m0f38()};
// =====================================================================================================
// SSE Conversion Operations, as looney as they are.

12
tests/ctest/common/x86emitter/codegen_tests_main.cpp
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@ -149,6 +149,12 @@ TEST(CodegenTests, SSETest)
{
x86Emitter::use_avx = false;
CODEGEN_TEST(xPAND(xmm3, xmm8), "66 41 0f db d8");
CODEGEN_TEST(xPANDN(xmm4, xmm9), "66 41 0f df e1");
CODEGEN_TEST(xPOR(xmm5, xmm8), "66 41 0f eb e8");
CODEGEN_TEST(xPXOR(xmm9, xmm4), "66 44 0f ef cc");
CODEGEN_TEST(xPTEST(xmm2, xmm9), "66 41 0f 38 17 d1");
CODEGEN_TEST(xCVTDQ2PD(xmm0, ptr64[rax]), "f3 0f e6 00");
CODEGEN_TEST(xCVTDQ2PS(xmm0, xmm8), "41 0f 5b c0");
CODEGEN_TEST(xCVTPD2DQ(xmm8, ptr128[r8]), "f2 45 0f e6 00");
@ -306,6 +312,12 @@ TEST(CodegenTests, AVXTest)
{
x86Emitter::use_avx = true;
CODEGEN_TEST(xPAND(xmm3, xmm8), "c5 b9 db db"); // => vpand xmm3, xmm8, xmm3
CODEGEN_TEST(xPANDN(xmm4, xmm9), "c4 c1 59 df e1");
CODEGEN_TEST(xPOR(xmm5, xmm8), "c5 b9 eb ed"); // => vpor xmm5, xmm8, xmm5
CODEGEN_TEST(xPXOR(xmm9, xmm4), "c5 31 ef cc");
CODEGEN_TEST(xPTEST(xmm2, xmm9), "c4 c2 79 17 d1");
CODEGEN_TEST(xCVTDQ2PD(xmm0, ptr64[rax]), "c5 fa e6 00");
CODEGEN_TEST(xCVTDQ2PS(xmm0, xmm8), "c4 c1 78 5b c0");
CODEGEN_TEST(xCVTPD2DQ(xmm8, ptr128[r8]), "c4 41 7b e6 00");