mirror of https://github.com/PCSX2/pcsx2
3rdparty: Update CPUInfo to commit 161a9ec374884f4b3e85725cb22e05f9458fdc93
Signed-off-by: SternXD <stern@sidestore.io>
This commit is contained in:
SternXD
Ty
parent
eb0b23a284
commit
35efe8fcb6
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@ -1,4 +1,4 @@
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CMAKE_MINIMUM_REQUIRED(VERSION 3.5 FATAL_ERROR)
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CMAKE_MINIMUM_REQUIRED(VERSION 3.18 FATAL_ERROR)
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# ---[ Setup project
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PROJECT(
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@ -108,7 +108,7 @@ IF(NOT CMAKE_SYSTEM_NAME)
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"Target operating system is not specified. "
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"cpuinfo will compile, but cpuinfo_initialize() will always fail.")
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SET(CPUINFO_SUPPORTED_PLATFORM FALSE)
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ELSEIF(NOT CMAKE_SYSTEM_NAME MATCHES "^(Windows|WindowsStore|CYGWIN|MSYS|Darwin|Linux|Android|FreeBSD)$")
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ELSEIF(NOT CMAKE_SYSTEM_NAME MATCHES "^(Windows|WindowsStore|CYGWIN|MSYS|Darwin|Linux|Android|FreeBSD|Emscripten)$")
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IF(${CMAKE_VERSION} VERSION_GREATER_EQUAL "3.14" AND NOT IS_APPLE_OS)
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MESSAGE(WARNING
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"Target operating system \"${CMAKE_SYSTEM_NAME}\" is not supported in cpuinfo. "
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@ -184,10 +184,11 @@ IF(CPUINFO_SUPPORTED_PLATFORM)
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ELSEIF(CMAKE_SYSTEM_NAME STREQUAL "FreeBSD")
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LIST(APPEND CPUINFO_SRCS src/x86/freebsd/init.c)
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ENDIF()
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ELSEIF(CMAKE_SYSTEM_NAME MATCHES "^Windows" AND CPUINFO_TARGET_PROCESSOR MATCHES "^(ARM64|arm64)$")
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ELSEIF(CMAKE_SYSTEM_NAME MATCHES "^Windows" AND CPUINFO_TARGET_PROCESSOR MATCHES "^(ARM64|arm64|aarch64)$")
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LIST(APPEND CPUINFO_SRCS
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src/arm/windows/init-by-logical-sys-info.c
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src/arm/windows/init.c)
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src/arm/windows/init.c
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src/arm/uarch.c)
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ELSEIF(CPUINFO_TARGET_PROCESSOR MATCHES "^(armv[5-8].*|aarch64|arm64.*)$" OR IOS_ARCH MATCHES "^(armv7.*|arm64.*)$")
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LIST(APPEND CPUINFO_SRCS
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src/arm/uarch.c
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@ -218,7 +219,7 @@ IF(CPUINFO_SUPPORTED_PLATFORM)
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ELSEIF(CPUINFO_TARGET_PROCESSOR MATCHES "^(riscv(32|64))$")
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LIST(APPEND CPUINFO_SRCS
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src/riscv/uarch.c)
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IF(CMAKE_SYSTEM_NAME STREQUAL "Linux")
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IF(CMAKE_SYSTEM_NAME STREQUAL "Linux" OR CMAKE_SYSTEM_NAME STREQUAL "Android")
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LIST(APPEND CPUINFO_SRCS
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src/riscv/linux/init.c
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src/riscv/linux/riscv-hw.c
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@ -747,6 +748,11 @@ IF(CPUINFO_SUPPORTED_PLATFORM AND CPUINFO_BUILD_MOCK_TESTS)
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TARGET_LINK_LIBRARIES(pixel-2-xl-test PRIVATE cpuinfo_mock gtest)
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ADD_TEST(NAME pixel-2-xl-test COMMAND pixel-2-xl-test)
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ADD_EXECUTABLE(pixel-8-test test/mock/pixel-8.cc)
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TARGET_INCLUDE_DIRECTORIES(pixel-8-test BEFORE PRIVATE test/mock)
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TARGET_LINK_LIBRARIES(pixel-8-test PRIVATE cpuinfo_mock gtest)
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ADD_TEST(NAME pixel-8-test COMMAND pixel-8-test)
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ADD_EXECUTABLE(xiaomi-mi-5c-test test/mock/xiaomi-mi-5c.cc)
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TARGET_INCLUDE_DIRECTORIES(xiaomi-mi-5c-test BEFORE PRIVATE test/mock)
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TARGET_LINK_LIBRARIES(xiaomi-mi-5c-test PRIVATE cpuinfo_mock gtest)
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@ -1,11 +1,11 @@
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CMAKE_MINIMUM_REQUIRED(VERSION 2.8.12 FATAL_ERROR)
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CMAKE_MINIMUM_REQUIRED(VERSION 3.18 FATAL_ERROR)
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PROJECT(googlebenchmark-download NONE)
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INCLUDE(ExternalProject)
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ExternalProject_Add(googlebenchmark
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URL https://github.com/google/benchmark/archive/v1.6.1.zip
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URL_HASH SHA256=367e963b8620080aff8c831e24751852cffd1f74ea40f25d9cc1b667a9dd5e45
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URL https://github.com/google/benchmark/archive/refs/tags/v1.9.4.tar.gz
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URL_HASH SHA256=b334658edd35efcf06a99d9be21e4e93e092bd5f95074c1673d5c8705d95c104
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SOURCE_DIR "${CONFU_DEPENDENCIES_SOURCE_DIR}/googlebenchmark"
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BINARY_DIR "${CONFU_DEPENDENCIES_BINARY_DIR}/googlebenchmark"
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CONFIGURE_COMMAND ""
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@ -1,11 +1,11 @@
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CMAKE_MINIMUM_REQUIRED(VERSION 2.8.12 FATAL_ERROR)
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CMAKE_MINIMUM_REQUIRED(VERSION 3.18 FATAL_ERROR)
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PROJECT(googletest-download NONE)
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INCLUDE(ExternalProject)
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ExternalProject_Add(googletest
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URL https://github.com/google/googletest/archive/release-1.11.0.zip
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URL_HASH SHA256=353571c2440176ded91c2de6d6cd88ddd41401d14692ec1f99e35d013feda55a
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URL https://github.com/google/googletest/archive/refs/tags/v1.17.0.zip
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URL_HASH SHA256=40d4ec942217dcc84a9ebe2a68584ada7d4a33a8ee958755763278ea1c5e18ff
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SOURCE_DIR "${CONFU_DEPENDENCIES_SOURCE_DIR}/googletest"
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BINARY_DIR "${CONFU_DEPENDENCIES_BINARY_DIR}/googletest"
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CONFIGURE_COMMAND ""
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@ -373,10 +373,14 @@ enum cpuinfo_uarch {
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cpuinfo_uarch_goldmont = 0x00100404,
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/** Intel Goldmont Plus microarchitecture (Gemini Lake). */
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cpuinfo_uarch_goldmont_plus = 0x00100405,
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/** Intel Gracemont microarchitecture (Twin Lake). */
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cpuinfo_uarch_gracemont = 0x00100406,
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/** Intel Airmont microarchitecture (10 nm out-of-order Atom). */
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cpuinfo_uarch_tremont = 0x00100406,
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/** Intel Gracemont microarchitecture (AlderLake N). */
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cpuinfo_uarch_gracemont = 0x00100407,
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/** Intel Crestmont microarchitecture (Sierra Forest). */
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cpuinfo_uarch_crestmont = 0x00100407,
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cpuinfo_uarch_crestmont = 0x00100408,
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/** Intel Darkmont microarchitecture (e-core used in Clearwater Forest). */
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cpuinfo_uarch_darkmont = 0x00100409,
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/** Intel Knights Ferry HPC boards. */
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cpuinfo_uarch_knights_ferry = 0x00100500,
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@ -388,8 +392,6 @@ enum cpuinfo_uarch {
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cpuinfo_uarch_knights_hill = 0x00100503,
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/** Intel Knights Mill Xeon Phi. */
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cpuinfo_uarch_knights_mill = 0x00100504,
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/** Intel Darkmont microarchitecture (e-core used in Clearwater Forest). */
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cpuinfo_uarch_darkmont = 0x00100505,
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/** Intel/Marvell XScale series. */
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cpuinfo_uarch_xscale = 0x00100600,
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@ -508,6 +510,8 @@ enum cpuinfo_uarch {
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cpuinfo_uarch_cortex_x3 = 0x00300503,
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/** ARM Cortex-X4. */
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cpuinfo_uarch_cortex_x4 = 0x00300504,
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/** ARM Cortex-X925. */
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cpuinfo_uarch_cortex_x925 = 0x00300505,
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/** ARM Cortex-A510. */
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cpuinfo_uarch_cortex_a510 = 0x00300551,
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@ -519,6 +523,8 @@ enum cpuinfo_uarch {
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cpuinfo_uarch_cortex_a715 = 0x00300572,
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/** ARM Cortex-A720. */
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cpuinfo_uarch_cortex_a720 = 0x00300573,
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/** ARM Cortex-A725. */
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cpuinfo_uarch_cortex_a725 = 0x00300574,
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/** Qualcomm Scorpion. */
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cpuinfo_uarch_scorpion = 0x00400100,
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@ -730,7 +736,7 @@ struct cpuinfo_cluster {
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uint64_t frequency;
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};
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#define CPUINFO_PACKAGE_NAME_MAX 48
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#define CPUINFO_PACKAGE_NAME_MAX 64
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struct cpuinfo_package {
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/** SoC or processor chip model name */
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@ -149,8 +149,6 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo(
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cpuinfo_log_warning("VDOT instructions disabled: cause occasional SIGILL on Unisoc T310");
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} else if (chipset->series == cpuinfo_arm_chipset_series_unisoc_ums && chipset->model == 312) {
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cpuinfo_log_warning("VDOT instructions disabled: cause occasional SIGILL on Unisoc UMS312");
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} else if (chipset->vendor == cpuinfo_arm_chipset_vendor_unknown) {
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cpuinfo_log_warning("VDOT instructions disabled: unknown chipset");
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} else {
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switch (midr & (CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK)) {
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case UINT32_C(0x4100D0B0): /* Cortex-A76 */
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@ -468,6 +468,56 @@ static bool match_universal(const char* start, const char* end, struct cpuinfo_a
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return true;
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}
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/**
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* Tries to match /s5e\d{4}$/ signature for Samsung Exynos chipsets.
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* If match successful, extracts model information into \p chipset argument.
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*
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* @param start - start of the platform identifier (ro.product.board or
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* ro.board.platform) to match.
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* @param end - end of the platform identifier (ro.product.board or
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* ro.board.platform) to match.
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* @param[out] chipset - location where chipset information will be stored upon
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* a successful match.
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*
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* @returns true if signature matched, false otherwise.
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*/
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static bool match_s5e(const char* start, const char* end, struct cpuinfo_arm_chipset chipset[restrict static 1]) {
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/* Expect exactly 7 symbols: "s5e" (3 symbols) + 4-digit model number */
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if (start + 7 != end) {
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return false;
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}
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/* Check that string starts with "s5e" */
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if (start[0] != 's') {
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return false;
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}
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/* Load next 2 bytes as little endian 16-bit word */
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const uint16_t expected_5e = load_u16le(start + 1);
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if (expected_5e != UINT16_C(0x6535) /* "e5" = reverse("5e") */) {
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return false;
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}
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/* Check and parse 4-digit model number */
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uint32_t model = 0;
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for (uint32_t i = 3; i < 7; i++) {
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const uint32_t digit = (uint32_t)(uint8_t)start[i] - '0';
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if (digit >= 10) {
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/* Not really a digit */
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return false;
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}
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model = model * 10 + digit;
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}
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/* Return parsed chipset. */
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*chipset = (struct cpuinfo_arm_chipset){
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.vendor = cpuinfo_arm_chipset_vendor_samsung,
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.series = cpuinfo_arm_chipset_series_samsung_exynos,
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.model = model,
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};
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return true;
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}
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/**
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* Compares, case insensitively, a string to known values "SMDK4210" and
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* "SMDK4x12" for Samsung Exynos chipsets. If platform identifier matches one of
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@ -903,7 +953,7 @@ static bool match_sc(const char* start, const char* end, struct cpuinfo_arm_chip
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}
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/**
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* Tries to match, case-sentitively, /Unisoc T\d{3,4}/ signature for Unisoc T
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* Tries to match, case-sentitively, /Unisoc T\d{3,4}/ or /UNISOC T\d{3,4}/ signature for Unisoc T
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* chipset. If match successful, extracts model information into \p chipset
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* argument.
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*
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@ -917,7 +967,7 @@ static bool match_sc(const char* start, const char* end, struct cpuinfo_arm_chip
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* @returns true if signature matched, false otherwise.
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*/
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static bool match_t(const char* start, const char* end, struct cpuinfo_arm_chipset chipset[restrict static 1]) {
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/* Expect 11-12 symbols: "Unisoc T" (8 symbols) + 3-4-digit model number
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/* Expect 11-12 symbols: "Unisoc T" / "UNISOC T" (8 symbols) + 3-4-digit model number
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*/
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const size_t length = end - start;
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switch (length) {
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@ -928,16 +978,18 @@ static bool match_t(const char* start, const char* end, struct cpuinfo_arm_chips
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return false;
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}
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/* Check that string starts with "Unisoc T". The first four characters
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/* Check that string starts with "Unisoc T" or "UNISOC T". The first four characters
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* are loaded as 32-bit little endian word */
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const uint32_t expected_unis = load_u32le(start);
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if (expected_unis != UINT32_C(0x73696E55) /* "sinU" = reverse("Unis") */) {
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if (expected_unis != UINT32_C(0x73696E55) /* "sinU" = reverse("Unis") */ &&
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expected_unis != UINT32_C(0x53494E55) /* "SINU" = reverse("UNIS") */) {
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return false;
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}
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/* The next four characters are loaded as 32-bit little endian word */
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const uint32_t expected_oc_t = load_u32le(start + 4);
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if (expected_oc_t != UINT32_C(0x5420636F) /* "T co" = reverse("oc T") */) {
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if (expected_oc_t != UINT32_C(0x5420636F) /* "T co" = reverse("oc T") */ &&
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expected_oc_t != UINT32_C(0x5420434F) /* "T CO" = reverse("OC T") */) {
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return false;
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}
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@ -2837,6 +2889,15 @@ struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset_from_ro_product_bo
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return chipset;
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}
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/* Check s5eXXXX (Samsung Exynos) signature */
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if (match_s5e(board, board_end, &chipset)) {
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cpuinfo_log_debug(
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"matched S5E (Samsung Exynos) signature in ro.product.board string \"%.*s\"",
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(int)board_length,
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board);
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return chipset;
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}
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#if CPUINFO_ARCH_ARM
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/* Check SMDK (Samsung Exynos) signature */
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if (match_and_parse_smdk(board, board_end, cores, &chipset)) {
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@ -3949,6 +4010,20 @@ static inline struct cpuinfo_arm_chipset disambiguate_spreadtrum_chipset(
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return *ro_board_platform_chipset;
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}
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static enum cpuinfo_arm_chipset_vendor disambiguate_chipset_vendor(
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enum cpuinfo_arm_chipset_vendor vendor_a,
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enum cpuinfo_arm_chipset_vendor vendor_b) {
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/* Some UNISOC-based platforms reporting conflicting vendor names depending
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* on the source. For phones that report both UNISOC and Spreadtrum, treat it
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* as UNISOC. */
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if ((vendor_a == cpuinfo_arm_chipset_vendor_unisoc && vendor_b == cpuinfo_arm_chipset_vendor_spreadtrum) ||
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(vendor_a == cpuinfo_arm_chipset_vendor_spreadtrum && vendor_b == cpuinfo_arm_chipset_vendor_unisoc)) {
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return cpuinfo_arm_chipset_vendor_unisoc;
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}
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return cpuinfo_arm_chipset_vendor_unknown;
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}
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/*
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* Decodes chipset name from Android system properties:
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* - /proc/cpuinfo Hardware string
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@ -4009,13 +4084,22 @@ struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset(
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} else if (vendor != decoded_vendor) {
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/* Parsing different system properties produces
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* different chipset vendors. This situation is
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* rare. */
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* rare. Try to disambiguate for known cases,
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* otherwise treat as unknown. */
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enum cpuinfo_arm_chipset_vendor disambiguated_vendor =
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disambiguate_chipset_vendor(vendor, decoded_vendor);
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if (disambiguated_vendor != cpuinfo_arm_chipset_vendor_unknown) {
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vendor = disambiguated_vendor;
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} else {
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cpuinfo_log_error(
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"chipset detection failed: different chipset vendors reported in different system properties");
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goto finish;
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}
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}
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}
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}
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if (vendor == cpuinfo_arm_chipset_vendor_unknown) {
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cpuinfo_log_warning("chipset detection failed: none of the system properties matched known signatures");
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goto finish;
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@ -125,6 +125,18 @@ void cpuinfo_arm_decode_vendor_uarch(
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case 0xD4F: /* Neoverse V2 */
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*uarch = cpuinfo_uarch_neoverse_v2;
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break;
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case 0xD81: /* Cortex-A720 */
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*uarch = cpuinfo_uarch_cortex_a720;
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break;
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case 0xD82: /* Cortex-X4 */
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*uarch = cpuinfo_uarch_cortex_x4;
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break;
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case 0xD85: /* Cortex-X925 */
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*uarch = cpuinfo_uarch_cortex_x925;
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break;
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case 0xD87: /* Cortex-A725 */
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*uarch = cpuinfo_uarch_cortex_a725;
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break;
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default:
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switch (midr_get_part(midr) >> 8) {
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#if CPUINFO_ARCH_ARM
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|
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@ -750,12 +750,6 @@ void store_core_info_per_processor(
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if (cores) {
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processors[processor_global_index].core = cores + core_id;
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cores[core_id].core_id = core_id;
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if (chip_info->uarchs == NULL) {
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cpuinfo_log_error("uarch is NULL for core %d", core_id);
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return;
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}
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cores[core_id].uarch = chip_info->uarchs[0].uarch;
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cores[core_id].frequency = chip_info->uarchs[0].frequency;
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@ -842,7 +836,6 @@ static bool connect_packages_cores_clusters_by_processors(
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processor->cluster = cluster;
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if (chip_info) {
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size_t converted_chars = 0;
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if (!WideCharToMultiByte(
|
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CP_UTF8,
|
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WC_ERR_INVALID_CHARS,
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|
|
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|
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@ -21,7 +21,6 @@ static struct woa_chip_info woa_chip_unknown = {L"Unknown", {{cpuinfo_vendor_unk
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|||
|
||||
BOOL CALLBACK cpuinfo_arm_windows_init(PINIT_ONCE init_once, PVOID parameter, PVOID* context) {
|
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struct woa_chip_info* chip_info = NULL;
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enum cpuinfo_vendor vendor = cpuinfo_vendor_unknown;
|
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|
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set_cpuinfo_isa_fields();
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|
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@ -134,6 +133,26 @@ static struct core_info_by_chip_name get_core_info_from_midr(uint32_t midr, uint
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return info;
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}
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|
||||
/* https://developer.arm.com/documentation/ddi0601/2024-06/AArch64-Registers
|
||||
CP 4000: MIDR_EL1
|
||||
CP 4020: ID_AA64PFR0_EL1
|
||||
CP 4021: ID_AA64PFR1_EL1
|
||||
CP 4028: ID_AA64DFR0_EL1
|
||||
CP 4029: ID_AA64DFR1_EL1
|
||||
CP 402C: ID_AA64AFR0_EL1
|
||||
CP 402D: ID_AA64AFR1_EL1
|
||||
CP 4030: ID_AA64ISAR0_EL1
|
||||
CP 4031: ID_AA64ISAR1_EL1
|
||||
CP 4038: ID_AA64MMFR0_EL1
|
||||
CP 4039: ID_AA64MMFR1_EL1
|
||||
CP 403A: ID_AA64MMFR2_EL1
|
||||
CP 4080: ?
|
||||
CP 4081: ?
|
||||
CP 4100: ?
|
||||
CP 4510: ?
|
||||
CP 5801: ?
|
||||
*/
|
||||
|
||||
static struct woa_chip_info* get_system_info_from_registry(void) {
|
||||
wchar_t* text_buffer = NULL;
|
||||
LPCWSTR cpu0_subkey = L"HARDWARE\\DESCRIPTION\\System\\CentralProcessor\\0";
|
||||
|
|
@ -195,21 +214,40 @@ static void set_cpuinfo_isa_fields(void) {
|
|||
const bool dotprod = IsProcessorFeaturePresent(PF_ARM_V82_DP_INSTRUCTIONS_AVAILABLE) != 0;
|
||||
cpuinfo_isa.dot = dotprod;
|
||||
|
||||
SYSTEM_INFO system_info;
|
||||
GetSystemInfo(&system_info);
|
||||
switch (system_info.wProcessorLevel) {
|
||||
case 0x803: // Kryo 385 Silver (Snapdragon 850)
|
||||
cpuinfo_isa.fp16arith = dotprod;
|
||||
cpuinfo_isa.rdm = dotprod;
|
||||
break;
|
||||
default:
|
||||
cpuinfo_isa.sve = IsProcessorFeaturePresent(PF_ARM_SVE_INSTRUCTIONS_AVAILABLE) != 0;
|
||||
cpuinfo_isa.sve2 = IsProcessorFeaturePresent(PF_ARM_SVE2_INSTRUCTIONS_AVAILABLE) != 0;
|
||||
cpuinfo_isa.i8mm = IsProcessorFeaturePresent(PF_ARM_V82_I8MM_INSTRUCTIONS_AVAILABLE) != 0;
|
||||
cpuinfo_isa.jscvt = IsProcessorFeaturePresent(PF_ARM_V83_JSCVT_INSTRUCTIONS_AVAILABLE) != 0;
|
||||
cpuinfo_isa.fcma = IsProcessorFeaturePresent(PF_ARM_FMAC_INSTRUCTIONS_AVAILABLE) != 0;
|
||||
// FEAT_FP16 Implies FEAT_FHM in 8.4
|
||||
// https://developer.arm.com/documentation/109697/2025_09/Feature-descriptions/The-Armv8-4-architecture-extension?lang=en
|
||||
cpuinfo_isa.fhm = IsProcessorFeaturePresent(PF_ARM_V82_FP16_INSTRUCTIONS_AVAILABLE) != 0;
|
||||
cpuinfo_isa.fp16arith = cpuinfo_isa.fhm;
|
||||
|
||||
cpuinfo_isa.sme = IsProcessorFeaturePresent(PF_ARM_SME_INSTRUCTIONS_AVAILABLE) != 0;
|
||||
cpuinfo_isa.sme2 = IsProcessorFeaturePresent(PF_ARM_SME2_INSTRUCTIONS_AVAILABLE) != 0;
|
||||
cpuinfo_isa.sme2p1 = IsProcessorFeaturePresent(PF_ARM_SME2_1_INSTRUCTIONS_AVAILABLE) != 0;
|
||||
cpuinfo_isa.sme_b16b16 = IsProcessorFeaturePresent(PF_ARM_SME_B16B16_INSTRUCTIONS_AVAILABLE) != 0;
|
||||
cpuinfo_isa.sme_f16f16 = IsProcessorFeaturePresent(PF_ARM_SME_F16F16_INSTRUCTIONS_AVAILABLE) != 0;
|
||||
|
||||
// TODO: Add when available in Windows SDK
|
||||
// - sme_i16i32
|
||||
// - sme_bi32i32
|
||||
|
||||
cpuinfo_isa.bf16 = IsProcessorFeaturePresent(PF_ARM_V86_BF16_INSTRUCTIONS_AVAILABLE) != 0;
|
||||
|
||||
// TODO: This is not available in the Windows SDK yet , so conservatively go with the lowest value (128 bits)
|
||||
// https://developer.arm.com/documentation/101427/0102/Register-descriptions/Scalable-vector-extensions--SVE--registers/ZCR-EL1--SVE-Control-Register--EL1
|
||||
cpuinfo_isa.svelen =
|
||||
cpuinfo_isa.sve ? 128 / 8 : 0; // This value is in bytes, see cpuinfo_get_max_arm_sve_length
|
||||
|
||||
// TODO : Fetch from feature registers when available
|
||||
// cpuinfo_isa.smelen = 0;
|
||||
|
||||
// Assume that Dot Product support implies FP16
|
||||
// arithmetics and RDM support. ARM manuals don't
|
||||
// guarantee that, but it holds in practice.
|
||||
cpuinfo_isa.fp16arith = dotprod;
|
||||
cpuinfo_isa.rdm = dotprod;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Windows API reports all or nothing for cryptographic instructions. */
|
||||
const bool crypto = IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE) != 0;
|
||||
|
|
|
|||
|
|
@ -19,3 +19,63 @@ struct woa_chip_info {
|
|||
};
|
||||
|
||||
bool cpu_info_init_by_logical_sys_info(const struct woa_chip_info* chip_info, enum cpuinfo_vendor vendor);
|
||||
|
||||
#ifndef PF_ARM_FMAC_INSTRUCTIONS_AVAILABLE
|
||||
#define PF_ARM_FMAC_INSTRUCTIONS_AVAILABLE (27)
|
||||
#endif
|
||||
|
||||
#ifndef PF_ARM_V81_ATOMIC_INSTRUCTIONS_AVAILABLE
|
||||
#define PF_ARM_V81_ATOMIC_INSTRUCTIONS_AVAILABLE (34)
|
||||
#endif
|
||||
|
||||
#ifndef PF_ARM_V83_JSCVT_INSTRUCTIONS_AVAILABLE
|
||||
#define PF_ARM_V83_JSCVT_INSTRUCTIONS_AVAILABLE (44)
|
||||
#endif
|
||||
|
||||
#ifndef PF_ARM_SVE_INSTRUCTIONS_AVAILABLE
|
||||
#define PF_ARM_SVE_INSTRUCTIONS_AVAILABLE (46)
|
||||
#endif
|
||||
|
||||
#ifndef PF_ARM_SVE2_INSTRUCTIONS_AVAILABLE
|
||||
#define PF_ARM_SVE2_INSTRUCTIONS_AVAILABLE (47)
|
||||
#endif
|
||||
|
||||
#ifndef PF_ARM_SME_BI32I32_INSTRUCTIONS_AVAILABLE
|
||||
#define PF_ARM_SME_BI32I32_INSTRUCTIONS_AVAILABLE (55)
|
||||
#endif
|
||||
|
||||
#ifndef PF_ARM_V82_I8MM_INSTRUCTIONS_AVAILABLE
|
||||
#define PF_ARM_V82_I8MM_INSTRUCTIONS_AVAILABLE (66)
|
||||
#endif
|
||||
|
||||
#ifndef PF_ARM_V86_BF16_INSTRUCTIONS_AVAILABLE
|
||||
#define PF_ARM_V86_BF16_INSTRUCTIONS_AVAILABLE (68)
|
||||
#endif
|
||||
|
||||
#ifndef PF_ARM_SME_INSTRUCTIONS_AVAILABLE
|
||||
#define PF_ARM_SME_INSTRUCTIONS_AVAILABLE (70)
|
||||
#endif
|
||||
|
||||
#ifndef PF_ARM_SME2_INSTRUCTIONS_AVAILABLE
|
||||
#define PF_ARM_SME2_INSTRUCTIONS_AVAILABLE (71)
|
||||
#endif
|
||||
|
||||
#ifndef PF_ARM_SME2_1_INSTRUCTIONS_AVAILABLE
|
||||
#define PF_ARM_SME2_1_INSTRUCTIONS_AVAILABLE (72)
|
||||
#endif
|
||||
|
||||
#ifndef PF_ARM_SME2_2_INSTRUCTIONS_AVAILABLE
|
||||
#define PF_ARM_SME2_2_INSTRUCTIONS_AVAILABLE (73)
|
||||
#endif
|
||||
|
||||
#ifndef PF_ARM_SME_F16F16_INSTRUCTIONS_AVAILABLE
|
||||
#define PF_ARM_SME_F16F16_INSTRUCTIONS_AVAILABLE (83)
|
||||
#endif
|
||||
|
||||
#ifndef PF_ARM_SME_B16B16_INSTRUCTIONS_AVAILABLE
|
||||
#define PF_ARM_SME_B16B16_INSTRUCTIONS_AVAILABLE (84)
|
||||
#endif
|
||||
|
||||
#ifndef PF_ARM_V82_FP16_INSTRUCTIONS_AVAILABLE
|
||||
#define PF_ARM_V82_FP16_INSTRUCTIONS_AVAILABLE (67)
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -105,6 +105,7 @@ CPUINFO_INTERNAL void cpuinfo_x86_detect_topology(
|
|||
CPUINFO_INTERNAL void cpuinfo_x86_detect_cache(
|
||||
uint32_t max_base_index,
|
||||
uint32_t max_extended_index,
|
||||
/* amd_topology_extensions is not used, kept for backward compatibility */
|
||||
bool amd_topology_extensions,
|
||||
enum cpuinfo_vendor vendor,
|
||||
const struct cpuinfo_x86_model_info* model_info,
|
||||
|
|
|
|||
|
|
@ -87,7 +87,7 @@ void cpuinfo_x86_detect_cache(
|
|||
}
|
||||
}
|
||||
}
|
||||
if (amd_topology_extensions && max_extended_index >= UINT32_C(0x8000001D)) {
|
||||
if (max_extended_index >= UINT32_C(0x8000001D)) {
|
||||
struct cpuid_regs leaf0x8000001D;
|
||||
uint32_t input_ecx = 0;
|
||||
do {
|
||||
|
|
|
|||
|
|
@ -72,7 +72,7 @@ void cpuinfo_x86_init_processor(struct cpuinfo_x86_processor* processor) {
|
|||
for (uint32_t i = 0; i < 3; i++) {
|
||||
brand_string[i] = cpuid(UINT32_C(0x80000002) + i);
|
||||
}
|
||||
memcpy(processor->brand_string, brand_string, sizeof(processor->brand_string));
|
||||
memcpy(processor->brand_string, brand_string, sizeof(brand_string));
|
||||
cpuinfo_log_debug("raw CPUID brand string: \"%48s\"", processor->brand_string);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -188,10 +188,17 @@ enum cpuinfo_uarch cpuinfo_x86_decode_uarch(
|
|||
case 0x5A: // Moorefield
|
||||
case 0x5D: // SoFIA
|
||||
return cpuinfo_uarch_silvermont;
|
||||
case 0xBE: // Twin Lake
|
||||
case 0x86: // Jasper Lake
|
||||
case 0x8A: // Lakefield
|
||||
case 0x96: // Elkhart Lake
|
||||
case 0x9C: // Jacobsville
|
||||
return cpuinfo_uarch_tremont;
|
||||
case 0xBE: // Alder Lake-N
|
||||
return cpuinfo_uarch_gracemont;
|
||||
case 0xAF: // Sierra Forest
|
||||
return cpuinfo_uarch_crestmont;
|
||||
case 0xDD: // Clearwater Forest
|
||||
return cpuinfo_uarch_darkmont;
|
||||
case 0x4C: // Braswell, Cherry
|
||||
// Trail
|
||||
case 0x75: // Spreadtrum
|
||||
|
|
@ -208,8 +215,6 @@ enum cpuinfo_uarch cpuinfo_x86_decode_uarch(
|
|||
return cpuinfo_uarch_knights_landing;
|
||||
case 0x85:
|
||||
return cpuinfo_uarch_knights_mill;
|
||||
case 0xDD: // Clearwater Forest
|
||||
return cpuinfo_uarch_darkmont;
|
||||
}
|
||||
break;
|
||||
case 0x0F:
|
||||
|
|
|
|||
Loading…
Reference in New Issue