mirror
/
pcsx2
mirror of https://github.com/PCSX2/pcsx2
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Common: Switch movd/q to auto SSE/AVX

This commit is contained in:
TellowKrinkle 2025-08-09 22:38:32 -05:00 committed by TellowKrinkle
parent 338e1a71a9
commit 88515d58ab
3 changed files with 41 additions and 29 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
common/emitter/instructions.h
View File

@ -448,16 +448,16 @@ namespace x86Emitter
extern void xFXSAVE(const xIndirectVoid& dest);
extern void xFXRSTOR(const xIndirectVoid& src);
extern void xMOVDZX(const xRegisterSSE& to, const xRegister32or64& from);
extern void xMOVDZX(const xRegisterSSE& to, const xIndirectVoid& src);
extern void xMOVDZX(const xRegisterSSE& dst, const xRegister32or64& src);
extern void xMOVDZX(const xRegisterSSE& dst, const xIndirectVoid& src);
extern void xMOVD(const xRegister32or64& to, const xRegisterSSE& from);
extern void xMOVD(const xIndirectVoid& dest, const xRegisterSSE& from);
extern void xMOVD(const xRegister32or64& dst, const xRegisterSSE& src);
extern void xMOVD(const xIndirectVoid& dst, const xRegisterSSE& src);
extern void xMOVQ(const xIndirectVoid& dest, const xRegisterSSE& from);
extern void xMOVQ(const xIndirectVoid& dst, const xRegisterSSE& src);
extern void xMOVQZX(const xRegisterSSE& to, const xIndirectVoid& src);
extern void xMOVQZX(const xRegisterSSE& to, const xRegisterSSE& from);
extern void xMOVQZX(const xRegisterSSE& dst, const xIndirectVoid& src);
extern void xMOVQZX(const xRegisterSSE& dst, const xRegisterSSE& src);
extern void xMOVSS(const xRegisterSSE& to, const xRegisterSSE& from);
extern void xMOVSS(const xIndirectVoid& to, const xRegisterSSE& from);

23
common/emitter/simd.cpp
View File

@ -793,26 +793,17 @@ namespace x86Emitter
// * MOVD has valid forms for MMX and XMM registers.
//
__fi void xMOVDZX(const xRegisterSSE& to, const xRegister32or64& from) { xOpWrite0F(0x66, 0x6e, to, from); }
__fi void xMOVDZX(const xRegisterSSE& to, const xIndirectVoid& src) { xOpWrite0F(0x66, 0x6e, to, src); }
__fi void xMOVDZX(const xRegisterSSE& dst, const xRegister32or64& src) { EmitSIMD(SIMDInstructionInfo(0x6e).p66().srcw().mov(), dst, dst, src); }
__fi void xMOVDZX(const xRegisterSSE& dst, const xIndirectVoid& src) { EmitSIMD(SIMDInstructionInfo(0x6e).p66().mov(), dst, dst, src); }
__fi void xMOVD(const xRegister32or64& to, const xRegisterSSE& from) { xOpWrite0F(0x66, 0x7e, from, to); }
__fi void xMOVD(const xIndirectVoid& dest, const xRegisterSSE& from) { xOpWrite0F(0x66, 0x7e, from, dest); }
__fi void xMOVD(const xRegister32or64& dst, const xRegisterSSE& src) { EmitSIMD(SIMDInstructionInfo(0x7e).p66().srcw().mov(), src, src, dst); }
__fi void xMOVD(const xIndirectVoid& dst, const xRegisterSSE& src) { EmitSIMD(SIMDInstructionInfo(0x7e).p66().mov(), src, src, dst); }
// Moves from XMM to XMM, with the *upper 64 bits* of the destination register
// being cleared to zero.
__fi void xMOVQZX(const xRegisterSSE& to, const xRegisterSSE& from) { xOpWrite0F(0xf3, 0x7e, to, from); }
// Moves from XMM to XMM, with the *upper 64 bits* of the destination register
// being cleared to zero.
__fi void xMOVQZX(const xRegisterSSE& to, const xIndirectVoid& src) { xOpWrite0F(0xf3, 0x7e, to, src); }
// Moves from XMM to XMM, with the *upper 64 bits* of the destination register
// being cleared to zero.
__fi void xMOVQZX(const xRegisterSSE& to, const void* src) { xOpWrite0F(0xf3, 0x7e, to, src); }
__fi void xMOVQZX(const xRegisterSSE& dst, const xRegisterSSE& src) { EmitSIMD(SIMDInstructionInfo(0x7e).pf3().mov(), dst, dst, src); }
__fi void xMOVQZX(const xRegisterSSE& dst, const xIndirectVoid& src) { EmitSIMD(SIMDInstructionInfo(0x7e).pf3().mov(), dst, dst, src); }
// Moves lower quad of XMM to ptr64 (no bits are cleared)
__fi void xMOVQ(const xIndirectVoid& dest, const xRegisterSSE& from) { xOpWrite0F(0x66, 0xd6, from, dest); }
__fi void xMOVQ(const xIndirectVoid& dst, const xRegisterSSE& src) { EmitSIMD(SIMDInstructionInfo(0xd6).p66().mov(), src, src, dst); }
//////////////////////////////////////////////////////////////////////////////////////////
//

33
tests/ctest/common/x86emitter/codegen_tests_main.cpp
View File

@ -388,12 +388,19 @@ TEST(CodegenTests, SSETest)
CODEGEN_TEST(xPMOVSX.DQ(xmm2, xmm3), "66 0f 38 25 d3");
CODEGEN_TEST(xPMOVZX.DQ(xmm4, xmm9), "66 41 0f 38 35 e1");
CODEGEN_TEST(xMOVD(eax, xmm1), "66 0f 7e c8");
CODEGEN_TEST(xMOVD(eax, xmm10), "66 44 0f 7e d0");
CODEGEN_TEST(xMOVD(rax, xmm1), "66 48 0f 7e c8");
CODEGEN_TEST(xMOVD(r10, xmm1), "66 49 0f 7e ca");
CODEGEN_TEST(xMOVD(rax, xmm10), "66 4c 0f 7e d0");
CODEGEN_TEST(xMOVD(r10, xmm10), "66 4d 0f 7e d2");
CODEGEN_TEST(xMOVD(eax, xmm1), "66 0f 7e c8");
CODEGEN_TEST(xMOVD(eax, xmm10), "66 44 0f 7e d0");
CODEGEN_TEST(xMOVD(rax, xmm1), "66 48 0f 7e c8");
CODEGEN_TEST(xMOVD(r10, xmm1), "66 49 0f 7e ca");
CODEGEN_TEST(xMOVD(rax, xmm10), "66 4c 0f 7e d0");
CODEGEN_TEST(xMOVD(r10, xmm10), "66 4d 0f 7e d2");
CODEGEN_TEST(xMOVD(ptr[r8], xmm9), "66 45 0f 7e 08");
CODEGEN_TEST(xMOVQ(ptr[r8], xmm9), "66 45 0f d6 08");
CODEGEN_TEST(xMOVDZX(xmm9, ecx), "66 44 0f 6e c9");
CODEGEN_TEST(xMOVDZX(xmm9, rcx), "66 4c 0f 6e c9");
CODEGEN_TEST(xMOVDZX(xmm9, ptr[r9]), "66 45 0f 6e 09");
CODEGEN_TEST(xMOVQZX(xmm9, xmm4), "f3 44 0f 7e cc");
CODEGEN_TEST(xMOVQZX(xmm9, ptr[r8]), "f3 45 0f 7e 08");
}
TEST(CodegenTests, AVXTest)
@ -647,6 +654,20 @@ TEST(CodegenTests, AVXTest)
CODEGEN_TEST(xMOVSHDUP(xmm9, xmm1), "c5 7a 16 c9");
CODEGEN_TEST(xMOVSHDUP(xmm9, xmm8), "c4 41 7a 16 c8");
CODEGEN_TEST(xMOVD(eax, xmm1), "c5 f9 7e c8");
CODEGEN_TEST(xMOVD(eax, xmm10), "c5 79 7e d0");
CODEGEN_TEST(xMOVD(rax, xmm1), "c4 e1 f9 7e c8");
CODEGEN_TEST(xMOVD(r10, xmm1), "c4 c1 f9 7e ca");
CODEGEN_TEST(xMOVD(rax, xmm10), "c4 61 f9 7e d0");
CODEGEN_TEST(xMOVD(r10, xmm10), "c4 41 f9 7e d2");
CODEGEN_TEST(xMOVD(ptr[r8], xmm9), "c4 41 79 7e 08");
CODEGEN_TEST(xMOVQ(ptr[r8], xmm9), "c4 41 79 d6 08");
CODEGEN_TEST(xMOVDZX(xmm9, ecx), "c5 79 6e c9");
CODEGEN_TEST(xMOVDZX(xmm9, rcx), "c4 61 f9 6e c9");
CODEGEN_TEST(xMOVDZX(xmm9, ptr[r9]), "c4 41 79 6e 09");
CODEGEN_TEST(xMOVQZX(xmm9, xmm4), "c5 7a 7e cc");
CODEGEN_TEST(xMOVQZX(xmm9, ptr[r8]), "c4 41 7a 7e 08");
CODEGEN_TEST(xVMOVAPS(xmm0, xmm1), "c5 f8 28 c1");
CODEGEN_TEST(xVMOVAPS(xmm0, ptr32[rdi]), "c5 f8 28 07");
CODEGEN_TEST(xVMOVAPS(ptr32[rdi], xmm0), "c5 f8 29 07");