3rdparty: Update CPUInfo to commit e4cadd02a8b386c38b84f0a19eddacec3f433baa

3rdparty/cpuinfo/README.md

@@ -9,7 +9,7 @@ cpuinfo is a library to detect essential for performance optimization informatio
 ## Features
 
 - **Cross-platform** availability:
-  - Linux, Windows, macOS, Android, and iOS operating systems
+  - Linux, Windows, macOS, Android, iOS and FreeBSD operating systems
   - x86, x86-64, ARM, and ARM64 architectures
 - Modern **C/C++ interface**
   - Thread-safe
@@ -258,6 +258,8 @@ LDFLAGS+= $(pkg-config --libs libcpuinfo)
   - [x] x86
   - [x] x86-64
   - [x] arm64
+- [x] FreeBSD
+  - [x] x86-64
 
 ## Methods
 

3rdparty/cpuinfo/include/cpuinfo.h

@@ -353,6 +353,8 @@ enum cpuinfo_uarch {
 	cpuinfo_uarch_palm_cove = 0x0010020B,
 	/** Intel Sunny Cove microarchitecture (10 nm, Ice Lake). */
 	cpuinfo_uarch_sunny_cove = 0x0010020C,
+	/** Intel Willow Cove microarchitecture (10 nm, Tiger Lake). */
+	cpuinfo_uarch_willow_cove = 0x0010020D,
 
 	/** Pentium 4 with Willamette, Northwood, or Foster cores. */
 	cpuinfo_uarch_willamette = 0x00100300,
@@ -371,6 +373,10 @@ enum cpuinfo_uarch {
 	cpuinfo_uarch_goldmont = 0x00100404,
 	/** Intel Goldmont Plus microarchitecture (Gemini Lake). */
 	cpuinfo_uarch_goldmont_plus = 0x00100405,
+	/** Intel Gracemont microarchitecture (Twin Lake). */
+	cpuinfo_uarch_gracemont = 0x00100406,
+	/** Intel Crestmont microarchitecture (Sierra Forest). */
+	cpuinfo_uarch_crestmont = 0x00100407,
 
 	/** Intel Knights Ferry HPC boards. */
 	cpuinfo_uarch_knights_ferry = 0x00100500,
@@ -382,6 +388,8 @@ enum cpuinfo_uarch {
 	cpuinfo_uarch_knights_hill = 0x00100503,
 	/** Intel Knights Mill Xeon Phi. */
 	cpuinfo_uarch_knights_mill = 0x00100504,
+	/** Intel Darkmont microarchitecture (e-core used in Clearwater Forest). */
+	cpuinfo_uarch_darkmont = 0x00100505,
 
 	/** Intel/Marvell XScale series. */
 	cpuinfo_uarch_xscale = 0x00100600,
@@ -581,6 +589,22 @@ enum cpuinfo_uarch {
 	cpuinfo_uarch_avalanche = 0x0070010D,
 	/** Apple A15 / M2 processor (little cores). */
 	cpuinfo_uarch_blizzard = 0x0070010E,
+	/** Apple A16 processor (big cores). */
+	cpuinfo_uarch_everest = 0x00700200,
+	/** Apple A16 processor (little cores). */
+	cpuinfo_uarch_sawtooth = 0x00700201,
+	/** Apple A17 processor (big cores). */
+	cpuinfo_uarch_coll_everest = 0x00700202,
+	/** Apple A17 processor (little cores). */
+	cpuinfo_uarch_coll_sawtooth = 0x00700203,
+	/** Apple A18 processor (big cores). */
+	cpuinfo_uarch_tupai_everest = 0x00700204,
+	/** Apple A18 processor (little cores). */
+	cpuinfo_uarch_tupai_sawtooth = 0x00700205,
+	/** Apple A18 pro processor (big cores). */
+	cpuinfo_uarch_tahiti_everest = 0x00700206,
+	/** Apple A18 pro processor (little cores). */
+	cpuinfo_uarch_tahiti_sawtooth = 0x00700207,
 
 	/** Cavium ThunderX. */
 	cpuinfo_uarch_thunderx = 0x00800100,
@@ -1700,6 +1724,7 @@ struct cpuinfo_arm_isa {
 	bool sme_b16b16;
 	bool sme_f16f16;
 	uint32_t svelen;
+	uint32_t smelen;
 #endif
 	bool rdm;
 	bool fp16arith;
@@ -2081,6 +2106,15 @@ static inline uint32_t cpuinfo_get_max_arm_sve_length(void) {
 #endif
 }
 
+// Function to get the max SME vector length on ARM CPU's which support SME.
+static inline uint32_t cpuinfo_get_max_arm_sme_length(void) {
+#if CPUINFO_ARCH_ARM64
+	return cpuinfo_isa.smelen * 8; // bytes * 8 = bit length(vector length)
+#else
+	return 0;
+#endif
+}
+
 static inline bool cpuinfo_has_arm_sme(void) {
 #if CPUINFO_ARCH_ARM64
 	return cpuinfo_isa.sme;

3rdparty/cpuinfo/src/arm/linux/aarch32-isa.c

@@ -149,6 +149,8 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo(
 			cpuinfo_log_warning("VDOT instructions disabled: cause occasional SIGILL on Unisoc T310");
 		} else if (chipset->series == cpuinfo_arm_chipset_series_unisoc_ums && chipset->model == 312) {
 			cpuinfo_log_warning("VDOT instructions disabled: cause occasional SIGILL on Unisoc UMS312");
+		} else if (chipset->vendor == cpuinfo_arm_chipset_vendor_unknown) {
+			cpuinfo_log_warning("VDOT instructions disabled: unknown chipset");
 		} else {
 			switch (midr & (CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK)) {
 				case UINT32_C(0x4100D0B0): /* Cortex-A76 */

3rdparty/cpuinfo/src/arm/linux/aarch64-isa.c

@@ -191,4 +191,21 @@ void cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo(
 		// Mask out the SVE vector length bits
 		isa->svelen = ret & PR_SVE_VL_LEN_MASK;
 	}
+
+#ifndef PR_SME_GET_VL
+#define PR_SME_GET_VL 64
+#endif
+
+#ifndef PR_SME_VL_LEN_MASK
+#define PR_SME_VL_LEN_MASK 0xffff
+#endif
+
+	ret = prctl(PR_SME_GET_VL);
+	if (ret < 0) {
+		cpuinfo_log_warning("No SME support on this machine");
+		isa->smelen = 0; // Assume no SME support if the call fails
+	} else {
+		// Mask out the SME vector length bits
+		isa->smelen = ret & PR_SME_VL_LEN_MASK;
+	}
 }

3rdparty/cpuinfo/src/arm/mach/init.c

@@ -27,6 +27,45 @@
 #ifndef CPUFAMILY_ARM_AVALANCHE_BLIZZARD
 #define CPUFAMILY_ARM_AVALANCHE_BLIZZARD 0xDA33D83D
 #endif
+// Following are copied over from ncnn/src/cpu.cpp
+// A16
+#ifndef CPUFAMILY_ARM_EVEREST_SAWTOOTH
+#define CPUFAMILY_ARM_EVEREST_SAWTOOTH 0x8765edea
+#endif
+// A17
+#ifndef CPUFAMILY_ARM_COLL
+#define CPUFAMILY_ARM_COLL 0x2876f5b5
+#endif
+// A18
+#ifndef CPUFAMILY_ARM_TUPAI
+#define CPUFAMILY_ARM_TUPAI 0x204526d0
+#endif
+// A18 Pro
+#ifndef CPUFAMILY_ARM_TAHITI
+#define CPUFAMILY_ARM_TAHITI 0x75d4acb9
+#endif
+// For M3/M4 we need to populate more information about
+// efficiency and perf cores.
+// M3
+#ifndef CPUFAMILY_ARM_IBIZA
+#define CPUFAMILY_ARM_IBIZA 0xfa33415e
+#endif
+// M3 Pro
+#ifndef CPUFAMILY_ARM_LOBOS
+#define CPUFAMILY_ARM_LOBOS 0x5f4dea93
+#endif
+// M3 Max
+#ifndef CPUFAMILY_ARM_PALMA
+#define CPUFAMILY_ARM_PALMA 0x72015832
+#endif
+// M4
+#ifndef CPUFAMILY_ARM_DONAN
+#define CPUFAMILY_ARM_DONAN 0x6f5129ac
+#endif
+// M4 Pro / M4 Max
+#ifndef CPUFAMILY_ARM_BRAVA
+#define CPUFAMILY_ARM_BRAVA 0x17d5b93a
+#endif
 
 struct cpuinfo_arm_isa cpuinfo_isa = {
 	.aes = true,
@@ -93,6 +132,23 @@ static enum cpuinfo_uarch decode_uarch(uint32_t cpu_family, uint32_t core_index,
 		case CPUFAMILY_ARM_AVALANCHE_BLIZZARD:
 			/* Hexa-core: 2x Avalanche + 4x Blizzard */
 			return core_index + 4 < core_count ? cpuinfo_uarch_avalanche : cpuinfo_uarch_blizzard;
+		case CPUFAMILY_ARM_EVEREST_SAWTOOTH:
+			/* Hexa-core: 2x Avalanche + 4x Blizzard */
+			return core_index + 4 < core_count ? cpuinfo_uarch_everest : cpuinfo_uarch_sawtooth;
+			return core_index + 4 < core_count ? cpuinfo_uarch_avalanche : cpuinfo_uarch_blizzard;
+		case CPUFAMILY_ARM_COLL:
+			/* Hexa-core: 2x Avalanche + 4x Blizzard */
+			return core_index + 4 < core_count ? cpuinfo_uarch_coll_everest : cpuinfo_uarch_coll_sawtooth;
+
+		case CPUFAMILY_ARM_TUPAI:
+			/* Hexa-core: 2x Avalanche + 4x Blizzard */
+			return core_index + 4 < core_count ? cpuinfo_uarch_tupai_everest : cpuinfo_uarch_tupai_sawtooth;
+
+		case CPUFAMILY_ARM_TAHITI:
+			/* Hexa-core: 2x Avalanche + 4x Blizzard */
+			return core_index + 4 < core_count ? cpuinfo_uarch_tahiti_everest
+							   : cpuinfo_uarch_tahiti_sawtooth;
+
 		default:
 			/* Use hw.cpusubtype for detection */
 			break;

3rdparty/cpuinfo/src/riscv/linux/riscv-hw.c

@@ -112,7 +112,7 @@ void cpuinfo_riscv_linux_decode_vendor_uarch_from_hwprobe(
 	 *
 	 * for more details.
 	 */
-	int ret = syscall(NR_riscv_hwprobe, pairs, pairs_count, cpu_set_size, (unsigned long*)cpu_set, 0 /* flags */);
+	int ret = syscall(NR_riscv_hwprobe, pairs, pairs_count, cpu_set_size, cpu_set, 0 /* flags */);
 #else
 	int ret = __riscv_hwprobe(pairs, pairs_count, cpu_set_size, (unsigned long*)cpu_set, 0 /* flags */);
 #endif

3rdparty/cpuinfo/src/x86/linux/cpuinfo.c

@@ -80,11 +80,7 @@ struct proc_cpuinfo_parser_state {
  *	Decode a single line of /proc/cpuinfo information.
  *	Lines have format <words-with-spaces>[ ]*:[ ]<space-separated words>
  */
-static bool parse_line(
-	const char* line_start,
-	const char* line_end,
-	void* context,
-	uint64_t line_number) {
+static bool parse_line(const char* line_start, const char* line_end, void* context, uint64_t line_number) {
 	struct proc_cpuinfo_parser_state* restrict state = context;
 	/* Empty line. Skip. */
 	if (line_start == line_end) {
@@ -215,6 +211,5 @@ bool cpuinfo_x86_linux_parse_proc_cpuinfo(
 		.max_processors_count = max_processors_count,
 		.processors = processors,
 	};
-	return cpuinfo_linux_parse_multiline_file(
-		"/proc/cpuinfo", BUFFER_SIZE, parse_line, &state);
+	return cpuinfo_linux_parse_multiline_file("/proc/cpuinfo", BUFFER_SIZE, parse_line, &state);
 }

3rdparty/cpuinfo/src/x86/uarch.c

@@ -168,6 +168,9 @@ enum cpuinfo_uarch cpuinfo_x86_decode_uarch(
 						case 0x7E: // Ice Lake-U
 							return cpuinfo_uarch_sunny_cove;
 
+						case 0x8C: // Tiger U
+						case 0x8D: // Tiger H
+							return cpuinfo_uarch_willow_cove;
 						/* Low-power cores */
 						case 0x1C: // Diamondville,
 							   // Silverthorne,
@@ -185,6 +188,10 @@ enum cpuinfo_uarch cpuinfo_x86_decode_uarch(
 						case 0x5A: // Moorefield
 						case 0x5D: // SoFIA
 							return cpuinfo_uarch_silvermont;
+						case 0xBE: // Twin Lake
+							return cpuinfo_uarch_gracemont;
+						case 0xAF: // Sierra Forest
+							return cpuinfo_uarch_crestmont;
 						case 0x4C: // Braswell, Cherry
 							   // Trail
 						case 0x75: // Spreadtrum
@@ -201,6 +208,8 @@ enum cpuinfo_uarch cpuinfo_x86_decode_uarch(
 							return cpuinfo_uarch_knights_landing;
 						case 0x85:
 							return cpuinfo_uarch_knights_mill;
+						case 0xDD: // Clearwater Forest
+							return cpuinfo_uarch_darkmont;
 					}
 					break;
 				case 0x0F: