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Replace ultra headers with version J

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Ryan Dwyer
2021-10-14 17:52:32 +10:00
parent 735acc6025
commit d3ef0a34ad
299 changed files with 10766 additions and 6225 deletions
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src/include/PR/R4300.h
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/**************************************************************************
* *
* Copyright (C) 1995, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
**************************************************************************/
/**************************************************************************
*
* $Revision: 1.13 $
* $Date: 1997/02/11 08:15:34 $
* $Source: /disk6/Master/cvsmdev2/PR/include/R4300.h,v $
*
**************************************************************************/
#ifndef __R4300_H__
#define __R4300_H__
#include <PR/ultratypes.h>
/*
* Segment base addresses and sizes
*/
#define KUBASE 0
#define KUSIZE 0x80000000
#define K0BASE 0x80000000
#define K0SIZE 0x20000000
#define K1BASE 0xA0000000
#define K1SIZE 0x20000000
#define K2BASE 0xC0000000
#define K2SIZE 0x20000000
/*
* Exception vectors
*/
#define SIZE_EXCVEC 0x80 /* Size of an exc. vec */
#define UT_VEC K0BASE /* utlbmiss vector */
#define R_VEC (K1BASE+0x1fc00000) /* reset vector */
#define XUT_VEC (K0BASE+0x80) /* extended address tlbmiss */
#define ECC_VEC (K0BASE+0x100) /* Ecc exception vector */
#define E_VEC (K0BASE+0x180) /* Gen. exception vector */
/*
* Address conversion macros
*/
#ifdef _LANGUAGE_ASSEMBLY
#define K0_TO_K1(x) ((x)|0xA0000000) /* kseg0 to kseg1 */
#define K1_TO_K0(x) ((x)&0x9FFFFFFF) /* kseg1 to kseg0 */
#define K0_TO_PHYS(x) ((x)&0x1FFFFFFF) /* kseg0 to physical */
#define K1_TO_PHYS(x) ((x)&0x1FFFFFFF) /* kseg1 to physical */
#define KDM_TO_PHYS(x) ((x)&0x1FFFFFFF) /* direct mapped to physical */
#define PHYS_TO_K0(x) ((x)|0x80000000) /* physical to kseg0 */
#define PHYS_TO_K1(x) ((x)|0xA0000000) /* physical to kseg1 */
#else /* _LANGUAGE_C */
#define K0_TO_K1(x) ((u32)(x)|0xA0000000) /* kseg0 to kseg1 */
#define K1_TO_K0(x) ((u32)(x)&0x9FFFFFFF) /* kseg1 to kseg0 */
#define K0_TO_PHYS(x) ((u32)(x)&0x1FFFFFFF) /* kseg0 to physical */
#define K1_TO_PHYS(x) ((u32)(x)&0x1FFFFFFF) /* kseg1 to physical */
#define KDM_TO_PHYS(x) ((u32)(x)&0x1FFFFFFF) /* direct mapped to physical */
#define PHYS_TO_K0(x) ((u32)(x)|0x80000000) /* physical to kseg0 */
#define PHYS_TO_K1(x) ((u32)(x)|0xA0000000) /* physical to kseg1 */
#endif /* _LANGUAGE_ASSEMBLY */
/*
* Address predicates
*/
#define IS_KSEG0(x) ((u32)(x) >= K0BASE && (u32)(x) < K1BASE)
#define IS_KSEG1(x) ((u32)(x) >= K1BASE && (u32)(x) < K2BASE)
#define IS_KSEGDM(x) ((u32)(x) >= K0BASE && (u32)(x) < K2BASE)
#define IS_KSEG2(x) ((u32)(x) >= K2BASE && (u32)(x) < KPTE_SHDUBASE)
#define IS_KPTESEG(x) ((u32)(x) >= KPTE_SHDUBASE)
#define IS_KUSEG(x) ((u32)(x) < K0BASE)
/*
* TLB size constants
*/
#define NTLBENTRIES 31 /* entry 31 is reserved by rdb */
#define TLBHI_VPN2MASK 0xffffe000
#define TLBHI_VPN2SHIFT 13
#define TLBHI_PIDMASK 0xff
#define TLBHI_PIDSHIFT 0
#define TLBHI_NPID 255 /* 255 to fit in 8 bits */
#define TLBLO_PFNMASK 0x3fffffc0
#define TLBLO_PFNSHIFT 6
#define TLBLO_CACHMASK 0x38 /* cache coherency algorithm */
#define TLBLO_CACHSHIFT 3
#define TLBLO_UNCACHED 0x10 /* not cached */
#define TLBLO_NONCOHRNT 0x18 /* Cacheable non-coherent */
#define TLBLO_EXLWR 0x28 /* Exclusive write */
#define TLBLO_D 0x4 /* writeable */
#define TLBLO_V 0x2 /* valid bit */
#define TLBLO_G 0x1 /* global access bit */
#define TLBINX_PROBE 0x80000000
#define TLBINX_INXMASK 0x3f
#define TLBINX_INXSHIFT 0
#define TLBRAND_RANDMASK 0x3f
#define TLBRAND_RANDSHIFT 0
#define TLBWIRED_WIREDMASK 0x3f
#define TLBCTXT_BASEMASK 0xff800000
#define TLBCTXT_BASESHIFT 23
#define TLBCTXT_BASEBITS 9
#define TLBCTXT_VPNMASK 0x7ffff0
#define TLBCTXT_VPNSHIFT 4
#define TLBPGMASK_4K 0x0
#define TLBPGMASK_16K 0x6000
#define TLBPGMASK_64K 0x1e000
/*
* Status register
*/
#define SR_CUMASK 0xf0000000 /* coproc usable bits */
#define SR_CU3 0x80000000 /* Coprocessor 3 usable */
#define SR_CU2 0x40000000 /* Coprocessor 2 usable */
#define SR_CU1 0x20000000 /* Coprocessor 1 usable */
#define SR_CU0 0x10000000 /* Coprocessor 0 usable */
#define SR_RP 0x08000000 /* Reduced power (quarter speed) */
#define SR_FR 0x04000000 /* MIPS III FP register mode */
#define SR_RE 0x02000000 /* Reverse endian */
#define SR_ITS 0x01000000 /* Instruction trace support */
#define SR_BEV 0x00400000 /* Use boot exception vectors */
#define SR_TS 0x00200000 /* TLB shutdown */
#define SR_SR 0x00100000 /* Soft reset occured */
#define SR_CH 0x00040000 /* Cache hit for last 'cache' op */
#define SR_CE 0x00020000 /* Create ECC */
#define SR_DE 0x00010000 /* ECC of parity does not cause error */
/*
* Interrupt enable bits
* (NOTE: bits set to 1 enable the corresponding level interrupt)
*/
#define SR_IMASK 0x0000ff00 /* Interrupt mask */
#define SR_IMASK8 0x00000000 /* mask level 8 */
#define SR_IMASK7 0x00008000 /* mask level 7 */
#define SR_IMASK6 0x0000c000 /* mask level 6 */
#define SR_IMASK5 0x0000e000 /* mask level 5 */
#define SR_IMASK4 0x0000f000 /* mask level 4 */
#define SR_IMASK3 0x0000f800 /* mask level 3 */
#define SR_IMASK2 0x0000fc00 /* mask level 2 */
#define SR_IMASK1 0x0000fe00 /* mask level 1 */
#define SR_IMASK0 0x0000ff00 /* mask level 0 */
#define SR_IBIT8 0x00008000 /* bit level 8 */
#define SR_IBIT7 0x00004000 /* bit level 7 */
#define SR_IBIT6 0x00002000 /* bit level 6 */
#define SR_IBIT5 0x00001000 /* bit level 5 */
#define SR_IBIT4 0x00000800 /* bit level 4 */
#define SR_IBIT3 0x00000400 /* bit level 3 */
#define SR_IBIT2 0x00000200 /* bit level 2 */
#define SR_IBIT1 0x00000100 /* bit level 1 */
#define SR_IMASKSHIFT 8
#define SR_KX 0x00000080 /* extended-addr TLB vec in kernel */
#define SR_SX 0x00000040 /* xtended-addr TLB vec supervisor */
#define SR_UX 0x00000020 /* xtended-addr TLB vec in user mode */
#define SR_KSU_MASK 0x00000018 /* mode mask */
#define SR_KSU_USR 0x00000010 /* user mode */
#define SR_KSU_SUP 0x00000008 /* supervisor mode */
#define SR_KSU_KER 0x00000000 /* kernel mode */
#define SR_ERL 0x00000004 /* Error level, 1=>cache error */
#define SR_EXL 0x00000002 /* Exception level, 1=>exception */
#define SR_IE 0x00000001 /* interrupt enable, 1=>enable */
/*
* Cause Register
*/
#define CAUSE_BD 0x80000000 /* Branch delay slot */
#define CAUSE_CEMASK 0x30000000 /* coprocessor error */
#define CAUSE_CESHIFT 28
/* Interrupt pending bits */
#define CAUSE_IP8 0x00008000 /* External level 8 pending - COMPARE */
#define CAUSE_IP7 0x00004000 /* External level 7 pending - INT4 */
#define CAUSE_IP6 0x00002000 /* External level 6 pending - INT3 */
#define CAUSE_IP5 0x00001000 /* External level 5 pending - INT2 */
#define CAUSE_IP4 0x00000800 /* External level 4 pending - INT1 */
#define CAUSE_IP3 0x00000400 /* External level 3 pending - INT0 */
#define CAUSE_SW2 0x00000200 /* Software level 2 pending */
#define CAUSE_SW1 0x00000100 /* Software level 1 pending */
#define CAUSE_IPMASK 0x0000FF00 /* Pending interrupt mask */
#define CAUSE_IPSHIFT 8
#define CAUSE_EXCMASK 0x0000007C /* Cause code bits */
#define CAUSE_EXCSHIFT 2
/* Cause register exception codes */
#define EXC_CODE(x) ((x)<<2)
/* Hardware exception codes */
#define EXC_INT EXC_CODE(0) /* interrupt */
#define EXC_MOD EXC_CODE(1) /* TLB mod */
#define EXC_RMISS EXC_CODE(2) /* Read TLB Miss */
#define EXC_WMISS EXC_CODE(3) /* Write TLB Miss */
#define EXC_RADE EXC_CODE(4) /* Read Address Error */
#define EXC_WADE EXC_CODE(5) /* Write Address Error */
#define EXC_IBE EXC_CODE(6) /* Instruction Bus Error */
#define EXC_DBE EXC_CODE(7) /* Data Bus Error */
#define EXC_SYSCALL EXC_CODE(8) /* SYSCALL */
#define EXC_BREAK EXC_CODE(9) /* BREAKpoint */
#define EXC_II EXC_CODE(10) /* Illegal Instruction */
#define EXC_CPU EXC_CODE(11) /* CoProcessor Unusable */
#define EXC_OV EXC_CODE(12) /* OVerflow */
#define EXC_TRAP EXC_CODE(13) /* Trap exception */
#define EXC_VCEI EXC_CODE(14) /* Virt. Coherency on Inst. fetch */
#define EXC_FPE EXC_CODE(15) /* Floating Point Exception */
#define EXC_WATCH EXC_CODE(23) /* Watchpoint reference */
#define EXC_VCED EXC_CODE(31) /* Virt. Coherency on data read */
/* C0_PRID Defines */
#define C0_IMPMASK 0xff00
#define C0_IMPSHIFT 8
#define C0_REVMASK 0xff
#define C0_MAJREVMASK 0xf0
#define C0_MAJREVSHIFT 4
#define C0_MINREVMASK 0xf
/*
* Coprocessor 0 operations
*/
#define C0_READI 0x1 /* read ITLB entry addressed by C0_INDEX */
#define C0_WRITEI 0x2 /* write ITLB entry addressed by C0_INDEX */
#define C0_WRITER 0x6 /* write ITLB entry addressed by C0_RAND */
#define C0_PROBE 0x8 /* probe for ITLB entry addressed by TLBHI */
#define C0_RFE 0x10 /* restore for exception */
/*
* 'cache' instruction definitions
*/
/* Target cache */
#define CACH_PI 0x0 /* specifies primary inst. cache */
#define CACH_PD 0x1 /* primary data cache */
#define CACH_SI 0x2 /* secondary instruction cache */
#define CACH_SD 0x3 /* secondary data cache */
/* Cache operations */
#define C_IINV 0x0 /* index invalidate (inst, 2nd inst) */
#define C_IWBINV 0x0 /* index writeback inval (d, sd) */
#define C_ILT 0x4 /* index load tag (all) */
#define C_IST 0x8 /* index store tag (all) */
#define C_CDX 0xc /* create dirty exclusive (d, sd) */
#define C_HINV 0x10 /* hit invalidate (all) */
#define C_HWBINV 0x14 /* hit writeback inv. (d, sd) */
#define C_FILL 0x14 /* fill (i) */
#define C_HWB 0x18 /* hit writeback (i, d, sd) */
#define C_HSV 0x1c /* hit set virt. (si, sd) */
/*
* Cache size definitions
*/
#define ICACHE_SIZE 0x4000 /* 16K */
#define ICACHE_LINESIZE 32 /* 8 words */
#define ICACHE_LINEMASK (ICACHE_LINESIZE-1)
#define DCACHE_SIZE 0x2000 /* 8K */
#define DCACHE_LINESIZE 16 /* 4 words */
#define DCACHE_LINEMASK (DCACHE_LINESIZE-1)
/*
* C0_CONFIG register definitions
*/
#define CONFIG_CM 0x80000000 /* 1 == Master-Checker enabled */
#define CONFIG_EC 0x70000000 /* System Clock ratio */
#define CONFIG_EC_1_1 0x6 /* System Clock ratio 1 :1 */
#define CONFIG_EC_3_2 0x7 /* System Clock ratio 1.5 :1 */
#define CONFIG_EC_2_1 0x0 /* System Clock ratio 2 :1 */
#define CONFIG_EC_3_1 0x1 /* System Clock ratio 3 :1 */
#define CONFIG_EP 0x0f000000 /* Transmit Data Pattern */
#define CONFIG_SB 0x00c00000 /* Secondary cache block size */
#define CONFIG_SS 0x00200000 /* Split scache: 0 == I&D combined */
#define CONFIG_SW 0x00100000 /* scache port: 0==128, 1==64 */
#define CONFIG_EW 0x000c0000 /* System Port width: 0==64, 1==32 */
#define CONFIG_SC 0x00020000 /* 0 -> 2nd cache present */
#define CONFIG_SM 0x00010000 /* 0 -> Dirty Shared Coherency enabled*/
#define CONFIG_BE 0x00008000 /* Endian-ness: 1 --> BE */
#define CONFIG_EM 0x00004000 /* 1 -> ECC mode, 0 -> parity */
#define CONFIG_EB 0x00002000 /* Block order:1->sequent,0->subblock */
#define CONFIG_IC 0x00000e00 /* Primary Icache size */
#define CONFIG_DC 0x000001c0 /* Primary Dcache size */
#define CONFIG_IB 0x00000020 /* Icache block size */
#define CONFIG_DB 0x00000010 /* Dcache block size */
#define CONFIG_CU 0x00000008 /* Update on Store-conditional */
#define CONFIG_K0 0x00000007 /* K0SEG Coherency algorithm */
#define CONFIG_UNCACHED 0x00000002 /* K0 is uncached */
#define CONFIG_NONCOHRNT 0x00000003
#define CONFIG_COHRNT_EXLWR 0x00000005
#define CONFIG_SB_SHFT 22 /* shift SB to bit position 0 */
#define CONFIG_IC_SHFT 9 /* shift IC to bit position 0 */
#define CONFIG_DC_SHFT 6 /* shift DC to bit position 0 */
#define CONFIG_BE_SHFT 15 /* shift BE to bit position 0 */
/*
* C0_TAGLO definitions for setting/getting cache states and physaddr bits
*/
#define SADDRMASK 0xFFFFE000 /* 31..13 -> scache paddr bits 35..17 */
#define SVINDEXMASK 0x00000380 /* 9..7: prim virt index bits 14..12 */
#define SSTATEMASK 0x00001c00 /* bits 12..10 hold scache line state */
#define SINVALID 0x00000000 /* invalid --> 000 == state 0 */
#define SCLEANEXCL 0x00001000 /* clean exclusive --> 100 == state 4 */
#define SDIRTYEXCL 0x00001400 /* dirty exclusive --> 101 == state 5 */
#define SECC_MASK 0x0000007f /* low 7 bits are ecc for the tag */
#define SADDR_SHIFT 4 /* shift STagLo (31..13) to 35..17 */
#define PADDRMASK 0xFFFFFF00 /* PTagLo31..8->prim paddr bits35..12 */
#define PADDR_SHIFT 4 /* roll bits 35..12 down to 31..8 */
#define PSTATEMASK 0x00C0 /* bits 7..6 hold primary line state */
#define PINVALID 0x0000 /* invalid --> 000 == state 0 */
#define PCLEANEXCL 0x0080 /* clean exclusive --> 10 == state 2 */
#define PDIRTYEXCL 0x00C0 /* dirty exclusive --> 11 == state 3 */
#define PPARITY_MASK 0x0001 /* low bit is parity bit (even). */
/*
* C0_CACHE_ERR definitions.
*/
#define CACHERR_ER 0x80000000 /* 0: inst ref, 1: data ref */
#define CACHERR_EC 0x40000000 /* 0: primary, 1: secondary */
#define CACHERR_ED 0x20000000 /* 1: data error */
#define CACHERR_ET 0x10000000 /* 1: tag error */
#define CACHERR_ES 0x08000000 /* 1: external ref, e.g. snoop*/
#define CACHERR_EE 0x04000000 /* error on SysAD bus */
#define CACHERR_EB 0x02000000 /* complicated, see spec. */
#define CACHERR_EI 0x01000000 /* complicated, see spec. */
#define CACHERR_SIDX_MASK 0x003ffff8 /* secondary cache index */
#define CACHERR_PIDX_MASK 0x00000007 /* primary cache index */
#define CACHERR_PIDX_SHIFT 12 /* bits 2..0 are paddr14..12 */
/* R4000 family supports hardware watchpoints:
* C0_WATCHLO:
* bits 31..3 are bits 31..3 of physaddr to watch
* bit 2: reserved; must be written as 0.
* bit 1: when set causes a watchpoint trap on load accesses to paddr.
* bit 0: when set traps on stores to paddr;
* C0_WATCHHI
* bits 31..4 are reserved and must be written as zeros.
* bits 3..0 are bits 35..32 of the physaddr to watch
*/
#define WATCHLO_WTRAP 0x00000001
#define WATCHLO_RTRAP 0x00000002
#define WATCHLO_ADDRMASK 0xfffffff8
#define WATCHLO_VALIDMASK 0xfffffffb
#define WATCHHI_VALIDMASK 0x0000000f
/*
* Coprocessor 0 registers
*/
#ifdef _LANGUAGE_ASSEMBLY
#define C0_INX $0
#define C0_RAND $1
#define C0_ENTRYLO0 $2
#define C0_ENTRYLO1 $3
#define C0_CONTEXT $4
#define C0_PAGEMASK $5 /* page mask */
#define C0_WIRED $6 /* # wired entries in tlb */
#define C0_BADVADDR $8
#define C0_COUNT $9 /* free-running counter */
#define C0_ENTRYHI $10
#define C0_SR $12
#define C0_CAUSE $13
#define C0_EPC $14
#define C0_PRID $15 /* revision identifier */
#define C0_COMPARE $11 /* counter comparison reg. */
#define C0_CONFIG $16 /* hardware configuration */
#define C0_LLADDR $17 /* load linked address */
#define C0_WATCHLO $18 /* watchpoint */
#define C0_WATCHHI $19 /* watchpoint */
#define C0_ECC $26 /* S-cache ECC and primary parity */
#define C0_CACHE_ERR $27 /* cache error status */
#define C0_TAGLO $28 /* cache operations */
#define C0_TAGHI $29 /* cache operations */
#define C0_ERROR_EPC $30 /* ECC error prg. counter */
# else /* ! _LANGUAGE_ASSEMBLY */
#define C0_INX 0
#define C0_RAND 1
#define C0_ENTRYLO0 2
#define C0_ENTRYLO1 3
#define C0_CONTEXT 4
#define C0_PAGEMASK 5 /* page mask */
#define C0_WIRED 6 /* # wired entries in tlb */
#define C0_BADVADDR 8
#define C0_COUNT 9 /* free-running counter */
#define C0_ENTRYHI 10
#define C0_SR 12
#define C0_CAUSE 13
#define C0_EPC 14
#define C0_PRID 15 /* revision identifier */
#define C0_COMPARE 11 /* counter comparison reg. */
#define C0_CONFIG 16 /* hardware configuration */
#define C0_LLADDR 17 /* load linked address */
#define C0_WATCHLO 18 /* watchpoint */
#define C0_WATCHHI 19 /* watchpoint */
#define C0_ECC 26 /* S-cache ECC and primary parity */
#define C0_CACHE_ERR 27 /* cache error status */
#define C0_TAGLO 28 /* cache operations */
#define C0_TAGHI 29 /* cache operations */
#define C0_ERROR_EPC 30 /* ECC error prg. counter */
#endif /* _LANGUAGE_ASSEMBLY */
/*
* floating-point status register
*/
#define FPCSR_FS 0x01000000 /* flush denorm to zero */
#define FPCSR_C 0x00800000 /* condition bit */
#define FPCSR_CE 0x00020000 /* cause: unimplemented operation */
#define FPCSR_CV 0x00010000 /* cause: invalid operation */
#define FPCSR_CZ 0x00008000 /* cause: division by zero */
#define FPCSR_CO 0x00004000 /* cause: overflow */
#define FPCSR_CU 0x00002000 /* cause: underflow */
#define FPCSR_CI 0x00001000 /* cause: inexact operation */
#define FPCSR_EV 0x00000800 /* enable: invalid operation */
#define FPCSR_EZ 0x00000400 /* enable: division by zero */
#define FPCSR_EO 0x00000200 /* enable: overflow */
#define FPCSR_EU 0x00000100 /* enable: underflow */
#define FPCSR_EI 0x00000080 /* enable: inexact operation */
#define FPCSR_FV 0x00000040 /* flag: invalid operation */
#define FPCSR_FZ 0x00000020 /* flag: division by zero */
#define FPCSR_FO 0x00000010 /* flag: overflow */
#define FPCSR_FU 0x00000008 /* flag: underflow */
#define FPCSR_FI 0x00000004 /* flag: inexact operation */
#define FPCSR_RM_MASK 0x00000003 /* rounding mode mask */
#define FPCSR_RM_RN 0x00000000 /* round to nearest */
#define FPCSR_RM_RZ 0x00000001 /* round to zero */
#define FPCSR_RM_RP 0x00000002 /* round to positive infinity */
#define FPCSR_RM_RM 0x00000003 /* round to negative infinity */
#endif /* __R4300_H */
src/include/PR/abi.h
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#ifndef _ABI_H_
#define _ABI_H_
/**************************************************************************
* *
* Copyright (C) 1994, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
**************************************************************************/
/**************************************************************************
*
* $Revision: 1.32 $
* $Date: 1997/02/11 08:16:37 $
* $Source: /exdisk2/cvs/N64OS/Master/cvsmdev2/PR/include/abi.h,v $
*
**************************************************************************/
/*
* Header file for the Audio Binary Interface.
* This is included in the Media Binary Interface file
* mbi.h.
*
* This file follows the framework used for graphics.
*
*/
/* Audio commands: */
#define A_SPNOOP 0
#define A_ADPCM 1
#define A_CLEARBUFF 2
#define A_ENVMIXER 3
#define A_LOADBUFF 4
#define A_RESAMPLE 5
#define A_SAVEBUFF 6
#define A_SEGMENT 7
#define A_SETBUFF 8
#define A_SETVOL 9
#define A_DMEMMOVE 10
#define A_LOADADPCM 11
#define A_MIXER 12
#define A_INTERLEAVE 13
#define A_POLEF 14
#define A_SETLOOP 15
#define ACMD_SIZE 32
/*
* Audio flags
*/
#define A_INIT 0x01
#define A_CONTINUE 0x00
#define A_LOOP 0x02
#define A_OUT 0x02
#define A_LEFT 0x02
#define A_RIGHT 0x00
#define A_VOL 0x04
#define A_RATE 0x00
#define A_AUX 0x08
#define A_NOAUX 0x00
#define A_MAIN 0x00
#define A_MIX 0x10
/*
* BEGIN C-specific section: (typedef's)
*/
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
/*
* Data Structures.
*/
typedef struct {
unsigned int cmd:8;
unsigned int flags:8;
unsigned int gain:16;
unsigned int addr;
} Aadpcm;
typedef struct {
unsigned int cmd:8;
unsigned int flags:8;
unsigned int gain:16;
unsigned int addr;
} Apolef;
typedef struct {
unsigned int cmd:8;
unsigned int flags:8;
unsigned int pad1:16;
unsigned int addr;
} Aenvelope;
typedef struct {
unsigned int cmd:8;
unsigned int pad1:8;
unsigned int dmem:16;
unsigned int pad2:16;
unsigned int count:16;
} Aclearbuff;
typedef struct {
unsigned int cmd:8;
unsigned int pad1:8;
unsigned int pad2:16;
unsigned int inL:16;
unsigned int inR:16;
} Ainterleave;
typedef struct {
unsigned int cmd:8;
unsigned int pad1:24;
unsigned int addr;
} Aloadbuff;
typedef struct {
unsigned int cmd:8;
unsigned int flags:8;
unsigned int pad1:16;
unsigned int addr;
} Aenvmixer;
typedef struct {
unsigned int cmd:8;
unsigned int flags:8;
unsigned int gain:16;
unsigned int dmemi:16;
unsigned int dmemo:16;
} Amixer;
typedef struct {
unsigned int cmd:8;
unsigned int flags:8;
unsigned int dmem2:16;
unsigned int addr;
} Apan;
typedef struct {
unsigned int cmd:8;
unsigned int flags:8;
unsigned int pitch:16;
unsigned int addr;
} Aresample;
typedef struct {
unsigned int cmd:8;
unsigned int flags:8;
unsigned int pad1:16;
unsigned int addr;
} Areverb;
typedef struct {
unsigned int cmd:8;
unsigned int pad1:24;
unsigned int addr;
} Asavebuff;
typedef struct {
unsigned int cmd:8;
unsigned int pad1:24;
unsigned int pad2:2;
unsigned int number:4;
unsigned int base:24;
} Asegment;
typedef struct {
unsigned int cmd:8;
unsigned int flags:8;
unsigned int dmemin:16;
unsigned int dmemout:16;
unsigned int count:16;
} Asetbuff;
typedef struct {
unsigned int cmd:8;
unsigned int flags:8;
unsigned int vol:16;
unsigned int voltgt:16;
unsigned int volrate:16;
} Asetvol;
typedef struct {
unsigned int cmd:8;
unsigned int pad1:8;
unsigned int dmemin:16;
unsigned int dmemout:16;
unsigned int count:16;
} Admemmove;
typedef struct {
unsigned int cmd:8;
unsigned int pad1:8;
unsigned int count:16;
unsigned int addr;
} Aloadadpcm;
typedef struct {
unsigned int cmd:8;
unsigned int pad1:8;
unsigned int pad2:16;
unsigned int addr;
} Asetloop;
/*
* Generic Acmd Packet
*/
typedef struct {
unsigned int w0;
unsigned int w1;
} Awords;
typedef union {
Awords words;
Aadpcm adpcm;
Apolef polef;
Aclearbuff clearbuff;
Aenvelope envelope;
Ainterleave interleave;
Aloadbuff loadbuff;
Aenvmixer envmixer;
Aresample resample;
Areverb reverb;
Asavebuff savebuff;
Asegment segment;
Asetbuff setbuff;
Asetvol setvol;
Admemmove dmemmove;
Aloadadpcm loadadpcm;
Amixer mixer;
Asetloop setloop;
long long int force_union_align; /* dummy, force alignment */
} Acmd;
/*
* ADPCM State
*/
typedef short ADPCM_STATE[16];
/*
* Pole filter state
*/
typedef short POLEF_STATE[4];
/*
* Resampler state
*/
typedef short RESAMPLE_STATE[16];
/*
* Resampler constants
*/
#define UNITY_PITCH 0x8000
#define MAX_RATIO 1.99996 /* within .03 cents of +1 octave */
/*
* Enveloper/Mixer state
*/
typedef short ENVMIX_STATE[40];
/*
* Macros to assemble the audio command list
*/
#define aADPCMdec(pkt, f, s) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = _SHIFTL(A_ADPCM, 24, 8) | _SHIFTL(f, 16, 8); \
_a->words.w1 = (unsigned int)(s); \
}
#define aPoleFilter(pkt, f, g, s) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (_SHIFTL(A_POLEF, 24, 8) | _SHIFTL(f, 16, 8) | \
_SHIFTL(g, 0, 16)); \
_a->words.w1 = (unsigned int)(s); \
}
#define aClearBuffer(pkt, d, c) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = _SHIFTL(A_CLEARBUFF, 24, 8) | _SHIFTL(d, 0, 24); \
_a->words.w1 = (unsigned int)(c); \
}
#define aEnvMixer(pkt, f, s) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = _SHIFTL(A_ENVMIXER, 24, 8) | _SHIFTL(f, 16, 8); \
_a->words.w1 = (unsigned int)(s); \
}
#define aInterleave(pkt, l, r) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = _SHIFTL(A_INTERLEAVE, 24, 8); \
_a->words.w1 = _SHIFTL(l, 16, 16) | _SHIFTL(r, 0, 16); \
}
#define aLoadBuffer(pkt, s) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = _SHIFTL(A_LOADBUFF, 24, 8); \
_a->words.w1 = (unsigned int)(s); \
}
#define aMix(pkt, f, g, i, o) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (_SHIFTL(A_MIXER, 24, 8) | _SHIFTL(f, 16, 8) | \
_SHIFTL(g, 0, 16)); \
_a->words.w1 = _SHIFTL(i,16, 16) | _SHIFTL(o, 0, 16); \
}
#define aPan(pkt, f, d, s) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (_SHIFTL(A_PAN, 24, 8) | _SHIFTL(f, 16, 8) | \
_SHIFTL(d, 0, 16)); \
_a->words.w1 = (unsigned int)(s); \
}
#define aResample(pkt, f, p, s) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (_SHIFTL(A_RESAMPLE, 24, 8) | _SHIFTL(f, 16, 8) |\
_SHIFTL(p, 0, 16)); \
_a->words.w1 = (unsigned int)(s); \
}
#define aSaveBuffer(pkt, s) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = _SHIFTL(A_SAVEBUFF, 24, 8); \
_a->words.w1 = (unsigned int)(s); \
}
#define aSegment(pkt, s, b) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = _SHIFTL(A_SEGMENT, 24, 8); \
_a->words.w1 = _SHIFTL(s, 24, 8) | _SHIFTL(b, 0, 24); \
}
#define aSetBuffer(pkt, f, i, o, c) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (_SHIFTL(A_SETBUFF, 24, 8) | _SHIFTL(f, 16, 8) | \
_SHIFTL(i, 0, 16)); \
_a->words.w1 = _SHIFTL(o, 16, 16) | _SHIFTL(c, 0, 16); \
}
#define aSetVolume(pkt, f, v, t, r) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (_SHIFTL(A_SETVOL, 24, 8) | _SHIFTL(f, 16, 16) | \
_SHIFTL(v, 0, 16)); \
_a->words.w1 = _SHIFTL(t, 16, 16) | _SHIFTL(r, 0, 16); \
}
#define aSetLoop(pkt, a) \
{ \
Acmd *_a = (Acmd *)pkt; \
_a->words.w0 = _SHIFTL(A_SETLOOP, 24, 8); \
_a->words.w1 = (unsigned int)(a); \
}
#define aDMEMMove(pkt, i, o, c) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = _SHIFTL(A_DMEMMOVE, 24, 8) | _SHIFTL(i, 0, 24); \
_a->words.w1 = _SHIFTL(o, 16, 16) | _SHIFTL(c, 0, 16); \
}
#define aLoadADPCM(pkt, c, d) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = _SHIFTL(A_LOADADPCM, 24, 8) | _SHIFTL(c, 0, 24); \
_a->words.w1 = (unsigned int) d; \
}
/*
* --------------------------------------------------------------------
* The below command is seemingly declared manually and used for the
* sound driver.
* --------------------------------------------------------------------
*/
// This is a version of aSetAudio which takes a single 32-bit parameter
// instead of two 16-bit ones. According to AziAudio, it is used to set
// ramping values when neither bit 4 nor bit 8 is set in the flags parameter.
#define aSetVolume32(pkt, f, v, tr) \
{ \
Acmd *_a = (Acmd *)pkt; \
\
_a->words.w0 = (_SHIFTL(A_SETVOL, 24, 8) | _SHIFTL(f, 16, 16) | \
_SHIFTL(v, 0, 16)); \
_a->words.w1 = (unsigned int)(tr); \
}
#endif /* _LANGUAGE_C */
#endif /* !_ABI_H_ */
src/include/PR/gbi.h
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src/include/PR/gbi.inc
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@@ -1,971 +0,0 @@
/*
* Graphics Binary Interface
* This supports Fast3D, Fast3DEX, and Fast3DEX2.
*/
/* Fast3DZEX support */
.ifdef F3DZEX_GBI
.set F3DEX_GBI_2, 1
.endif
/* Macros */
/* commands with no parameters */
.macro f3d_noparam cmd
.word (\cmd << 24), 0x00000000
.endm
.macro gsImmp1 cmd, param
.word (\cmd << 24), \param
.endm
/* DMA helper */
.macro gsDma1p cmd, segAddr, length, params
.word (\cmd << 24) | ((\params & 0xFFFF) << 16) | (\length & 0xFFFF)
.word \segAddr
.endm
/* DMA helper 3*/
.macro gsDma3p cmd, byte2, byte3, byte4, segAddr
.byte \cmd, \byte2, \byte3, \byte4
.word \segAddr
.endm
/* Helper for RGBA colors. */
.macro sDPRGBColor cmd r, g, b, a
.word \cmd << 24
.byte \r, \g, \b, \a
.endm
/* Opcodes */
.ifdef F3DEX_GBI_2
.set G_MTX, 0xDA
.set G_MOVEMEM, 0xDC
.set G_VTX, 0x01
.set G_DL, 0xDE
.set G_TRI2, 0x06
.set G_RDPHALF_1, 0xE1
.set G_RDPHALF_2, 0xF1
.set G_GEOMETRYMODE, 0xD9 /* Fast3DEX2 uses one GeometryMode opcode. */
.set G_ENDDL, 0xDF
.set G_SETOTHERMODE_L, 0xE2
.set G_SETOTHERMODE_H, 0xE3
.set G_TEXTURE, 0xD7
.set G_MOVEWORD, 0xDB
.set G_TRI1, 0x05
.set G_NOOP, 0xC0
.set G_RDPLOADSYNC, 0xE6
.set G_RDPPIPESYNC, 0xE7
.set G_RDPTILESYNC, 0xE8
.set G_RDPFULLSYNC, 0xE9
.set G_LOADTLUT, 0xF0
.set G_SETTILESIZE, 0xF2
.set G_LOADBLOCK, 0xF3
.set G_SETTILE, 0xF5
.set G_SETFILLCOLOR, 0xF7
.set G_SETFOGCOLOR, 0xF8
.set G_SETBLENDCOLOR, 0xF9
.set G_SETPRIMCOLOR, 0xFA
.set G_SETENVCOLOR, 0xFB
.set G_SETCOMBINE, 0xFC
.set G_SETTIMG, 0xFD
.set G_TEXRECT, 0xE4
.else /* F3D and F3DEX */
.set G_MTX, 0x01
.set G_MOVEMEM, 0x03
.set G_VTX, 0x04
.set G_DL, 0x06
.set G_TRI2, 0xB1
.set G_RDPHALF_CONT, 0xB2
.set G_RDPHALF_2, 0xB3
.set G_RDPHALF_1, 0xB4
.set G_CLEARGEOMETRYMODE, 0xB6
.set G_SETGEOMETRYMODE, 0xB7
.set G_ENDDL, 0xB8
.set G_SETOTHERMODE_L, 0xB9
.set G_SETOTHERMODE_H, 0xBA
.set G_TEXTURE, 0xBB
.set G_MOVEWORD, 0xBC
.set G_TRI1, 0xBF
.set G_NOOP, 0xC0
.set G_TEXRECT, 0xE4
.set G_RDPLOADSYNC, 0xE6
.set G_RDPPIPESYNC, 0xE7
.set G_RDPTILESYNC, 0xE8
.set G_RDPFULLSYNC, 0xE9
.set G_LOADTLUT, 0xF0
.set G_SETTILESIZE, 0xF2
.set G_LOADBLOCK, 0xF3
.set G_SETTILE, 0xF5
.set G_FILLRECT, 0xF6
.set G_SETFILLCOLOR, 0xF7
.set G_SETFOGCOLOR, 0xF8
.set G_SETBLENDCOLOR, 0xF9
.set G_SETPRIMCOLOR, 0xFA
.set G_SETENVCOLOR, 0xFB
.set G_SETCOMBINE, 0xFC
.set G_SETTIMG, 0xFD
.endif
/* Arguments */
/* gSPMatrix */
.ifdef F3DEX_GBI_2
.set G_MTX_MODELVIEW, 0x00
.set G_MTX_PROJECTION, 0x04
.set G_MTX_MUL, 0x00
.set G_MTX_LOAD, 0x02
.set G_MTX_NOPUSH, 0x00
.set G_MTX_PUSH, 0x01
.else /* F3D and F3DEX */
.set G_MTX_MODELVIEW, 0x00
.set G_MTX_PROJECTION, 0x01
.set G_MTX_MUL, 0x00
.set G_MTX_LOAD, 0x02
.set G_MTX_NOPUSH, 0x00
.set G_MTX_PUSH, 0x04
.endif
/* gSPLight */
.ifdef F3DEX_GBI_2
.set G_MVO_L0, (2*24)
.else
.set G_MV_L0, 0x86
.endif
/* gSPDisplayList / gSPBranchDisplayList */
.set G_DL_PUSH, 0x00
.set G_DL_NOPUSH, 0x01
/* gSPXGeometryMode */
.ifdef F3DEX_GBI_2
.set G_ZBUFFER, 0x00000001
.set G_SHADE, 0x00000004
.set G_SHADING_SMOOTH, 0x00200000
.set G_CULL_FRONT, 0x00000200
.set G_CULL_BACK, 0x00000400
.set G_FOG, 0x00010000
.set G_LIGHTING, 0x00020000
.set G_TEXTURE_GEN, 0x00040000
.set G_TEXTURE_GEN_LINEAR, 0x00080000
.else /* F3D and F3DEX */
.set G_ZBUFFER, 0x00000001
.set G_SHADE, 0x00000004
.set G_SHADING_SMOOTH, 0x00000200
.set G_CULL_FRONT, 0x00001000
.set G_CULL_BACK, 0x00002000
.set G_FOG, 0x00010000
.set G_LIGHTING, 0x00020000
.set G_TEXTURE_GEN, 0x00040000
.set G_TEXTURE_GEN_LINEAR, 0x00080000
.endif
/*
* Used for matching F3DEX2-style geometry mode usage.
* Ignored when building with Fast3DEX2.
*/
.set G_ORDER_SFIRST, 0
.set G_ORDER_CFIRST, 1
/* gSPSetOtherMode (L) */
.set G_MDSFT_ALPHACOMPARE, 0
.set G_MDSFT_ZSRCSEL, 2
.set G_MDSFT_RENDERMODE, 3
.set G_MDSFT_BLENDER, 16
.set G_AC_NONE, (0 << G_MDSFT_ALPHACOMPARE)
.set G_AC_THRESHOLD, (1 << G_MDSFT_ALPHACOMPARE)
.set G_AC_DITHER, (3 << G_MDSFT_ALPHACOMPARE)
.set G_ZS_PIXEL, (0 << G_MDSFT_ZSRCSEL)
.set G_ZS_PRIM, (1 << G_MDSFT_ZSRCSEL)
/************************* Set Render Mode *************************/
/* Cycle-Independent Blender Settings */
.set AA_EN, 0x8
.set Z_CMP, 0x10
.set Z_UPD, 0x20
.set IM_RD, 0x40
.set CLR_ON_CVG, 0x80
.set CVG_DST_CLAMP, 0
.set CVG_DST_WRAP, 0x100
.set CVG_DST_FULL, 0x200
.set CVG_DST_SAVE, 0x300
.set ZMODE_OPA, 0
.set ZMODE_INTER, 0x400
.set ZMODE_XLU, 0x800
.set ZMODE_DEC, 0xc00
.set CVG_X_ALPHA, 0x1000
.set ALPHA_CVG_SEL, 0x2000
.set FORCE_BL, 0x4000
.set TEX_EDGE, 0x0000 /* used to be 0x8000 */
/* Cycle-Dependent Blender Settings */
/* Blender runs the formula: (P * A + M - B) / (A + B) */
/* P and M values */
.set G_BL_CLR_IN, 0 /* 1st cycle: get color from input pixel.
2nd cycle: param is the numerator of the formula as computed for the first cycle. */
.set G_BL_CLR_MEM, 1 /* Takes color from the framebuffer */
.set G_BL_CLR_BL, 2 /* Takes color from the blend color register */
.set G_BL_CLR_FOG, 3 /* Takes color from the fog color register */
/* A values */
.set G_BL_A_IN, 0 /* Parameter is alpha value of input pixel */
.set G_BL_A_FOG, 1 /* Alpha value from the fog color register */
.set G_BL_A_SHADE, 2 /* Calculated alpha value for the pixel, presumably */
/* B values */
.set G_BL_1MA, 0 /* 1.0 - source alpha */
.set G_BL_A_MEM, 1 /* Framebuffer alpha value */
.set G_BL_1, 2 /* Constant 1.0 */
/* A and B values */
.set G_BL_0, 3 /* Constant 0.0 */
.macro .BL_DEPENDENT_SETTING label, p, a, m, b
.set \label\()_CYCLE1, ((\p << 30) | (\a << 26) | (\m << 22) | (\b << 18))
.set \label\()_CYCLE2, ((\p << 28) | (\a << 24) | (\m << 20) | (\b << 16))
.endm
.macro .BL_DEPENDENT_SETTING_CYCLE1_ONLY label, p, a, m, b
.set \label, ((\p << 30) | (\a << 26) | (\m << 22) | (\b << 18))
.endm
.BL_DEPENDENT_SETTING BL_DEP_SETTING_ZERO, G_BL_CLR_IN, G_BL_A_IN, G_BL_CLR_IN, G_BL_1MA /* Basically (0, 0, 0 ,0) */
/* Properly label these later! */
.BL_DEPENDENT_SETTING BL_DEP_SETTING_1, G_BL_CLR_IN, G_BL_A_IN, G_BL_CLR_MEM, G_BL_A_MEM
.BL_DEPENDENT_SETTING BL_DEP_SETTING_2, G_BL_CLR_IN, G_BL_A_IN, G_BL_CLR_MEM, G_BL_1MA
.BL_DEPENDENT_SETTING BL_DEP_SETTING_3, G_BL_CLR_IN, G_BL_0, G_BL_CLR_IN, G_BL_1
.BL_DEPENDENT_SETTING BL_DEP_SETTING_4, G_BL_CLR_IN, G_BL_A_FOG, G_BL_CLR_MEM, G_BL_1
.BL_DEPENDENT_SETTING BL_DEP_SETTING_5, G_BL_CLR_IN, G_BL_0, G_BL_CLR_BL, G_BL_A_MEM
.BL_DEPENDENT_SETTING_CYCLE1_ONLY BL_DEP_SETTING_FOG_SHADE_A, G_BL_CLR_FOG, G_BL_A_SHADE, G_BL_CLR_IN, G_BL_1MA
.BL_DEPENDENT_SETTING_CYCLE1_ONLY BL_DEP_SETTING_FOG_PRIM_A, G_BL_CLR_FOG, G_BL_A_FOG, G_BL_CLR_IN, G_BL_1MA
.BL_DEPENDENT_SETTING_CYCLE1_ONLY BL_DEP_SETTING_PASS, G_BL_CLR_IN, G_BL_0, G_BL_CLR_IN, G_BL_1
.macro .SET_RENDER_MODE label, indeptSettings, deptSettings
.set \label , (\indeptSettings | \deptSettings\()_CYCLE1)
.set \label\()2 , (\indeptSettings | \deptSettings\()_CYCLE2)
.endm
/* TODO: Make these more readable */
.SET_RENDER_MODE G_RM_AA_ZB_OPA_SURF, (AA_EN | Z_CMP | Z_UPD | IM_RD | CVG_DST_CLAMP | ZMODE_OPA | ALPHA_CVG_SEL), BL_DEP_SETTING_1
.SET_RENDER_MODE G_RM_RA_ZB_OPA_SURF, (AA_EN | Z_CMP | Z_UPD | CVG_DST_CLAMP | ZMODE_OPA | ALPHA_CVG_SEL), BL_DEP_SETTING_1
.SET_RENDER_MODE G_RM_AA_ZB_XLU_SURF, (AA_EN | Z_CMP | IM_RD | CVG_DST_WRAP | CLR_ON_CVG | FORCE_BL | ZMODE_XLU), BL_DEP_SETTING_2
.SET_RENDER_MODE G_RM_AA_ZB_OPA_DECAL, (AA_EN | Z_CMP | IM_RD | CVG_DST_WRAP | ALPHA_CVG_SEL | ZMODE_DEC), BL_DEP_SETTING_1
.SET_RENDER_MODE G_RM_RA_ZB_OPA_DECAL, (AA_EN | Z_CMP | CVG_DST_WRAP | ALPHA_CVG_SEL | ZMODE_DEC), BL_DEP_SETTING_1
.SET_RENDER_MODE G_RM_AA_ZB_XLU_DECAL, (AA_EN | Z_CMP | IM_RD | CVG_DST_WRAP | CLR_ON_CVG | FORCE_BL | ZMODE_DEC), BL_DEP_SETTING_2
.SET_RENDER_MODE G_RM_AA_ZB_OPA_INTER, (AA_EN | Z_CMP | Z_UPD | IM_RD | CVG_DST_CLAMP | ALPHA_CVG_SEL | ZMODE_INTER), BL_DEP_SETTING_1
.SET_RENDER_MODE G_RM_RA_ZB_OPA_INTER, (AA_EN | Z_CMP | Z_UPD | CVG_DST_CLAMP | ALPHA_CVG_SEL | ZMODE_INTER), BL_DEP_SETTING_1
.SET_RENDER_MODE G_RM_AA_ZB_XLU_INTER, (AA_EN | Z_CMP | IM_RD | CVG_DST_WRAP | CLR_ON_CVG | FORCE_BL | ZMODE_INTER), BL_DEP_SETTING_2
.SET_RENDER_MODE G_RM_AA_ZB_XLU_LINE, (AA_EN | Z_CMP | IM_RD | CVG_DST_CLAMP | CVG_X_ALPHA | ALPHA_CVG_SEL | FORCE_BL | ZMODE_XLU), BL_DEP_SETTING_2
.SET_RENDER_MODE G_RM_AA_ZB_DEC_LINE, (AA_EN | Z_CMP | IM_RD | CVG_DST_SAVE | CVG_X_ALPHA | ALPHA_CVG_SEL | FORCE_BL | ZMODE_DEC), BL_DEP_SETTING_2
.SET_RENDER_MODE G_RM_AA_ZB_TEX_EDGE, (AA_EN | Z_CMP | Z_UPD | IM_RD | CVG_DST_CLAMP | CVG_X_ALPHA | ALPHA_CVG_SEL | ZMODE_OPA | TEX_EDGE), BL_DEP_SETTING_1
.SET_RENDER_MODE G_RM_AA_ZB_TEX_INTER, (AA_EN | Z_CMP | Z_UPD | IM_RD | CVG_DST_CLAMP | CVG_X_ALPHA | ALPHA_CVG_SEL | ZMODE_INTER | TEX_EDGE), BL_DEP_SETTING_1
.SET_RENDER_MODE G_RM_AA_ZB_SUB_SURF, (AA_EN | Z_CMP | Z_UPD | IM_RD | CVG_DST_FULL | ZMODE_OPA | ALPHA_CVG_SEL), BL_DEP_SETTING_1
.SET_RENDER_MODE G_RM_AA_ZB_PCL_SURF, (AA_EN | Z_CMP | Z_UPD | IM_RD | CVG_DST_CLAMP | ZMODE_OPA | G_AC_DITHER), BL_DEP_SETTING_2
.SET_RENDER_MODE G_RM_AA_ZB_OPA_TERR, (AA_EN | Z_CMP | Z_UPD | IM_RD | CVG_DST_CLAMP | ZMODE_OPA | ALPHA_CVG_SEL), BL_DEP_SETTING_2
.SET_RENDER_MODE G_RM_AA_ZB_TEX_TERR, (AA_EN | Z_CMP | Z_UPD | IM_RD | CVG_DST_CLAMP | CVG_X_ALPHA | ALPHA_CVG_SEL | ZMODE_OPA | TEX_EDGE), BL_DEP_SETTING_2
.SET_RENDER_MODE G_RM_AA_ZB_SUB_TERR, (AA_EN | Z_CMP | Z_UPD | IM_RD | CVG_DST_FULL | ZMODE_OPA | ALPHA_CVG_SEL), BL_DEP_SETTING_2
.SET_RENDER_MODE G_RM_AA_OPA_SURF, (AA_EN | IM_RD | CVG_DST_CLAMP | ZMODE_OPA | ALPHA_CVG_SEL), BL_DEP_SETTING_1
.SET_RENDER_MODE G_RM_RA_OPA_SURF, (AA_EN | CVG_DST_CLAMP | ZMODE_OPA | ALPHA_CVG_SEL), BL_DEP_SETTING_1
.SET_RENDER_MODE G_RM_AA_XLU_SURF, (AA_EN | IM_RD | CVG_DST_WRAP | CLR_ON_CVG | FORCE_BL | ZMODE_OPA), BL_DEP_SETTING_2
.SET_RENDER_MODE G_RM_AA_XLU_LINE, (AA_EN | IM_RD | CVG_DST_CLAMP | CVG_X_ALPHA | ALPHA_CVG_SEL | FORCE_BL | ZMODE_OPA), BL_DEP_SETTING_2
.SET_RENDER_MODE G_RM_AA_DEC_LINE, (AA_EN | IM_RD | CVG_DST_FULL | CVG_X_ALPHA | ALPHA_CVG_SEL | FORCE_BL | ZMODE_OPA), BL_DEP_SETTING_2
.SET_RENDER_MODE G_RM_AA_TEX_EDGE, (AA_EN | IM_RD | CVG_DST_CLAMP | CVG_X_ALPHA | ALPHA_CVG_SEL | ZMODE_OPA | TEX_EDGE), BL_DEP_SETTING_1
.SET_RENDER_MODE G_RM_AA_SUB_SURF, (AA_EN | IM_RD | CVG_DST_FULL | ZMODE_OPA | ALPHA_CVG_SEL), BL_DEP_SETTING_1
.SET_RENDER_MODE G_RM_AA_PCL_SURF, (AA_EN | IM_RD | CVG_DST_CLAMP | ZMODE_OPA | G_AC_DITHER), BL_DEP_SETTING_2
.SET_RENDER_MODE G_RM_AA_OPA_TERR, (AA_EN | IM_RD | CVG_DST_CLAMP | ZMODE_OPA | ALPHA_CVG_SEL), BL_DEP_SETTING_2
.SET_RENDER_MODE G_RM_AA_TEX_TERR, (AA_EN | IM_RD | CVG_DST_CLAMP | CVG_X_ALPHA | ALPHA_CVG_SEL | ZMODE_OPA | TEX_EDGE), BL_DEP_SETTING_2
.SET_RENDER_MODE G_RM_AA_SUB_TERR, (AA_EN | IM_RD | CVG_DST_FULL | ZMODE_OPA | ALPHA_CVG_SEL), BL_DEP_SETTING_2
.SET_RENDER_MODE G_RM_ZB_OPA_SURF, (Z_CMP | Z_UPD | CVG_DST_FULL | ALPHA_CVG_SEL | ZMODE_OPA), BL_DEP_SETTING_1
.SET_RENDER_MODE G_RM_ZB_XLU_SURF, (Z_CMP | IM_RD | CVG_DST_FULL | FORCE_BL | ZMODE_XLU), BL_DEP_SETTING_2
.SET_RENDER_MODE G_RM_ZB_OPA_DECAL, (Z_CMP | CVG_DST_FULL | ALPHA_CVG_SEL | ZMODE_DEC), BL_DEP_SETTING_1
.SET_RENDER_MODE G_RM_ZB_XLU_DECAL, (Z_CMP | IM_RD | CVG_DST_FULL | FORCE_BL | ZMODE_DEC), BL_DEP_SETTING_2
.SET_RENDER_MODE G_RM_ZB_CLD_SURF, (Z_CMP | IM_RD | CVG_DST_SAVE | FORCE_BL | ZMODE_XLU), BL_DEP_SETTING_2
.SET_RENDER_MODE G_RM_ZB_OVL_SURF, (Z_CMP | IM_RD | CVG_DST_SAVE | FORCE_BL | ZMODE_DEC), BL_DEP_SETTING_2
.SET_RENDER_MODE G_RM_ZB_PCL_SURF, (Z_CMP | Z_UPD | CVG_DST_FULL | ZMODE_OPA | G_AC_DITHER), BL_DEP_SETTING_3
.SET_RENDER_MODE G_RM_OPA_SURF, (CVG_DST_CLAMP | FORCE_BL | ZMODE_OPA), BL_DEP_SETTING_3
.SET_RENDER_MODE G_RM_XLU_SURF, (IM_RD | CVG_DST_FULL | FORCE_BL | ZMODE_OPA), BL_DEP_SETTING_2
.SET_RENDER_MODE G_RM_TEX_EDGE, (CVG_DST_CLAMP | CVG_X_ALPHA | ALPHA_CVG_SEL | FORCE_BL | ZMODE_OPA | TEX_EDGE | AA_EN), BL_DEP_SETTING_3
.SET_RENDER_MODE G_RM_CLD_SURF, (IM_RD | CVG_DST_SAVE | FORCE_BL | ZMODE_OPA), BL_DEP_SETTING_2
.SET_RENDER_MODE G_RM_PCL_SURF, (CVG_DST_FULL | FORCE_BL | ZMODE_OPA | G_AC_DITHER), BL_DEP_SETTING_3
.SET_RENDER_MODE G_RM_ADD, (IM_RD | CVG_DST_SAVE | FORCE_BL | ZMODE_OPA), BL_DEP_SETTING_4
.SET_RENDER_MODE G_RM_NOOP, (0), BL_DEP_SETTING_ZERO
.SET_RENDER_MODE G_RM_VISCVG, (IM_RD | FORCE_BL), BL_DEP_SETTING_5
.SET_RENDER_MODE G_RM_OPA_CI, (CVG_DST_CLAMP | ZMODE_OPA), BL_DEP_SETTING_3
/* Custom version of G_RM_AA_ZB_XLU_SURF with Z_UPD */
.SET_RENDER_MODE G_RM_CUSTOM_AA_ZB_XLU_SURF, (AA_EN | Z_CMP | Z_UPD | IM_RD | CVG_DST_WRAP | CLR_ON_CVG | FORCE_BL | ZMODE_XLU), BL_DEP_SETTING_2
/* Special mode types only for mode 1 */
.set G_RM_FOG_SHADE_A, BL_DEP_SETTING_FOG_SHADE_A
.set G_RM_FOG_PRIM_A, BL_DEP_SETTING_FOG_PRIM_A
.set G_RM_PASS, BL_DEP_SETTING_PASS
/*******************************************************************/
/* gSPSetOtherMode (H) */
.set G_MDSFT_ALPHADITHER, 4
.set G_MDSFT_RGBDITHER, 6
.set G_MDSFT_COMBKEY, 8
.set G_MDSFT_TEXTCONV, 9
.set G_MDSFT_TEXTFILT, 12
.set G_MDSFT_TEXTLUT, 14
.set G_MDSFT_TEXTLOD, 16
.set G_MDSFT_TEXTDETAIL, 17
.set G_MDSFT_TEXTPERSP, 19
.set G_MDSFT_CYCLETYPE, 20
.set G_MDSFT_PIPELINE, 23
.set G_CYC_1CYCLE, (0 << G_MDSFT_CYCLETYPE)
.set G_CYC_2CYCLE, (1 << G_MDSFT_CYCLETYPE)
.set G_CYC_COPY, (2 << G_MDSFT_CYCLETYPE)
.set G_CYC_FILL, (3 << G_MDSFT_CYCLETYPE)
.set G_TP_NONE, (0 << G_MDSFT_TEXTPERSP)
.set G_TP_PERSP, (1 << G_MDSFT_TEXTPERSP)
.set G_TD_CLAMP, (0 << G_MDSFT_TEXTDETAIL)
.set G_TD_SHARPEN, (1 << G_MDSFT_TEXTDETAIL)
.set G_TD_DETAIL, (2 << G_MDSFT_TEXTDETAIL)
.set G_TL_TILE, (0 << G_MDSFT_TEXTLOD)
.set G_TL_LOD, (1 << G_MDSFT_TEXTLOD)
.set G_TT_NONE, (0 << G_MDSFT_TEXTLUT)
.set G_TT_RGBA16, (2 << G_MDSFT_TEXTLUT)
.set G_TT_IA16, (3 << G_MDSFT_TEXTLUT)
.set G_TF_POINT, (0 << G_MDSFT_TEXTFILT)
.set G_TF_AVERAGE, (3 << G_MDSFT_TEXTFILT)
.set G_TF_BILERP, (2 << G_MDSFT_TEXTFILT)
.set G_TC_CONV, (0 << G_MDSFT_TEXTCONV)
.set G_TC_FILTCONV, (5 << G_MDSFT_TEXTCONV)
.set G_TC_FILT, (6 << G_MDSFT_TEXTCONV)
.set G_CK_NONE, (0 << G_MDSFT_COMBKEY)
.set G_CK_KEY, (1 << G_MDSFT_COMBKEY)
.set G_CD_MAGICSQ, (0 << G_MDSFT_RGBDITHER)
.set G_CD_BAYER, (1 << G_MDSFT_RGBDITHER)
.set G_CD_NOISE, (2 << G_MDSFT_RGBDITHER)
/* gDPSetTile */
.set G_TX_LOADTILE, 0x7
.set G_TX_RENDERTILE, 0x0
/* axis clamp and mirror flags */
.set G_TX_NOMIRROR, 0x0
.set G_TX_WRAP, 0x0
.set G_TX_MIRROR, 0x1
.set G_TX_CLAMP, 0x2
/* mask flags */
.set G_TX_NOMASK, 0x0
/* shift flags */
.set G_TX_NOLOD, 0x0
/* gDPSetCombine */
.set G_CCMUX_COMBINED, 0
.set G_CCMUX_TEXEL0, 1
.set G_CCMUX_TEXEL1, 2
.set G_CCMUX_PRIMITIVE, 3
.set G_CCMUX_SHADE, 4
.set G_CCMUX_ENVIRONMENT, 5
.set G_CCMUX_CENTER, 6
.set G_CCMUX_SCALE, 6
.set G_CCMUX_COMBINED_ALPHA, 7
.set G_CCMUX_TEXEL0_ALPHA, 8
.set G_CCMUX_TEXEL1_ALPHA, 9
.set G_CCMUX_PRIMITIVE_ALPHA, 10
.set G_CCMUX_SHADE_ALPHA, 11
.set G_CCMUX_ENV_ALPHA, 12
.set G_CCMUX_LOD_FRACTION, 13
.set G_CCMUX_PRIM_LOD_FRAC, 14
.set G_CCMUX_NOISE, 7
.set G_CCMUX_K4, 7
.set G_CCMUX_K5, 15
.set G_CCMUX_1, 6
.set G_CCMUX_0, 31
/* alpha combiner */
.set G_ACMUX_COMBINED, 0
.set G_ACMUX_TEXEL0, 1
.set G_ACMUX_TEXEL1, 2
.set G_ACMUX_PRIMITIVE, 3
.set G_ACMUX_SHADE, 4
.set G_ACMUX_ENVIRONMENT, 5
.set G_ACMUX_LOD_FRACTION, 0
.set G_ACMUX_PRIM_LOD_FRAC, 6
.set G_ACMUX_1, 6
.set G_ACMUX_0, 7
/* gDPSetTextureImage */
/* fmt */
.set G_IM_FMT_RGBA, 0x00
.set G_IM_FMT_YUV, 0x01
.set G_IM_FMT_CI, 0x02
.set G_IM_FMT_IA, 0x03
.set G_IM_FMT_I, 0x04
/* size */
.set G_IM_SIZ_4b, 0x00
.set G_IM_SIZ_8b, 0x01
.set G_IM_SIZ_16b, 0x02
.set G_IM_SIZ_32b, 0x03
.set G_TX_DXT_FRAC, 11
.set G_TEXTURE_IMAGE_FRAC, 2
/* gDPLoadBlock*/
.set G_TX_DXT_FRAC, 11
.set G_TEXTURE_IMAGE_FRAC, 2
/* gSPNumLights / gSPFogFactor */
/* Index in DMEM table */
.set G_MW_NUMLIGHT, 0x02
.set G_MW_FOG, 0x08
.set G_MW_PERSPNORM, 0x0E
/* Offsets in DMEM table */
.set G_MWO_NUMLIGHT, 0x00
.set G_MWO_FOG, 0x00
/* Parameter for gsSPNumLights; not really needed but is good for formality. */
.set NUMLIGHTS_0, 1
.set NUMLIGHTS_1, 1
.set NUMLIGHTS_2, 2
.set NUMLIGHTS_3, 3
.set NUMLIGHTS_4, 4
.set NUMLIGHTS_5, 5
.set NUMLIGHTS_6, 6
.set NUMLIGHTS_7, 7
/* GBI macros */
/* gsMoveWd */
.macro gsMoveWd index, offset, data
.ifdef F3DEX_GBI_2
.word G_MOVEWORD << 24 | ((\index & 0xFF) << 16) | (\offset & 0xFFFF)
.else
.word G_MOVEWORD << 24 | ((\offset & 0xFFFF) << 8) | (\index & 0xFF)
.endif
.word \data
.endm
.set G_MWO_NUMLIGHT, 0x00
/*
* gSPNumLights
* Parameter:
* n = NUMLIGHTS_* (ranges from 0 to 7)
*/
.macro gsSPNumLights n
.ifdef F3DEX_GBI_2
gsMoveWd G_MW_NUMLIGHT, G_MWO_NUMLIGHT, (\n * 24)
.else
gsMoveWd G_MW_NUMLIGHT, G_MWO_NUMLIGHT, ((\n + 1) * 32 + 0x80000000)
.endif
.endm
/* gSPMatrix */
.macro gsSPMatrix matrix, params
.ifdef F3DEX_GBI_2
gsDma3p G_MTX, 0x38, 0, (\params ^ G_MTX_PUSH), \matrix
.else /* Fast3D and Fast3DEX */
gsDma1p G_MTX, \matrix, 64, \params
.endif
.endm
/* gSPLight */
.macro gsSPLight light, num
.ifdef F3DEX_GBI_2
gsDma3p G_MOVEMEM, 8, ((G_MVO_L0+((\num-1)*24))/8), 10, \light
.else /* Fast3D and Fast3DEX */
gsDma1p G_MOVEMEM, \light, 16, ((\num)-1)*2+G_MV_L0
.endif
.endm
/* gSPVertex */
.macro gsSPVertex verts, num, index
.ifdef F3DEX_GBI_2
.word (G_VTX << 24) | ((\num & 0xFF) << 12) | (((\index+\num) & 0x7F) << 1)
.word \verts
.else /* Fast3D and Fast3DEX */
.ifdef F3DEX_GBI
gsDma1p G_VTX, \verts, (\num)<<10|(16*(\num)-1), (2*\index)
.else /* Fast3D */
gsDma1p G_VTX, \verts, 16*\num, ((\num)-1)<<4|(\index)
.endif
.endif
.endm
/*
* gSPGeometryMode
* In Fast3DEX2 it is better to use this, as the RSP geometry mode
* is able to be set and cleared in a single command.
*/
.macro gsSPGeometryMode cc, ff, order
.ifdef F3DEX_GBI_2
.word (G_GEOMETRYMODE << 24) | ((~(\cc)) & 0x00FFFFFF)
.word \ff
.else
.if \order == 0
gsSPSetGeometryMode \ff
gsSPClearGeometryMode \cc
.else
gsSPClearGeometryMode \cc
gsSPSetGeometryMode \ff
.endif
.endif
.endm
/* gSPSetGeometryMode */
.macro gsSPSetGeometryMode, flags
.ifdef F3DEX_GBI_2
.word (G_GEOMETRYMODE << 24) | 0x00FFFFFF
.word \flags
.else /* Fast3D and Fast3DEX */
.word G_SETGEOMETRYMODE << 24
.word \flags
.endif
.endm
/* gSPClearGeometryMode */
.macro gsSPClearGeometryMode, flags
.ifdef F3DEX_GBI_2
.word (G_GEOMETRYMODE << 24) | ((~(\flags)) & 0x00FFFFFF)
.word 0
.else /* Fast3D and Fast3DEX */
.word G_CLEARGEOMETRYMODE << 24
.word \flags
.endif
.endm
/* gSPPerspNormalize */
.macro gsSPPerspNormalize, perspNorm
.ifndef F3D_OLD
gsMoveWd G_MW_PERSPNORM, 0, \perspNorm
.else
gsImmp1 G_RDPHALF_1, \perspNorm
.endif
.endm
/* gSPEndDisplayList */
.macro gsSPEndDisplayList
f3d_noparam G_ENDDL
.endm
/* gSPSetOtherMode */
.macro gsSPSetOtherMode cmd, sft, len, data
.ifdef F3DEX_GBI_2
.word ((\cmd & 0xFF) << 24) | ((32 - (\sft & 0xFF) - (\len & 0xFF)) << 8) | ((\len-1) & 0xFF)
.word \data
.else /* Fast3D and Fast3DEX2 */
.word ((\cmd & 0xFF) << 24) | ((\sft & 0xFF) << 8) | (\len & 0xFF)
.word \data
.endif
.endm
.macro gsSPTexture scaleS, scaleT, level, tile, enable
.ifdef F3DEX_GBI_2
.word (G_TEXTURE << 24) | ((\level & 0x7) << 11) | ((\tile & 0x7) << 8) | (\enable*2)
.word ((\scaleS & 0xFFFF) << 16) | (\scaleT & 0xFFFF)
.else /* Fast3D and Fast3DEX */
.word (G_TEXTURE << 24) | ((\level & 0x7) << 11) | ((\tile & 0x7) << 8) | \enable
.word ((\scaleS & 0xFFFF) << 16) | (\scaleT & 0xFFFF)
.endif
.endm
/* gSPSetRenderMode */
.macro gsDPSetRenderMode cycle1Mode, cycle2Mode
gsSPSetOtherMode G_SETOTHERMODE_L, G_MDSFT_RENDERMODE, 29, \cycle1Mode | \cycle2Mode
.endm
/* gDPSetTexturePersp */
.macro gsDPSetTexturePersp type
gsSPSetOtherMode G_SETOTHERMODE_H, G_MDSFT_TEXTPERSP, 1, \type
.endm
/* gDPSetCycleType */
.macro gsDPSetCycleType type
gsSPSetOtherMode G_SETOTHERMODE_H, G_MDSFT_CYCLETYPE, 2, \type
.endm
/* gDPSetTextureDetail */
.macro gsDPSetTextureDetail type
gsSPSetOtherMode G_SETOTHERMODE_H, G_MDSFT_TEXTDETAIL, 2, \type
.endm
/* gDPSetTextureLOD*/
.macro gsDPSetTextureLOD type
gsSPSetOtherMode G_SETOTHERMODE_H, G_MDSFT_TEXTLOD, 1, \type
.endm
/* gDPSetTextureTLUT */
.macro gsDPSetTextureLUT type
gsSPSetOtherMode G_SETOTHERMODE_H, G_MDSFT_TEXTLUT, 2, \type
.endm
/* gDPSetTextureFilter */
.macro gsDPSetTextureFilter type
gsSPSetOtherMode G_SETOTHERMODE_H, G_MDSFT_TEXTFILT, 2, \type
.endm
/* gDPSetTextureConvert */
.macro gsDPSetTextureConvert type
gsSPSetOtherMode G_SETOTHERMODE_H, G_MDSFT_TEXTCONV, 3, \type
.endm
/* gDPSetCombineKey */
.macro gsDPSetCombineKey type
gsSPSetOtherMode G_SETOTHERMODE_H, G_MDSFT_COMBKEY, 1, \type
.endm
/* gDPSetColorDither */
.macro gsDPSetColorDither mode
gsSPSetOtherMode G_SETOTHERMODE_H, G_MDSFT_RGBDITHER, 2, \mode
.endm
/* gsDPSetAlphaCompare */
.macro gsDPSetAlphaCompare type
gsSPSetOtherMode G_SETOTHERMODE_L, G_MDSFT_ALPHACOMPARE, 2, \type
.endm
/* gDPSetDepthSource */
.macro gsDPSetDepthSource src
gsSPSetOtherMode G_SETOTHERMODE_L, G_MDSFT_ZSRCSEL, 1, \src
.endm
/* gSPDisplayList */
.macro gsSPDisplayList dl
gsDma1p G_DL, \dl, 0, G_DL_PUSH
.endm
/* gSPBranchDisplayList */
.macro gsSPBranchList dl
gsDma1p G_DL, \dl, 0, G_DL_NOPUSH
.endm
/*
* gSP1Triangle
* Note: flag has no effect on this implementation of gSP1Triangle.
*/
.macro gsSP1Triangle v0, v1, v2, flag
.ifndef F3DEX_GBI_2
.word G_TRI1 << 24
.ifdef F3DEX_GBI /* Fast3DEX */
.word (\v0*2 << 16) | (\v1*2 << 8) | \v2*2
.else /* Fast3D */
.word (\v0*10 << 16) | (\v1*10 << 8) | \v2*10
.endif
.else /* Fast3DEX2 */
.byte G_TRI1, \v0*2, \v1*2, \v2*2
.word 0
.endif
.endm
/*
* gSP2Triangles
* Note: flag has no effect on this implementation of gSP2Triangles.
*/
.macro gsSP2Triangles v0, v1, v2, flag0, v3, v4, v5, flag1
.ifdef F3DEX_GBI_SHARED /* Fast3DEX and Fast3DEX2 have the same G_TRI2 syntax. */
.word (G_TRI2 << 24) | (\v0*2 << 16) | (\v1*2 << 8) | \v2*2
.word (0x00 << 24) | (\v3*2 << 16) | (\v4*2 << 8) | \v5*2
.else /* Backwards compatibility with Fast3D. */
gsSP1Triangle \v0, \v1, \v2, \flag0
gsSP1Triangle \v3, \v4, \v5, \flag1
.endif
.endm
/* gDPNoOp */
.macro gsDPNoOp
f3d_noparam G_NOOP
.endm
/* gSPTextureRectangle */
.macro gsSPTextureRectangle xl, yl, xh, yh, tile, s, t, dsdx, dtdy
.word (G_TEXRECT << 24) | (\xh << 12) | \yh
.word (\tile << 24) | (\xl << 12) | \yl
.ifdef F3D_OLD
.word (G_RDPHALF_2 << 24)
.else
.word (G_RDPHALF_1 << 24)
.endif
.word (\s << 16) | \t
.ifdef F3D_OLD
.word (G_RDPHALF_CONT << 24)
.else
.word (G_RDPHALF_2 << 24)
.endif
.word (\dsdx << 16) | \dtdy
.endm
/* gDPLoadSync */
.macro gsDPLoadSync
f3d_noparam G_RDPLOADSYNC
.endm
/* gDPPipeSync*/
.macro gsDPPipeSync
f3d_noparam G_RDPPIPESYNC
.endm
/* gDPFullSync*/
.macro gsDPFullSync
f3d_noparam G_RDPFULLSYNC
.endm
/* gDPLoadTLUTCmd */
.macro gsDPLoadTLUTCmd tile, count
.word G_LOADTLUT << 24
.word ((\tile & 0x7) << 24) | ((\count - 1) & 0x3FF) << 14
.endm
/* gDPTileSync */
.macro gsDPTileSync
f3d_noparam G_RDPTILESYNC
.endm
/* gDPSetTileSize */
.macro gsDPSetTileSize tile, uls, ult, lrs, lrt
.word (G_SETTILESIZE << 24) | ((\uls & 0x0FFF) << 12) | (\ult & 0x0FFF)
.word ((\tile & 0x7) << 24) | ((\lrs & 0x0FFF) << 12) | (\lrt & 0x0FFF)
.endm
/* gsDPLoadBlock */
.macro gsDPLoadBlock tile, uls, ult, lrs, dxt
.word (G_LOADBLOCK << 24) | ((\uls & 0x0FFF) << 12) | (\ult & 0x0FFF)
.word ((\tile & 0x7) << 24) | ((\lrs & 0x0FFF) << 12) | (\dxt & 0x0FFF)
.endm
/* gDPSetTile */
.macro gsDPSetTile fmt, siz, line, tmem, tile, palette, cmt, maskt, shiftt, cms, masks, shifts
.word (G_SETTILE << 24) | ((\fmt & 0x7) << 21) | ((\siz & 0x3) << 19) | ((\line & 0x1FF) << 9) | (\tmem & 0x1FF)
.word ((\tile & 0x7) << 24) | ((\palette & 0xF) << 20) | ((\cmt & 0x3) << 18) | ((\maskt & 0xF) << 14) | ((\shiftt & 0xF) << 10) | ((\cms & 0x3) << 8) | ((\masks & 0xF) << 4) | (\shifts & 0xF)
.endm
/* gDPFillRectangle */
.macro gsDPFillRectangle ulx, uly, lrx, lry
.word (G_FILLRECT << 24) | ((\lrx & 0x3FF) << 14) | ((\lry & 0x3FF) << 2)
.word ((\ulx & 0x3FF) << 14) | ((\uly & 0x3FF) << 2)
.endm
/* gDPSetFillColor */
.macro gsDPSetFillColor fillValue
.word G_SETFILLCOLOR << 24
.word \fillValue
.endm
/* gDPSetFogColor */
.macro gsDPSetFogColor r, g, b, a
sDPRGBColor G_SETFOGCOLOR, \r, \g, \b, \a
.endm
/* gDPSetBlendColor */
.macro gsDPSetBlendColor r, g, b, a
sDPRGBColor G_SETBLENDCOLOR, \r, \g, \b, \a
.endm
/* gDPSetPrimColor */
.macro gsDPSetPrimColor m, l, r, g, b, a
.word (G_SETPRIMCOLOR << 24) | ((\m & 0xFF) << 8) | (\l & 0xFF)
.word (\r << 24) | (\g << 16) | (\b << 8) | \a
.endm
/* gDPSetEnvColor */
.macro gsDPSetEnvColor r, g, b, a
sDPRGBColor G_SETENVCOLOR, \r, \g, \b, \a
.endm
/* gDPSetCombine */
.macro gsDPSetCombine muxs0, muxs1
.word (G_SETCOMBINE << 24) | (\muxs0 & 0x00FFFFFF)
.word \muxs1
.endm
/* gDPSetCombineMode */
.macro gsDPSetCombineModeLERP a0, b0, c0, d0, Aa0, Ab0, Ac0, Ad0, a1, b1, c1, d1, Aa1, Ab1, Ac1, Ad1
.word (G_SETCOMBINE << 24) | ((\a0 & 0xF) << 20) | ((\c0 & 0x1F) << 15) | ((\Aa0 & 0x7) << 12) | ((\Ac0 & 0x7) << 9) | ((\a1 & 0xF) << 5) | (\c1 & 0x1F)
.word ((\b0 & 0xF) << 28) | ((\b1 & 0xF) << 24) | ((\Aa1 & 0x7) << 21) | ((\Ac1 & 0x7) << 18) | ((\d0 & 0x7) << 15) | ((\Ab0 & 0x7) << 12) | ((\Ad0 & 0x7) << 9) | ((\d1 & 0x7) << 6) | ((\Ab1 & 0x7) << 3) | (\Ad1 & 0x7)
.endm
/* gDPSetCombineMode1Cycle */
.macro gsDPSetCombineModeLERP1Cycle a0, b0, c0, d0, Aa0, Ab0, Ac0, Ad0
gsDPSetCombineModeLERP \a0, \b0, \c0, \d0, \Aa0, \Ab0, \Ac0, \Ad0, \a0, \b0, \c0, \d0, \Aa0, \Ab0, \Ac0, \Ad0
.endm
/* gDPSetTextureImage */
.macro gsDPSetTextureImage fmt, size, width, segAddr
.word (G_SETTIMG << 24) | ((\fmt & 0x7) << 21) | ((\size & 0x3) << 19) | ((\width-1) & 0x0FFF)
.word \segAddr
.endm
/* gDPLoadTextureBlock */
/* Calculate gDPLoadBlock for 8, 16, and 32 bit textures */
.macro _calc_gsDPLoadBlockNot4b width, height, shift, incr, byteSize
.if (((\width * \byteSize) / 8) > 1) /* result of TXL2WORDS is greater than 1 */
gsDPLoadBlock G_TX_LOADTILE, 0, 0, (((\width * \height) + \incr) >> \shift) - 1, (((1 << G_TX_DXT_FRAC) + ((\width * \byteSize) / 8) - 1) / ((\width * \byteSize) / 8))
.else /* result of TXL2WORDS is 1 */
gsDPLoadBlock G_TX_LOADTILE, 0, 0, (((\width * \height) + \incr) >> \shift) - 1, (1 << G_TX_DXT_FRAC)
.endif
.endm
/* Calculate gDPLoadBlock for 4-bit textures */
.macro _calc_gsDPLoadBlock4b width, height
.if ((\width / 16) > 1) /* result of TXL2WORDS_4b is greater than 1 */
gsDPLoadBlock G_TX_LOADTILE, 0, 0, (((\width * \height) + 3) >> 2) - 1, (((1 << G_TX_DXT_FRAC) + (\width / 16) - 1) / (\width / 16))
.else /* result of TXL2WORDS_4b is 1 */
gsDPLoadBlock G_TX_LOADTILE, 0, 0, (((\width * \height) + 3) >> 2) - 1, (1 << G_TX_DXT_FRAC)
.endif
.endm
/* Calculate gDPLoadBlock using texture bit size, width, and height */
.macro _calc_gsDPLoadBlock siz, width, height
.if (\siz == G_IM_SIZ_4b)
_calc_gsDPLoadBlock4b \width, \height
.elseif (\siz == G_IM_SIZ_8b)
_calc_gsDPLoadBlockNot4b \width, \height, 1, 1, 1
.elseif (\siz == G_IM_SIZ_16b)
_calc_gsDPLoadBlockNot4b \width, \height, 0, 0, 2
.elseif (\siz == G_IM_SIZ_32b)
_calc_gsDPLoadBlockNot4b \width, \height, 0, 0, 4
.endif
.endm
/*
* gDPLoadTextureBlock is a macro that allows you to easily load a texture in the f3d family of ucodes
* Parameters:
* timg = label to the texture data
* fmt = image format (G_IM_FMT_RGBA, G_IM_FMT_CI, G_IM_FMT_IA, G_IM_FMT_I, or G_IM_FMT_YUV)
* siz = bits per pixel (G_IM_SIZ_4b, G_IM_SIZ_8b, G_IM_SIZ_16b, or G_IM_SIZ_32b)
* width = width of the texture in pixels
* height = height of the texture in pixels
* pal = palette id to use if using G_IM_FMT_CI, otherwise it should be 0.
* cms = Clamp & Mirror flags for the S axis
* cmt = Clamp & Mirror flags for the T axis
* masks = Sets how much of the S axis is shown before clamping. This is usually just log2(width).
* maskt = Sets how much of the T axis is shown before clamping. This is usually just log2(height).
* shifts = Sets the amount to shift S axis values after perspective division. This is usually G_TX_NOLOD.
* shiftt = Sets the amount to shift T axis values after perspective division. This is usually G_TX_NOLOD.
*/
.macro gsDPLoadTextureBlock timg, fmt, siz, width, height, pal, cms, cmt, masks, maskt, shifts, shiftt
.if (\siz == G_IM_SIZ_32b)
gsDPSetTextureImage \fmt, \siz, 1, \timg
gsDPSetTile \fmt, \siz, 0, 0, G_TX_LOADTILE, 0, \cmt, \maskt, \shiftt, \cms, \masks, \shifts
.else
gsDPSetTextureImage \fmt, G_IM_SIZ_16b, 1, \timg
gsDPSetTile \fmt, G_IM_SIZ_16b, 0, 0, G_TX_LOADTILE, 0, \cmt, \maskt, \shiftt, \cms, \masks, \shifts
.endif
gsDPLoadSync
_calc_gsDPLoadBlock \siz, \width, \height
gsDPPipeSync
.if (\siz == G_IM_SIZ_4b)
gsDPSetTile \fmt, \siz, (7 >> 3), 0, G_TX_RENDERTILE, \pal, \cmt, \maskt, \shiftt, \cms, \masks, \shifts
.elseif (\siz == G_IM_SIZ_8b)
gsDPSetTile \fmt, \siz, ((\width + 7) >> 3), 0, G_TX_RENDERTILE, \pal, \cmt, \maskt, \shiftt, \cms, \masks, \shifts
.else
gsDPSetTile \fmt, \siz, (((\width * 2) + 7) >> 3), 0, G_TX_RENDERTILE, \pal, \cmt, \maskt, \shiftt, \cms, \masks, \shifts
.endif
gsDPSetTileSize G_TX_RENDERTILE, 0, 0, ((\width - 1) << G_TEXTURE_IMAGE_FRAC), ((\height - 1) << G_TEXTURE_IMAGE_FRAC)
.endm
/*
* gDPLoadTLUT_pal16, loads 16 colors into the TLUT
* Parameters:
* pal = palette number to use.
* timg_pal = label to palette data
*/
.macro gsDPLoadTLUT_pal16 pal, timg_pal
gsDPSetTextureImage G_IM_FMT_RGBA, G_IM_SIZ_16b, 1, \timg_pal
gsDPTileSync
gsDPSetTile 0, 0, 0, (256+(((\pal)&0xf)*16)), G_TX_LOADTILE, 0, 0, 0, 0, 0, 0, 0
gsDPLoadSync
gsDPLoadTLUTCmd G_TX_LOADTILE, 16
gsDPPipeSync
.endm
/*
* gDPLoadTLUT_pal256, loads 256 colors into the TLUT
* Parameters:
* timg_pal = label to palette data
*/
.macro gsDPLoadTLUT_pal256 timg_pal
gsDPSetTextureImage G_IM_FMT_RGBA, G_IM_SIZ_16b, 1, \timg_pal
gsDPTileSync
gsDPSetTile 0, 0, 0, 256, G_TX_LOADTILE, 0, 0, 0, 0, 0, 0, 0
gsDPLoadSync
gsDPLoadTLUTCmd G_TX_LOADTILE, 256
gsDPPipeSync
.endm
/*
* gDPLoadTextureBlock_4b is a macro that allows you to easily load a 4-bit texture in the Fast3D family of ucodes.
* Parameters:
* timg = label to the texture data
* fmt = image format (G_IM_FMT_RGBA, G_IM_FMT_CI, G_IM_FMT_IA, G_IM_FMT_I, or G_IM_FMT_YUV)
* width = width of the texture in pixels
* height = height of the texture in pixels
* pal = palette id to use if using G_IM_FMT_CI, otherwise it should be 0.
* cms = Clamp & Mirror flags for the S axis
* cmt = Clamp & Mirror flags for the T axis
* masks = Sets how much of the S axis is shown before clamping. This is usually just log2(width).
* maskt = Sets how much of the T axis is shown before clamping. This is usually just log2(height).
* shifts = Sets the amount to shift S axis values after perspective division. This is usually G_TX_NOLOD.
* shiftt = Sets the amount to shift T axis values after perspective division. This is usually G_TX_NOLOD.
*/
.macro gsDPLoadTextureBlock_4b timg, fmt, width, height, pal, cms, cmt, masks, maskt, shifts, shiftt
gsDPSetTextureImage \fmt, G_IM_SIZ_16b, 1, \timg
gsDPSetTile \fmt, G_IM_SIZ_16b, 0, 0, G_TX_LOADTILE, 0, \cmt, \maskt, \shiftt, \cms, \masks, \shifts
gsDPLoadSync
_calc_gsDPLoadBlock4b \width, \height
gsDPPipeSync
gsDPSetTile \fmt, G_IM_SIZ_4b, ((((\width) >> 1) + 7) >> 3), 0, G_TX_RENDERTILE, \pal, \cmt, \maskt, \shiftt, \cms, \masks, \shifts
gsDPSetTileSize G_TX_RENDERTILE, 0, 0, ((\width) - 1) << G_TEXTURE_IMAGE_FRAC, ((\height) - 1) << G_TEXTURE_IMAGE_FRAC
.endm
/*
* gSPFogFactor
* Parameters:
* fm = z multiplier
* fo = z offset
*
* FOG FORMULA: alpha(fog) = (eyespace z) * fm + fo (CLAMPED 0 to 255)
* note: (eyespace z) ranges [-1, 1]
*/
.macro gsSPFogFactor fm, fo
gsMoveWd G_MW_FOG, G_MWO_FOG, ((\fm & 0xFFFF) << 16) | (\fo & 0xFFFF)
.endm
/*
* gSPFogPosition
* Parameters:
* min = Place where fog starts (0 at the near plane, and 1000 at the far plane)
* max = Place where fog saturates (0 at the near plane, and 1000 at the far plane)
*
* This macro will throw an error if min or max is outside the range [0, 1000]
*
* Note: The min can be larger than max, as that just makes objects fade when they
* get closer to the camera.
*/
.macro gsSPFogPosition min, max
.if (\min >= 0 && \min <= 1000 && \max >= 0 && \max <= 1000)
gsMoveWd G_MW_FOG, G_MWO_FOG, (((128000 / (\max - \min)) & 0xFFFF) << 16) | ((((500 - \min) * 256) / (\max - \min)) & 0xFFFF)
.elseif \min < 0 || \min > 1000
.error "[gsSPFogPosition]: min should be in the range [0, 1000]"
.elseif \max < 0 || \max > 1000
.error "[gsSPFogPosition]: max should be in the range [0, 1000]"
.endif
.endm
src/include/PR/gbi_old.h
-1612
View File
File diff suppressed because it is too large Load Diff
src/include/PR/gs2dex.h
-392
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@@ -1,392 +0,0 @@
/*---------------------------------------------------------------------
Copyright (C) 1997, Nintendo.
File gs2dex.h
Coded by Yoshitaka Yasumoto. Jul 31, 1997.
Modified by
Comments Header file for S2DEX ucode.
$Id: gs2dex.h,v 1.21 1998/05/28 00:14:49 has Exp $
---------------------------------------------------------------------*/
#ifndef _GS2DEX_H_
#define _GS2DEX_H_
#ifdef _LANGUAGE_C_PLUS_PLUS
extern "C" {
#endif
#include <PR/ultratypes.h>
/*===========================================================================*
* Macro
*===========================================================================*/
#define GS_CALC_DXT(line) (((1<< G_TX_DXT_FRAC)-1)/(line)+1)
#define GS_PIX2TMEM(pix, siz) ((pix)>>(4-(siz)))
#define GS_PIX2DXT(pix, siz) GS_CALC_DXT(GS_PIX2TMEM((pix), (siz)))
/*===========================================================================*
* Data structures for S2DEX microcode
*===========================================================================*/
/*---------------------------------------------------------------------------*
* Background
*---------------------------------------------------------------------------*/
#define G_BGLT_LOADBLOCK 0x0033
#define G_BGLT_LOADTILE 0xfff4
#define G_BG_FLAG_FLIPS 0x01
#define G_BG_FLAG_FLIPT 0x10
/* Non scalable background plane */
typedef struct {
u16 imageX; /* x-coordinate of upper-left position of texture (u10.5) */
u16 imageW; /* width of the texture (u10.2) */
s16 frameX; /* upper-left position of transferred frame (s10.2) */
u16 frameW; /* width of transferred frame (u10.2) */
u16 imageY; /* y-coordinate of upper-left position of texture (u10.5) */
u16 imageH; /* height of the texture (u10.2) */
s16 frameY; /* upper-left position of transferred frame (s10.2) */
u16 frameH; /* height of transferred frame (u10.2) */
u64 *imagePtr; /* texture source address on DRAM */
u16 imageLoad; /* which to use, LoadBlock or LoadTile */
u8 imageFmt; /* format of texel - G_IM_FMT_* */
u8 imageSiz; /* size of texel - G_IM_SIZ_* */
u16 imagePal; /* pallet number */
u16 imageFlip; /* right & left image inversion (Inverted by G_BG_FLAG_FLIPS) */
/* The following is set in the initialization routine guS2DInitBg(). There is no need for the user to set it. */
u16 tmemW; /* TMEM width and Word size of frame 1 line.
At LoadBlock, GS_PIX2TMEM(imageW/4,imageSiz)
At LoadTile GS_PIX2TMEM(frameW/4,imageSiz)+1 */
u16 tmemH; /* height of TMEM loadable at a time (s13.2) 4 times value
When the normal texture, 512/tmemW*4
When the CI texture, 256/tmemW*4 */
u16 tmemLoadSH; /* SH value
At LoadBlock, tmemSize/2-1
At LoadTile, tmemW*16-1 */
u16 tmemLoadTH; /* TH value or Stride value
At LoadBlock, GS_CALC_DXT(tmemW)
At LoadTile, tmemH-1 */
u16 tmemSizeW; /* skip value of imagePtr for image 1-line
At LoadBlock, tmemW*2
At LoadTile, GS_PIX2TMEM(imageW/4,imageSiz)*2 */
u16 tmemSize; /* skip value of imagePtr for 1-loading
= tmemSizeW*tmemH */
} uObjBg_t; /* 40 bytes */
/* Scalable background plane */
typedef struct {
u16 imageX; /* x-coordinate of upper-left position of texture (u10.5) */
u16 imageW; /* width of texture (u10.2) */
s16 frameX; /* upper-left position of transferred frame (s10.2) */
u16 frameW; /* width of transferred frame (u10.2) */
u16 imageY; /* y-coordinate of upper-left position of texture (u10.5) */
u16 imageH; /* height of texture (u10.2) */
s16 frameY; /* upper-left position of transferred frame (s10.2) */
u16 frameH; /* height of transferred frame (u10.2) */
u64 *imagePtr; /* texture source address on DRAM */
u16 imageLoad; /* Which to use, LoadBlock or LoadTile? */
u8 imageFmt; /* format of texel - G_IM_FMT_* */
u8 imageSiz; /* size of texel - G_IM_SIZ_* */
u16 imagePal; /* pallet number */
u16 imageFlip; /* right & left image inversion (Inverted by G_BG_FLAG_FLIPS) */
u16 scaleW; /* scale value of X-direction (u5.10) */
u16 scaleH; /* scale value of Y-direction (u5.10) */
s32 imageYorig; /* start point of drawing on image (s20.5) */
u8 padding[4];
} uObjScaleBg_t; /* 40 bytes */
typedef union {
uObjBg_t b;
uObjScaleBg_t s;
long long int force_structure_alignment;
} uObjBg;
/*---------------------------------------------------------------------------*
* 2D Objects
*---------------------------------------------------------------------------*/
#define G_OBJ_FLAG_FLIPS 1<<0 /* inversion to S-direction */
#define G_OBJ_FLAG_FLIPT 1<<4 /* nversion to T-direction */
typedef struct {
s16 objX; /* s10.2 OBJ x-coordinate of upper-left end */
u16 scaleW; /* u5.10 Scaling of u5.10 width direction */
u16 imageW; /* u10.5 width of u10.5 texture (length of S-direction) */
u16 paddingX; /* Unused - Always 0 */
s16 objY; /* s10.2 OBJ y-coordinate of s10.2 OBJ upper-left end */
u16 scaleH; /* u5.10 Scaling of u5.10 height direction */
u16 imageH; /* u10.5 height of u10.5 texture (length of T-direction) */
u16 paddingY; /* Unused - Always 0 */
u16 imageStride; /* folding width of texel (In units of 64bit word) */
u16 imageAdrs; /* texture header position in TMEM (In units of 64bit word) */
u8 imageFmt; /* format of texel - G_IM_FMT_* */
u8 imageSiz; /* size of texel - G_IM_SIZ_* */
u8 imagePal; /* pallet number (0-7) */
u8 imageFlags; /* The display flag - G_OBJ_FLAG_FLIP* */
} uObjSprite_t; /* 24 bytes */
typedef union {
uObjSprite_t s;
long long int force_structure_alignment;
} uObjSprite;
/*---------------------------------------------------------------------------*
* 2D Matrix
*---------------------------------------------------------------------------*/
typedef struct {
s32 A, B, C, D; /* s15.16 */
s16 X, Y; /* s10.2 */
u16 BaseScaleX; /* u5.10 */
u16 BaseScaleY; /* u5.10 */
} uObjMtx_t; /* 24 bytes */
typedef union {
uObjMtx_t m;
long long int force_structure_alignment;
} uObjMtx;
typedef struct {
s16 X, Y; /* s10.2 */
u16 BaseScaleX; /* u5.10 */
u16 BaseScaleY; /* u5.10 */
} uObjSubMtx_t; /* 8 bytes */
typedef union {
uObjSubMtx_t m;
long long int force_structure_alignment;
} uObjSubMtx;
/*---------------------------------------------------------------------------*
* Loading into TMEM
*---------------------------------------------------------------------------*/
#define G_OBJLT_TXTRBLOCK 0x00001033
#define G_OBJLT_TXTRTILE 0x00fc1034
#define G_OBJLT_TLUT 0x00000030
#define GS_TB_TSIZE(pix,siz) (GS_PIX2TMEM((pix),(siz))-1)
#define GS_TB_TLINE(pix,siz) (GS_CALC_DXT(GS_PIX2TMEM((pix),(siz))))
typedef struct {
u32 type; /* G_OBJLT_TXTRBLOCK divided into types */
u64 *image; /* texture source address on DRAM */
u16 tmem; /* loaded TMEM word address (8byteWORD) */
u16 tsize; /* Texture size, Specified by macro GS_TB_TSIZE() */
u16 tline; /* width of Texture 1-line, Specified by macro GS_TB_TLINE() */
u16 sid; /* STATE ID Multipled by 4 (Either one of 0, 4, 8 and 12) */
u32 flag; /* STATE flag */
u32 mask; /* STATE mask */
} uObjTxtrBlock_t; /* 24 bytes */
#define GS_TT_TWIDTH(pix,siz) ((GS_PIX2TMEM((pix), (siz))<<2)-1)
#define GS_TT_THEIGHT(pix,siz) (((pix)<<2)-1)
typedef struct {
u32 type; /* G_OBJLT_TXTRTILE divided into types */
u64 *image; /* texture source address on DRAM */
u16 tmem; /* loaded TMEM word address (8byteWORD)*/
u16 twidth; /* width of Texture (Specified by macro GS_TT_TWIDTH()) */
u16 theight; /* height of Texture (Specified by macro GS_TT_THEIGHT()) */
u16 sid; /* STATE ID Multipled by 4 (Either one of 0, 4, 8 and 12) */
u32 flag; /* STATE flag */
u32 mask; /* STATE mask */
} uObjTxtrTile_t; /* 24 bytes */
#define GS_PAL_HEAD(head) ((head)+256)
#define GS_PAL_NUM(num) ((num)-1)
typedef struct {
u32 type; /* G_OBJLT_TLUT divided into types */
u64 *image; /* texture source address on DRAM */
u16 phead; /* pallet number of load header (Between 256 and 511) */
u16 pnum; /* loading pallet number -1 */
u16 zero; /* Assign 0 all the time */
u16 sid; /* STATE ID Multipled by 4 (Either one of 0, 4, 8 and 12)*/
u32 flag; /* STATE flag */
u32 mask; /* STATE mask */
} uObjTxtrTLUT_t; /* 24 bytes */
typedef union {
uObjTxtrBlock_t block;
uObjTxtrTile_t tile;
uObjTxtrTLUT_t tlut;
long long int force_structure_alignment;
} uObjTxtr;
/*---------------------------------------------------------------------------*
* Loading into TMEM & 2D Objects
*---------------------------------------------------------------------------*/
typedef struct {
uObjTxtr txtr;
uObjSprite sprite;
} uObjTxSprite; /* 48 bytes */
/*===========================================================================*
* GBI Commands for S2DEX microcode
*===========================================================================*/
/* GBI Header */
#ifdef F3DEX_GBI_2
#define G_OBJ_RECTANGLE_R 0xda
#define G_OBJ_MOVEMEM 0xdc
#define G_RDPHALF_0 0xe4
#define G_OBJ_RECTANGLE 0x01
#define G_OBJ_SPRITE 0x02
#define G_SELECT_DL 0x04
#define G_OBJ_LOADTXTR 0x05
#define G_OBJ_LDTX_SPRITE 0x06
#define G_OBJ_LDTX_RECT 0x07
#define G_OBJ_LDTX_RECT_R 0x08
#define G_BG_1CYC 0x09
#define G_BG_COPY 0x0a
#define G_OBJ_RENDERMODE 0x0b
#else
#define G_BG_1CYC 0x01
#define G_BG_COPY 0x02
#define G_OBJ_RECTANGLE 0x03
#define G_OBJ_SPRITE 0x04
#define G_OBJ_MOVEMEM 0x05
#define G_SELECT_DL 0xb0
#define G_OBJ_RENDERMODE 0xb1
#define G_OBJ_RECTANGLE_R 0xb2
#define G_OBJ_LOADTXTR 0xc1
#define G_OBJ_LDTX_SPRITE 0xc2
#define G_OBJ_LDTX_RECT 0xc3
#define G_OBJ_LDTX_RECT_R 0xc4
#define G_RDPHALF_0 0xe4
#endif
/*---------------------------------------------------------------------------*
* Background wrapped screen
*---------------------------------------------------------------------------*/
#define gSPBgRectangle(pkt, m, mptr) gDma0p((pkt),(m),(mptr),0)
#define gsSPBgRectangle(m, mptr) gsDma0p( (m),(mptr),0)
#define gSPBgRectCopy(pkt, mptr) gSPBgRectangle((pkt), G_BG_COPY, (mptr))
#define gsSPBgRectCopy(mptr) gsSPBgRectangle( G_BG_COPY, (mptr))
#define gSPBgRect1Cyc(pkt, mptr) gSPBgRectangle((pkt), G_BG_1CYC, (mptr))
#define gsSPBgRect1Cyc(mptr) gsSPBgRectangle( G_BG_1CYC, (mptr))
/*---------------------------------------------------------------------------*
* 2D Objects
*---------------------------------------------------------------------------*/
#define gSPObjSprite(pkt, mptr) gDma0p((pkt),G_OBJ_SPRITE, (mptr),0)
#define gsSPObjSprite(mptr) gsDma0p( G_OBJ_SPRITE, (mptr),0)
#define gSPObjRectangle(pkt, mptr) gDma0p((pkt),G_OBJ_RECTANGLE, (mptr),0)
#define gsSPObjRectangle(mptr) gsDma0p( G_OBJ_RECTANGLE, (mptr),0)
#define gSPObjRectangleR(pkt, mptr) gDma0p((pkt),G_OBJ_RECTANGLE_R,(mptr),0)
#define gsSPObjRectangleR(mptr) gsDma0p( G_OBJ_RECTANGLE_R,(mptr),0)
/*---------------------------------------------------------------------------*
* 2D Matrix
*---------------------------------------------------------------------------*/
#define gSPObjMatrix(pkt, mptr) gDma1p((pkt),G_OBJ_MOVEMEM,(mptr),0,23)
#define gsSPObjMatrix(mptr) gsDma1p( G_OBJ_MOVEMEM,(mptr),0,23)
#define gSPObjSubMatrix(pkt, mptr) gDma1p((pkt),G_OBJ_MOVEMEM,(mptr),2, 7)
#define gsSPObjSubMatrix(mptr) gsDma1p( G_OBJ_MOVEMEM,(mptr),2, 7)
/*---------------------------------------------------------------------------*
* Loading into TMEM
*---------------------------------------------------------------------------*/
#define gSPObjLoadTxtr(pkt, tptr) gDma0p((pkt),G_OBJ_LOADTXTR, (tptr),23)
#define gsSPObjLoadTxtr(tptr) gsDma0p( G_OBJ_LOADTXTR, (tptr),23)
#define gSPObjLoadTxSprite(pkt, tptr) gDma0p((pkt),G_OBJ_LDTX_SPRITE,(tptr),47)
#define gsSPObjLoadTxSprite(tptr) gsDma0p( G_OBJ_LDTX_SPRITE,(tptr),47)
#define gSPObjLoadTxRect(pkt, tptr) gDma0p((pkt),G_OBJ_LDTX_RECT, (tptr),47)
#define gsSPObjLoadTxRect(tptr) gsDma0p( G_OBJ_LDTX_RECT, (tptr),47)
#define gSPObjLoadTxRectR(pkt, tptr) gDma0p((pkt),G_OBJ_LDTX_RECT_R,(tptr),47)
#define gsSPObjLoadTxRectR(tptr) gsDma0p( G_OBJ_LDTX_RECT_R,(tptr),47)
/*---------------------------------------------------------------------------*
* Select Display List
*---------------------------------------------------------------------------*/
#define gSPSelectDL(pkt, mptr, sid, flag, mask) \
{ gDma1p((pkt), G_RDPHALF_0, (flag), (u32)(mptr) & 0xffff, (sid)); \
gDma1p((pkt), G_SELECT_DL, (mask), (u32)(mptr) >> 16, G_DL_PUSH); }
#define gsSPSelectDL(mptr, sid, flag, mask) \
{ gsDma1p(G_RDPHALF_0, (flag), (u32)(mptr) & 0xffff, (sid)); \
gsDma1p(G_SELECT_DL, (mask), (u32)(mptr) >> 16, G_DL_PUSH); }
#define gSPSelectBranchDL(pkt, mptr, sid, flag, mask) \
{ gDma1p((pkt), G_RDPHALF_0, (flag), (u32)(mptr) & 0xffff, (sid)); \
gDma1p((pkt), G_SELECT_DL, (mask), (u32)(mptr) >> 16, G_DL_NOPUSH); }
#define gsSPSelectBranchDL(mptr, sid, flag, mask) \
{ gsDma1p(G_RDPHALF_0, (flag), (u32)(mptr) & 0xffff, (sid)); \
gsDma1p(G_SELECT_DL, (mask), (u32)(mptr) >> 16, G_DL_NOPUSH); }
/*---------------------------------------------------------------------------*
* Set general status
*---------------------------------------------------------------------------*/
#define G_MW_GENSTAT 0x08 /* Note that it is the same value of G_MW_FOG */
#define gSPSetStatus(pkt, sid, val) \
gMoveWd((pkt), G_MW_GENSTAT, (sid), (val))
#define gsSPSetStatus(sid, val) \
gsMoveWd( G_MW_GENSTAT, (sid), (val))
/*---------------------------------------------------------------------------*
* Set Object Render Mode
*---------------------------------------------------------------------------*/
#define G_OBJRM_NOTXCLAMP 0x01
#define G_OBJRM_XLU 0x02 /* Ignored */
#define G_OBJRM_ANTIALIAS 0x04 /* Ignored */
#define G_OBJRM_BILERP 0x08
#define G_OBJRM_SHRINKSIZE_1 0x10
#define G_OBJRM_SHRINKSIZE_2 0x20
#define G_OBJRM_WIDEN 0x40
#define gSPObjRenderMode(pkt, mode) gImmp1((pkt),G_OBJ_RENDERMODE,(mode))
#define gsSPObjRenderMode(mode) gsImmp1( G_OBJ_RENDERMODE,(mode))
/*===========================================================================*
* Render Mode Macro
*===========================================================================*/
#define RM_RA_SPRITE(clk) \
AA_EN | CVG_DST_CLAMP | \
CVG_X_ALPHA | ALPHA_CVG_SEL | ZMODE_OPA | TEX_EDGE | \
GBL_c##clk(G_BL_CLR_IN, G_BL_A_IN, G_BL_CLR_MEM, G_BL_1MA)
#define G_RM_SPRITE G_RM_OPA_SURF
#define G_RM_SPRITE2 G_RM_OPA_SURF2
#define G_RM_RA_SPRITE RM_RA_SPRITE(1)
#define G_RM_RA_SPRITE2 RM_RA_SPRITE(2)
#define G_RM_AA_SPRITE G_RM_AA_TEX_TERR
#define G_RM_AA_SPRITE2 G_RM_AA_TEX_TERR2
#define G_RM_XLU_SPRITE G_RM_XLU_SURF
#define G_RM_XLU_SPRITE2 G_RM_XLU_SURF2
#define G_RM_AA_XLU_SPRITE G_RM_AA_XLU_SURF
#define G_RM_AA_XLU_SPRITE2 G_RM_AA_XLU_SURF2
/*===========================================================================*
* External functions
*===========================================================================*/
extern u64 gspS2DEX_fifoTextStart[], gspS2DEX_fifoTextEnd[];
extern u64 gspS2DEX_fifoDataStart[], gspS2DEX_fifoDataEnd[];
extern u64 gspS2DEX_fifo_dTextStart[], gspS2DEX_fifo_dTextEnd[];
extern u64 gspS2DEX_fifo_dDataStart[], gspS2DEX_fifo_dDataEnd[];
extern u64 gspS2DEX2_fifoTextStart[], gspS2DEX2_fifoTextEnd[];
extern u64 gspS2DEX2_fifoDataStart[], gspS2DEX2_fifoDataEnd[];
extern u64 gspS2DEX2_xbusTextStart[], gspS2DEX2_xbusTextEnd[];
extern u64 gspS2DEX2_xbusDataStart[], gspS2DEX2_xbusDataEnd[];
extern void guS2DInitBg(uObjBg *);
#ifdef F3DEX_GBI_2
# define guS2DEmuBgRect1Cyc guS2D2EmuBgRect1Cyc /*Wrapper*/
# define guS2DEmuSetScissor guS2D2EmuSetScissor /*Wrapper*/
extern void guS2D2EmuSetScissor(u32, u32, u32, u32, u8);
extern void guS2D2EmuBgRect1Cyc(Gfx **, uObjBg *);
#else
extern void guS2DEmuSetScissor(u32, u32, u32, u32, u8);
extern void guS2DEmuBgRect1Cyc(Gfx **, uObjBg *);
#endif
#ifdef _LANGUAGE_C_PLUS_PLUS
}
#endif
#endif /* _GS2DEX_H_ */
/*======== End of gs2dex.h ========*/
src/include/PR/gu.h
-41
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#ifndef _ULTRA64_GU_H_
#define _ULTRA64_GU_H_
#define GU_PI 3.1415926
#define FTOFIX32(x) (long)((x) * (float)0x00010000)
#define FIX32TOF(x) ((float)(x) * (1.0f / (float)0x00010000))
#define FTOFRAC8(x) ((int) MIN(((x) * (128.0f)), 127.0f) & 0xff)
/* Functions */
void guPerspectiveF(float mf[4][4], u16 *perspNorm, float fovy, float aspect,
float near, float far, float scale);
void guPerspective(Mtx *m, u16 *perspNorm, float fovy, float aspect, float near,
float far, float scale);
void guOrtho(Mtx *m, float left, float right, float bottom, float top,
float near, float far, float scale);
void guTranslate(Mtx *m, float x, float y, float z);
void guRotate(Mtx *m, float a, float x, float y, float z);
void guScale(Mtx *m, float x, float y, float z);
void guMtxF2L(float mf[4][4], Mtx *m);
void guMtxIdent(Mtx *m);
void guMtxIdentF(float mf[4][4]);
void guMtxL2F(float mf[4][4], Mtx *m);
void guNormalize(float *, float *, float *);
void guAlignF(float mf[4][4], float a, float x, float y, float z);
void guRotateF(float mf[4][4], float a, float x, float y, float z);
void guFrustumF(float mf[4][4], float l, float r, float b, float t, float n, float f, float scale);
void guLookAt(Mtx *m, float xEye, float yEye, float zEye,
float xAt, float yAt, float zAt,
float xUp, float yUp, float zUp);
signed short coss(unsigned short x);
signed short sins(unsigned short x);
/* Used only in Fast3DEX2 */
void guLookAtReflect (Mtx *m, LookAt *l, float xEye, float yEye, float zEye,
float xAt, float yAt, float zAt,
float xUp, float yUp, float zUp);
#endif
src/include/PR/libaudio.h
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#ifndef __LIB_AUDIO__
#define __LIB_AUDIO__
#ifdef _LANGUAGE_C_PLUS_PLUS
extern "C" {
#endif
#include <PR/ultratypes.h>
#include <PR/mbi.h>
/***********************************************************************
* misc defines
***********************************************************************/
#ifndef _EMULATOR
# ifdef AUD_PROFILE
#define PROFILE_AUD(num, cnt, max, min) \
{ \
u32 currCnt = osGetCount(); \
currCnt -= lastCnt[cnt_index]; \
cnt_index--; \
cnt += currCnt; \
num++; \
\
if ( currCnt > max ) max = currCnt; \
if ( currCnt < min ) min = currCnt; \
}
# endif /* AUD_PROFILE */
#endif /* EMULATOR */
#ifndef NULL
#define NULL 0
#endif
#define AL_FX_BUFFER_SIZE 8192
#define AL_FRAME_INIT -1
#if PAL
#define AL_USEC_PER_FRAME 20000
#else
#define AL_USEC_PER_FRAME 16000
#endif
#define AL_MAX_PRIORITY 127
#define AL_GAIN_CHANGE_TIME 1000
typedef s32 ALMicroTime;
typedef u8 ALPan;
#define AL_PAN_CENTER 64
#define AL_PAN_LEFT 0
#define AL_PAN_RIGHT 127
#define AL_VOL_FULL 127
#define AL_KEY_MIN 0
#define AL_KEY_MAX 127
#define AL_DEFAULT_FXMIX 0
#define AL_SUSTAIN 63
/***********************************************************************
* Error handling
***********************************************************************/
#ifdef _DEBUG
#define ALFailIf(condition, error) \
if (condition) { \
__osError(error, 0); \
return; }
#else
#define ALFailIf(condition, error) \
if (condition) { \
return; }
#endif
#ifdef _DEBUG
#define ALFlagFailIf(condition, flag, error) \
if (condition) { \
if(flag) __osError(error, 0); \
return; }
#else
#define ALFlagFailIf(condition, flag, error) \
if (condition) { \
return; }
#endif
/***********************************************************************
* Audio Library global routines
***********************************************************************/
typedef struct ALLink_s {
struct ALLink_s *next;
struct ALLink_s *prev;
} ALLink;
void alUnlink(ALLink *element);
void alLink(ALLink *element, ALLink *after);
typedef s32 (*ALDMAproc)(s32 addr, s32 len, void *state);
typedef ALDMAproc (*ALDMANew)(void *state);
void alCopy(void *src, void *dest, s32 len);
typedef struct {
u8 *base;
u8 *cur;
s32 len;
s32 count;
} ALHeap;
#define AL_HEAP_DEBUG 1
#define AL_HEAP_MAGIC 0x20736a73
#define AL_HEAP_INIT 0
void alHeapInit(ALHeap *hp, u8 *base, s32 len);
void *alHeapDBAlloc(u8 *file, s32 line, ALHeap *hp, s32 num, s32 size);
s32 alHeapCheck(ALHeap *hp);
#ifdef _DEBUG
#define alHeapAlloc(hp, elem ,size) alHeapDBAlloc((u8 *) __FILE__,__LINE__,(hp),(elem),(size))
#else
#define alHeapAlloc(hp, elem ,size) alHeapDBAlloc(0, 0,(hp),(elem),(size))
#endif
/***********************************************************************
* FX Stuff
***********************************************************************/
#define AL_FX_NONE 0
#define AL_FX_SMALLROOM 1
#define AL_FX_BIGROOM 2
#define AL_FX_CHORUS 3
#define AL_FX_FLANGE 4
#define AL_FX_ECHO 5
#define AL_FX_CUSTOM 6
typedef u8 ALFxId;
typedef void *ALFxRef;
/***********************************************************************
* data structures for sound banks
***********************************************************************/
#define AL_BANK_VERSION 0x4231 /* 'B1' */
/* Possible wavetable types */
enum {AL_ADPCM_WAVE = 0,
AL_RAW16_WAVE};
typedef struct {
s32 order;
s32 npredictors;
s16 book[1]; /* Actually variable size. Must be 8-byte aligned */
} ALADPCMBook;
typedef struct {
u32 start;
u32 end;
u32 count;
ADPCM_STATE state;
} ALADPCMloop;
typedef struct {
u32 start;
u32 end;
u32 count;
} ALRawLoop;
typedef struct {
ALMicroTime attackTime;
ALMicroTime decayTime;
ALMicroTime releaseTime;
u8 attackVolume;
u8 decayVolume;
} ALEnvelope;
typedef struct {
u8 velocityMin;
u8 velocityMax;
u8 keyMin;
u8 keyMax;
u8 keyBase;
s8 detune;
} ALKeyMap;
typedef struct {
ALADPCMloop *loop;
ALADPCMBook *book;
} ALADPCMWaveInfo;
typedef struct {
ALRawLoop *loop;
} ALRAWWaveInfo;
typedef struct ALWaveTable_s {
u8 *base; /* ptr to start of wave data */
s32 len; /* length of data in bytes */
u8 type; /* compression type */
u8 flags; /* offset/address flags */
union {
ALADPCMWaveInfo adpcmWave;
ALRAWWaveInfo rawWave;
} waveInfo;
} ALWaveTable;
typedef struct ALSound_s {
ALEnvelope *envelope;
ALKeyMap *keyMap;
ALWaveTable *wavetable; /* offset to wavetable struct */
ALPan samplePan;
u8 sampleVolume;
u8 flags;
} ALSound;
typedef struct {
u8 volume; /* overall volume for this instrument */
ALPan pan; /* 0 = hard left, 127 = hard right */
u8 priority; /* voice priority for this instrument */
u8 flags;
u8 tremType; /* the type of tremelo osc. to use */
u8 tremRate; /* the rate of the tremelo osc. */
u8 tremDepth; /* the depth of the tremelo osc */
u8 tremDelay; /* the delay for the tremelo osc */
u8 vibType; /* the type of tremelo osc. to use */
u8 vibRate; /* the rate of the tremelo osc. */
u8 vibDepth; /* the depth of the tremelo osc */
u8 vibDelay; /* the delay for the tremelo osc */
s16 bendRange; /* pitch bend range in cents */
s16 soundCount; /* number of sounds in this array */
ALSound *soundArray[1];
} ALInstrument;
typedef struct ALBank_s {
s16 instCount; /* number of programs in this bank */
u8 flags;
u8 pad;
s32 sampleRate; /* e.g. 44100, 22050, etc... */
ALInstrument *percussion; /* default percussion for GM */
ALInstrument *instArray[1]; /* ARRAY of instruments */
} ALBank;
typedef struct { /* Note: sizeof won't be correct */
s16 revision; /* format revision of this file */
s16 bankCount; /* number of banks */
ALBank *bankArray[1]; /* ARRAY of bank offsets */
} ALBankFile;
void alBnkfNew(ALBankFile *f, u8 *table);
/***********************************************************************
* Sequence Files
***********************************************************************/
#define AL_SEQBANK_VERSION 'S1'
typedef struct {
u8 *offset;
s32 len;
} ALSeqData;
typedef struct { /* Note: sizeof won't be correct */
s16 revision; /* format revision of this file */
s16 seqCount; /* number of sequences */
ALSeqData seqArray[1]; /* ARRAY of sequence info */
} ALSeqFile;
void alSeqFileNew(ALSeqFile *f, u8 *base);
/***********************************************************************
* Synthesis driver stuff
***********************************************************************/
typedef ALMicroTime (*ALVoiceHandler)(void *);
typedef struct {
s32 maxVVoices; /* obsolete */
s32 maxPVoices;
s32 maxUpdates;
s32 maxFXbusses;
void *dmaproc;
ALHeap *heap;
s32 outputRate; /* output sample rate */
ALFxId fxTypes[4];
s32 *params;
} ALSynConfig;
typedef struct ALPlayer_s {
struct ALPlayer_s *next;
void *clientData; /* storage for client callback */
ALVoiceHandler handler; /* voice handler for player */
ALMicroTime callTime; /* usec requested callback */
s32 samplesLeft; /* usec remaining to callback */
} ALPlayer;
typedef struct ALVoice_s {
ALLink node;
struct PVoice_s *pvoice;
ALWaveTable *table;
void *clientPrivate;
s16 state;
s16 priority;
s16 fxBus;
s16 unityPitch;
} ALVoice;
typedef struct ALVoiceConfig_s {
s16 priority; /* voice priority */
s16 fxBus; /* bus assignment */
u8 unityPitch; /* unity pitch flag */
} ALVoiceConfig;
/**
* This struct needs some modifications but I'm not sure how yet.
* outputRate should be at 0x40
*/
typedef struct {
/*0x00*/ ALPlayer *head; /* client list head */
/*0x04*/ ALLink pFreeList; /* list of free physical voices */
/*0x0c*/ ALLink pAllocList; /* list of allocated physical voices */
/*0x14*/ ALLink pLameList; /* list of voices ready to be freed */
/*0x1c*/ s32 paramSamples;
/*0x20*/ s32 curSamples; /* samples from start of game */
/*0x24*/ ALDMANew dma;
/*0x28*/ ALHeap *heap;
/*0x2c*/ struct ALParam_s *paramList;
/*0x30*/ struct ALMainBus_s *mainBus;
/*0x34*/ struct ALAuxBus_s *auxBus; /* ptr to array of aux bus structs */
/*0x38*/ struct ALFilter_s *outputFilter; /* last filter in the filter chain */
/*0x3c*/ s32 numPVoices;
/*0x40*/ s32 maxAuxBusses;
/*0x44*/ s32 outputRate; /* output sample rate */
/*0x48*/ s32 maxOutSamples; /* Maximum samples rsp can generate
at one time at output rate */
} ALSynth;
void alSynNew(ALSynth *s, ALSynConfig *config);
void alSynDelete(ALSynth *s);
void alSynAddPlayer(ALSynth *s, ALPlayer *client);
void alSynRemovePlayer(ALSynth *s, ALPlayer *client);
s32 alSynAllocVoice(ALSynth *s, ALVoice *v, ALVoiceConfig *vc);
void alSynFreeVoice(ALSynth *s, ALVoice *voice);
void alSynStartVoice(ALSynth *s, ALVoice *voice, ALWaveTable *w);
void alSynStartVoiceParams(ALSynth *s, ALVoice *voice, ALWaveTable *w,
f32 pitch, s16 vol, ALPan pan, u8 fxmix,
ALMicroTime t);
void alSynStopVoice(ALSynth *s, ALVoice *voice);
void alSynSetVol(ALVoice *v, s16 vol, ALMicroTime delta);
void alSynSetPitch(ALSynth *s, ALVoice *voice, f32 ratio);
void alSynSetPan(ALSynth *s, ALVoice *voice, ALPan pan);
void alSynSetFXMix(ALSynth *s, ALVoice *voice, u8 fxmix);
void n_alSynSetPriority(ALVoice *voice, s16 priority);
s16 alSynGetPriority(ALSynth *s, ALVoice *voice);
ALFxRef *alSynAllocFX(ALSynth *s, s16 bus, ALSynConfig *c, ALHeap *hp);
ALFxRef alSynGetFXRef(ALSynth *s, s16 bus, s16 index);
void alSynFreeFX(ALSynth *s, ALFxRef *fx);
void alSynSetFXParam(ALSynth *s, ALFxRef fx, s16 paramID, void *param);
/***********************************************************************
* Audio Library (AL) stuff
***********************************************************************/
typedef struct {
ALSynth drvr;
} ALGlobals;
extern ALGlobals *n_syn;
void alInit(ALGlobals *glob, ALSynConfig *c);
void alClose(ALGlobals *glob);
Acmd *alAudioFrame(Acmd *cmdList, s32 *cmdLen, s16 *outBuf, s32 outLen);
/***********************************************************************
* Sequence Player stuff
***********************************************************************/
/*
* Play states
*/
#define AL_STOPPED 0
#define AL_PLAYING 1
#define AL_STOPPING 2
#define AL_DEFAULT_PRIORITY 5
#define AL_DEFAULT_VOICE 0
#define AL_MAX_CHANNELS 16
/*
* Audio Library event type definitions
*/
enum ALMsg {
AL_SEQ_REF_EVT, /* Reference to a pending event in the sequence. */
AL_SEQ_MIDI_EVT,
AL_SEQP_MIDI_EVT,
AL_TEMPO_EVT,
AL_SEQ_END_EVT,
AL_NOTE_END_EVT,
AL_SEQP_ENV_EVT,
AL_SEQP_META_EVT,
AL_SEQP_PROG_EVT,
AL_SEQP_API_EVT,
AL_SEQP_VOL_EVT,
AL_SEQP_LOOP_EVT,
AL_SEQP_PRIORITY_EVT,
AL_SEQP_SEQ_EVT,
AL_SEQP_BANK_EVT,
AL_SEQP_PLAY_EVT,
AL_SEQP_STOP_EVT,
AL_SEQP_STOPPING_EVT,
AL_TRACK_END,
AL_CSP_LOOPSTART,
AL_CSP_LOOPEND,
AL_CSP_NOTEOFF_EVT,
AL_TREM_OSC_EVT,
AL_VIB_OSC_EVT
};
/*
* Midi event definitions
*/
#define AL_EVTQ_END 0x7fffffff
enum AL_MIDIstatus {
/* For distinguishing channel number from status */
AL_MIDI_ChannelMask = 0x0F,
AL_MIDI_StatusMask = 0xF0,
/* Channel voice messages */
AL_MIDI_ChannelVoice = 0x80,
AL_MIDI_NoteOff = 0x80,
AL_MIDI_NoteOn = 0x90,
AL_MIDI_PolyKeyPressure = 0xA0,
AL_MIDI_ControlChange = 0xB0,
AL_MIDI_ChannelModeSelect = 0xB0,
AL_MIDI_ProgramChange = 0xC0,
AL_MIDI_ChannelPressure = 0xD0,
AL_MIDI_PitchBendChange = 0xE0,
/* System messages */
AL_MIDI_SysEx = 0xF0, /* System Exclusive */
/* System common */
AL_MIDI_SystemCommon = 0xF1,
AL_MIDI_TimeCodeQuarterFrame = 0xF1,
AL_MIDI_SongPositionPointer = 0xF2,
AL_MIDI_SongSelect = 0xF3,
AL_MIDI_Undefined1 = 0xF4,
AL_MIDI_Undefined2 = 0xF5,
AL_MIDI_TuneRequest = 0xF6,
AL_MIDI_EOX = 0xF7, /* End of System Exclusive */
/* System real time */
AL_MIDI_SystemRealTime = 0xF8,
AL_MIDI_TimingClock = 0xF8,
AL_MIDI_Undefined3 = 0xF9,
AL_MIDI_Start = 0xFA,
AL_MIDI_Continue = 0xFB,
AL_MIDI_Stop = 0xFC,
AL_MIDI_Undefined4 = 0xFD,
AL_MIDI_ActiveSensing = 0xFE,
AL_MIDI_SystemReset = 0xFF,
AL_MIDI_Meta = 0xFF /* MIDI Files only */
};
enum AL_MIDIctrl {
AL_MIDI_VOLUME_CTRL = 0x07,
AL_MIDI_PAN_CTRL = 0x0A,
AL_MIDI_PRIORITY_CTRL = 0x10, /* use general purpose controller for priority */
AL_MIDI_FX_CTRL_0 = 0x14,
AL_MIDI_FX_CTRL_1 = 0x15,
AL_MIDI_FX_CTRL_2 = 0x16,
AL_MIDI_FX_CTRL_3 = 0x17,
AL_MIDI_FX_CTRL_4 = 0x18,
AL_MIDI_FX_CTRL_5 = 0x19,
AL_MIDI_FX_CTRL_6 = 0x1A,
AL_MIDI_FX_CTRL_7 = 0x1B,
AL_MIDI_FX_CTRL_8 = 0x1C,
AL_MIDI_FX_CTRL_9 = 0x1D,
AL_MIDI_SUSTAIN_CTRL = 0x40,
AL_MIDI_FX1_CTRL = 0x5B,
AL_MIDI_FX3_CTRL = 0x5D
};
enum AL_MIDImeta {
AL_MIDI_META_TEMPO = 0x51,
AL_MIDI_META_EOT = 0x2f
};
#define AL_CMIDI_BLOCK_CODE 0xFE
#define AL_CMIDI_LOOPSTART_CODE 0x2E
#define AL_CMIDI_LOOPEND_CODE 0x2D
#define AL_CMIDI_CNTRL_LOOPSTART 102
#define AL_CMIDI_CNTRL_LOOPEND 103
#define AL_CMIDI_CNTRL_LOOPCOUNT_SM 104
#define AL_CMIDI_CNTRL_LOOPCOUNT_BIG 105
typedef struct {
u8 *curPtr; /* ptr to the next event */
s32 lastTicks; /* sequence clock ticks (used by alSeqSetLoc) */
s32 curTicks; /* sequence clock ticks of next event (used by loop end test) */
s16 lastStatus; /* the last status msg */
} ALSeqMarker;
typedef struct {
s32 ticks; /* MIDI, Tempo and End events must start with ticks */
u8 status;
u8 byte1;
u8 byte2;
u32 duration;
} ALMIDIEvent;
typedef struct {
s32 ticks;
u8 status;
u8 type;
u8 len;
u8 byte1;
u8 byte2;
u8 byte3;
} ALTempoEvent;
typedef struct {
s32 ticks;
u8 status;
u8 type;
u8 len;
} ALEndEvent;
typedef struct {
struct ALVoice_s *voice;
} ALNoteEvent;
typedef struct {
struct ALVoice_s *voice;
ALMicroTime delta;
u8 vol;
} ALVolumeEvent;
typedef struct {
s16 vol;
} ALSeqpVolEvent;
typedef struct {
ALSeqMarker *start;
ALSeqMarker *end;
s32 count;
} ALSeqpLoopEvent;
typedef struct {
u8 chan;
u8 priority;
} ALSeqpPriorityEvent;
typedef struct {
void *seq; /* pointer to a seq (could be an ALSeq or an ALCSeq). */
} ALSeqpSeqEvent;
typedef struct {
ALBank *bank;
} ALSeqpBankEvent;
typedef struct {
struct ALVoiceState_s *vs;
void *oscState;
u8 chan;
} ALOscEvent;
typedef struct {
s16 type;
union {
ALMIDIEvent midi;
ALTempoEvent tempo;
ALEndEvent end;
ALNoteEvent note;
ALVolumeEvent vol;
ALSeqpLoopEvent loop;
ALSeqpVolEvent spvol;
ALSeqpPriorityEvent sppriority;
ALSeqpSeqEvent spseq;
ALSeqpBankEvent spbank;
ALOscEvent osc;
} msg;
} ALEvent;
typedef struct {
ALLink node;
ALMicroTime delta;
ALEvent evt;
} ALEventListItem;
typedef struct {
ALLink freeList;
ALLink allocList;
s32 eventCount;
} ALEventQueue;
void n_alEvtqNew(ALEventQueue *evtq, ALEventListItem *items,
s32 itemCount);
ALMicroTime n_alEvtqNextEvent(ALEventQueue *evtq, ALEvent *evt);
void alEvtqPostEvent(ALEventQueue *evtq, ALEvent *evt,
ALMicroTime delta, s32 arg3);
void alEvtqFlush(ALEventQueue *evtq);
void n_alEvtqFlushType(ALEventQueue *evtq, s16 type);
#define AL_PHASE_ATTACK 0
#define AL_PHASE_NOTEON 0
#define AL_PHASE_DECAY 1
#define AL_PHASE_SUSTAIN 2
#define AL_PHASE_RELEASE 3
#define AL_PHASE_SUSTREL 4
typedef struct ALVoiceState_s {
struct ALVoiceState_s *next;/* MUST be first */
ALVoice voice;
ALSound *sound;
ALMicroTime envEndTime; /* time of envelope segment end */
f32 pitch; /* currect pitch ratio */
f32 vibrato; /* current value of the vibrato */
u8 envGain; /* current envelope gain */
u8 channel; /* channel assignment */
u8 key; /* note on key number */
u8 velocity; /* note on velocity */
u8 envPhase; /* what envelope phase */
u8 phase;
u8 tremelo; /* current value of the tremelo */
u8 flags; /* bit 0 tremelo flag
bit 1 vibrato flag */
u32 unk38;
u32 unk3c;
} ALVoiceState;
typedef struct {
/*0x00*/ ALInstrument *instrument; /* instrument assigned to this chan */
/*0x04*/ s16 bendRange; /* pitch bend range in cents */
/*0x06*/ ALFxId fxId; /* type of fx assigned to this chan */
/*0x07*/ ALPan pan; /* overall pan for this chan */
/*0x08*/ u8 priority; /* priority for this chan */
/*0x09*/ u8 vol; /* current volume for this chan */
/*0x0a*/ u8 fxmix; /* current fx mix for this chan */
/*0x0b*/ u8 unk0b;
/*0x0c*/ u8 sustain; /* current sustain pedal state */
u8 unk0d;
u8 unk0e;
u8 unk0f;
u8 unk10;
u8 unk11;
u8 unk12;
u8 unk13;
f32 pitchBend; /* current pitch bend val in cents */
u32 unk18;
u32 unk1c;
u32 unk20;
u32 unk24;
u32 unk28;
u32 unk2c;
u8 unk30;
u8 unk31;
u8 unk32;
} ALChanState;
typedef struct ALSeq_s {
u8 *base; /* ptr to start of sequence file */
u8 *trackStart; /* ptr to first MIDI event */
u8 *curPtr; /* ptr to next event to read */
s32 lastTicks; /* MIDI ticks for last event */
s32 len; /* length of sequence in bytes */
f32 qnpt; /* qrter notes / tick (1/division) */
s16 division; /* ticks per quarter note */
s16 lastStatus; /* for running status */
} ALSeq;
typedef struct {
u32 trackOffset[16];
u32 division;
} ALCMidiHdr;
typedef struct ALCSeq_s {
ALCMidiHdr *base; /* ptr to start of sequence file */
u32 validTracks; /* set of flags, showing valid tracks */
f32 qnpt; /* qrter notes / tick (1/division) */
u32 lastTicks; /* keep track of ticks incase app wants */
u32 lastDeltaTicks; /* number of delta ticks of last event */
u32 deltaFlag; /* flag: set if delta's not subtracted */
u8 *curLoc[16]; /* ptr to current track location, */
/* may point to next event, or may point */
/* to a backup code */
u8 *curBUPtr[16]; /* ptr to next event if in backup mode */
u8 curBULen[16]; /* if > 0, then in backup mode */
u8 lastStatus[16]; /* for running status */
u32 evtDeltaTicks[16]; /* delta time to next event */
} ALCSeq;
typedef struct {
u32 validTracks;
s32 lastTicks;
u32 lastDeltaTicks;
u8 *curLoc[16];
u8 *curBUPtr[16];
u8 curBULen[16];
u8 lastStatus[16];
u32 evtDeltaTicks[16];
} ALCSeqMarker;
#define NO_SOUND_ERR_MASK 0x01
#define NOTE_OFF_ERR_MASK 0x02
#define NO_VOICE_ERR_MASK 0x04
typedef struct {
s32 maxVoices; /* max number of voices to alloc */
s32 maxEvents; /* max internal events to support */
u8 maxChannels; /* max MIDI channels to support (16)*/
u8 debugFlags; /* control which error get reported */
ALHeap *heap; /* ptr to initialized heap */
void *initOsc;
void *updateOsc;
void *stopOsc;
} ALSeqpConfig;
typedef ALMicroTime (*ALOscInit)(void **oscState,f32 *initVal, u8 oscType,
u8 oscRate, u8 oscDepth, u8 oscDelay);
typedef ALMicroTime (*ALOscUpdate)(void *oscState, f32 *updateVal);
typedef void (*ALOscStop)(void *oscState);
typedef struct {
ALPlayer node; /* note: must be first in structure */
ALSynth *drvr; /* reference to the client driver */
ALSeq *target; /* current sequence */
ALMicroTime curTime;
ALBank *bank; /* current ALBank */
s32 uspt; /* microseconds per tick */
s32 nextDelta; /* microseconds to next callback */
s32 state;
u16 chanMask; /* active channels */
s16 vol; /* overall sequence volume */
u8 maxChannels; /* number of MIDI channels */
u8 debugFlags; /* control which error get reported */
ALEvent nextEvent;
ALEventQueue evtq;
ALMicroTime frameTime;
ALChanState *chanState; /* 16 channels for MIDI */
ALVoiceState *vAllocHead; /* list head for allocated voices */
ALVoiceState *vAllocTail; /* list tail for allocated voices */
ALVoiceState *vFreeList; /* list of free voice state structs */
ALOscInit initOsc;
ALOscUpdate updateOsc;
ALOscStop stopOsc;
ALSeqMarker *loopStart;
ALSeqMarker *loopEnd;
s32 loopCount; /* -1 = loop forever, 0 = no loop */
} ALSeqPlayer;
typedef struct {
ALPlayer node; /* note: must be first in structure */
ALSynth *drvr; /* reference to the client driver */
ALCSeq *target; /* current sequence */
ALMicroTime curTime;
ALBank *bank; /* current ALBank */
s32 uspt; /* microseconds per tick */
s32 nextDelta; /* microseconds to next callback */
s32 state;
u16 chanMask; /* active channels */
s16 vol; /* overall sequence volume */
u8 maxChannels; /* number of MIDI channels */
u8 debugFlags; /* control which error get reported */
ALEvent nextEvent;
ALEventQueue evtq;
ALMicroTime frameTime;
ALChanState *chanState; /* 16 channels for MIDI */
ALVoiceState *vAllocHead; /* list head for allocated voices */
ALVoiceState *vAllocTail; /* list tail for allocated voices */
ALVoiceState *vFreeList; /* list of free voice state structs */
ALOscInit initOsc;
ALOscUpdate updateOsc;
ALOscStop stopOsc;
f32 unk7c;
f32 unk80;
s32 unk84;
u8 unk88;
u8 unk89;
} ALCSPlayer;
/*
* Sequence data representation routines
*/
void alSeqNew(ALSeq *seq, u8 *ptr, s32 len);
void alSeqNextEvent(ALSeq *seq, ALEvent *event);
s32 alSeqGetTicks(ALSeq *seq);
f32 alSeqTicksToSec(ALSeq *seq, s32 ticks, u32 tempo);
u32 alSeqSecToTicks(ALSeq *seq, f32 sec, u32 tempo);
void alSeqNewMarker(ALSeq *seq, ALSeqMarker *m, u32 ticks);
void alSeqSetLoc(ALSeq *seq, ALSeqMarker *marker);
void alSeqGetLoc(ALSeq *seq, ALSeqMarker *marker);
/*
* Compact Sequence data representation routines
*/
void alCSeqNew(ALCSeq *seq, u8 *ptr);
void alCSeqNextEvent(ALCSeq *seq, ALEvent *evt, s32 arg2);
s32 alCSeqGetTicks(ALCSeq *seq);
f32 alCSeqTicksToSec(ALCSeq *seq, s32 ticks, u32 tempo);
u32 alCSeqSecToTicks(ALCSeq *seq, f32 sec, u32 tempo);
void alCSeqNewMarker(ALCSeq *seq, ALCSeqMarker *m, u32 ticks);
void alCSeqSetLoc(ALCSeq *seq, ALCSeqMarker *marker);
void alCSeqGetLoc(ALCSeq *seq, ALCSeqMarker *marker);
/*
* Sequence Player routines
*/
f32 alCents2Ratio(s32 cents);
void alSeqpNew(ALSeqPlayer *seqp, ALSeqpConfig *config);
void alSeqpDelete(ALSeqPlayer *seqp);
void alSeqpSetSeq(ALSeqPlayer *seqp, ALSeq *seq);
ALSeq *alSeqpGetSeq(ALSeqPlayer *seqp);
void alSeqpPlay(ALSeqPlayer *seqp);
void alSeqpStop(ALSeqPlayer *seqp);
s32 alSeqpGetState(ALSeqPlayer *seqp);
void alSeqpSetBank(ALSeqPlayer *seqp, ALBank *b);
void alSeqpSetTempo(ALSeqPlayer *seqp, s32 tempo);
s32 alSeqpGetTempo(ALSeqPlayer *seqp);
s16 alSeqpGetVol(ALSeqPlayer *seqp); /* Master volume control */
void alSeqpSetVol(ALSeqPlayer *seqp, s16 vol);
void alSeqpLoop(ALSeqPlayer *seqp, ALSeqMarker *start, ALSeqMarker *end, s32 count);
void alSeqpSetChlProgram(ALSeqPlayer *seqp, u8 chan, u8 prog);
s32 alSeqpGetChlProgram(ALSeqPlayer *seqp, u8 chan);
void alSeqpSetChlFXMix(ALSeqPlayer *seqp, u8 chan, u8 fxmix);
u8 alSeqpGetChlFXMix(ALSeqPlayer *seqp, u8 chan);
void alSeqpSetChlVol(ALSeqPlayer *seqp, u8 chan, u8 vol);
u8 alSeqpGetChlVol(ALSeqPlayer *seqp, u8 chan);
void alSeqpSetChlPan(ALSeqPlayer *seqp, u8 chan, ALPan pan);
ALPan alSeqpGetChlPan(ALSeqPlayer *seqp, u8 chan);
void alSeqpSetChlPriority(ALSeqPlayer *seqp, u8 chan, u8 priority);
u8 alSeqpGetChlPriority(ALSeqPlayer *seqp, u8 chan);
void alSeqpSendMidi(ALSeqPlayer *seqp, s32 ticks, u8 status, u8 byte1, u8 byte2);
/* Maintain backwards compatibility with old routine names. */
#define alSeqpSetProgram alSeqpSetChlProgram
#define alSeqpGetProgram alSeqpGetChlProgram
#define alSeqpSetFXMix alSeqpSetChlFXMix
#define alSeqpGetFXMix alSeqpGetChlFXMix
#define alSeqpSetPan alSeqpSetChlPan
#define alSeqpGetPan alSeqpGetChlPan
#define alSeqpSetChannelPriority alSeqpSetChlPriority
#define alSeqpGetChannelPriority alSeqpGetChlPriority
/*
* Compressed Sequence Player routines
*/
void alCSPNew(ALCSPlayer *seqp, ALSeqpConfig *config);
void alCSPDelete(ALCSPlayer *seqp);
void alCSPSetSeq(ALCSPlayer *seqp, ALCSeq *seq);
ALCSeq *alCSPGetSeq(ALCSPlayer *seqp);
void alCSPPlay(ALCSPlayer *seqp);
void alCSPStop(ALCSPlayer *seqp);
s32 alCSPGetState(ALCSPlayer *seqp);
void alCSPSetBank(ALCSPlayer *seqp, ALBank *b);
void alCSPSetTempo(ALCSPlayer *seqp, s32 tempo);
s32 alCSPGetTempo(ALCSPlayer *seqp);
s16 alCSPGetVol(ALCSPlayer *seqp);
void alCSPSetVol(ALCSPlayer *seqp, s16 vol);
void alCSPSetChlProgram(ALCSPlayer *seqp, u8 chan, u8 prog);
s32 alCSPGetChlProgram(ALCSPlayer *seqp, u8 chan);
void alCSPSetChlFXMix(ALCSPlayer *seqp, u8 chan, u8 fxmix);
u8 alCSPGetChlFXMix(ALCSPlayer *seqp, u8 chan);
void alCSPSetChlPan(ALCSPlayer *seqp, u8 chan, ALPan pan);
ALPan alCSPGetChlPan(ALCSPlayer *seqp, u8 chan);
void alCSPSetChlVol(ALCSPlayer *seqp, u8 chan, u8 vol);
u8 alCSPGetChlVol(ALCSPlayer *seqp, u8 chan);
void alCSPSetChlPriority(ALCSPlayer *seqp, u8 chan, u8 priority);
u8 alCSPGetChlPriority(ALCSPlayer *seqp, u8 chan);
void alCSPSendMidi(ALCSPlayer *seqp, s32 ticks, u8 status,
u8 byte1, u8 byte2);
/* Maintain backwards compatibility with old routine names. */
#define alCSPSetProgram alCSPSetChlProgram
#define alCSPGetProgram alCSPGetChlProgram
#define alCSPSetFXMix alCSPSetChlFXMix
#define alCSPGetFXMix alCSPGetChlFXMix
#define alCSPSetPan alCSPSetChlPan
#define alCSPGetPan alCSPGetChlPan
#define alCSPSetChannelPriority alCSPSetChlPriority
#define alCSPGetChannelPriority alCSPGetChlPriority
/***********************************************************************
* Sound Player stuff
***********************************************************************/
typedef struct {
s32 maxSounds;
s32 maxEvents;
ALHeap *heap;
} ALSndpConfig;
typedef struct {
ALPlayer node; /* note: must be first in structure */
ALEventQueue evtq;
ALEvent nextEvent;
ALSynth *drvr; /* reference to the client driver */
s32 target;
void *sndState;
s32 maxSounds;
ALMicroTime frameTime;
ALMicroTime nextDelta; /* microseconds to next callback */
ALMicroTime curTime;
} ALSndPlayer;
typedef s16 ALSndId;
void alSndpNew(ALSndPlayer *sndp, ALSndpConfig *c);
void alSndpDelete(ALSndPlayer *sndp);
ALSndId alSndpAllocate(ALSndPlayer *sndp, ALSound *sound);
void alSndpDeallocate(ALSndPlayer *sndp, ALSndId id);
void alSndpSetSound(ALSndPlayer *sndp, ALSndId id);
ALSndId alSndpGetSound(ALSndPlayer *sndp);
void alSndpPlay(ALSndPlayer *sndp);
void alSndpPlayAt(ALSndPlayer *sndp, ALMicroTime delta);
void alSndpStop(ALSndPlayer *sndp);
void alSndpSetVol(ALSndPlayer *sndp, s16 vol);
void alSndpSetPitch(ALSndPlayer *sndp, f32 pitch);
void alSndpSetPan(ALSndPlayer *sndp, ALPan pan);
void alSndpSetPriority(ALSndPlayer *sndp, ALSndId id, u8 priority);
void alSndpSetFXMix(ALSndPlayer *sndp, u8 mix);
s32 alSndpGetState(ALSndPlayer *sndp);
#ifndef _FINALROM
void alParseAbiCL(Acmd *cmdList, u32 nbytes);
#endif
#ifdef _LANGUAGE_C_PLUS_PLUS
}
#endif
#endif /* !__LIB_AUDIO__ */
src/include/PR/libultra.h
-18
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@@ -1,18 +0,0 @@
#ifndef _LIBULTRA_H
#define _LIBULTRA_H
#define OS_TV_TYPE_PAL 0
#define OS_TV_TYPE_NTSC 1
#define OS_TV_TYPE_MPAL 2
#define RESET_TYPE_COLD_RESET 0
#define RESET_TYPE_NMI 1
#define RESET_TYPE_BOOT_DISK 2
extern s32 osTvType;
extern u32 osRomBase;
extern u32 osResetType;
extern u32 osMemSize;
extern u8 osAppNmiBuffer[64];
#endif /* _LIBULTRA_H */
src/include/PR/mbi.h
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@@ -1,104 +0,0 @@
#ifndef _MBI_H_
#define _MBI_H_
/**************************************************************************
* *
* Copyright (C) 1994, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
**************************************************************************/
/**************************************************************************
*
* $Revision: 1.136 $
* $Date: 1999/01/05 13:04:00 $
* $Source: /hosts/gate3/exdisk2/cvs/N64OS/Master/cvsmdev2/PR/include/mbi.h,v $
*
**************************************************************************/
/*
* Header file for the Media Binary Interface
*
* NOTE: This file is included by the RSP microcode, so any C-specific
* constructs must be bracketed by #ifdef _LANGUAGE_C
*
*/
/*
* the SHIFT macros are used to build display list commands, inserting
* bit-fields into a 32-bit word. They take a value, a shift amount,
* and a width.
*
* For the left shift, the lower bits of the value are masked,
* then shifted left.
*
* For the right shift, the value is shifted right, then the lower bits
* are masked.
*
* (NOTE: _SHIFTL(v, 0, 32) won't work, just use an assignment)
*
*/
#define _SHIFTL(v, s, w) \
((unsigned int) (((unsigned int)(v) & ((0x01 << (w)) - 1)) << (s)))
#define _SHIFTR(v, s, w) \
((unsigned int)(((unsigned int)(v) >> (s)) & ((0x01 << (w)) - 1)))
#define _SHIFT _SHIFTL /* old, for compatibility only */
#define G_ON (1)
#define G_OFF (0)
/**************************************************************************
*
* Graphics Binary Interface
*
**************************************************************************/
#ifdef F3D_OLD
#include <PR/gbi_old.h>
#else
#include <PR/gbi.h>
#endif
/**************************************************************************
*
* Audio Binary Interface
*
**************************************************************************/
#include <PR/abi.h>
/**************************************************************************
*
* Task list
*
**************************************************************************/
#define M_GFXTASK 1
#define M_AUDTASK 2
#define M_VIDTASK 3
#define M_HVQTASK 6
#define M_HVQMTASK 7
/**************************************************************************
*
* Segment macros and definitions
*
**************************************************************************/
#define NUM_SEGMENTS (16)
#define SEGMENT_OFFSET(a) ((unsigned int)(a) & 0x00ffffff)
#define SEGMENT_NUMBER(a) (((unsigned int)(a) << 4) >> 28)
#define SEGMENT_ADDR(num, off) (((num) << 24) + (off))
#ifndef NULL
#define NULL 0
#endif
#endif /* !_MBI_H_ */
src/include/PR/os_ai.h
-92
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@@ -1,92 +0,0 @@
/*====================================================================
* os_ai.h
*
* Copyright 1995, Silicon Graphics, Inc.
* All Rights Reserved.
*
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Silicon Graphics,
* Inc.; the contents of this file may not be disclosed to third
* parties, copied or duplicated in any form, in whole or in part,
* without the prior written permission of Silicon Graphics, Inc.
*
* RESTRICTED RIGHTS LEGEND:
* Use, duplication or disclosure by the Government is subject to
* restrictions as set forth in subdivision (c)(1)(ii) of the Rights
* in Technical Data and Computer Software clause at DFARS
* 252.227-7013, and/or in similar or successor clauses in the FAR,
* DOD or NASA FAR Supplement. Unpublished - rights reserved under the
* Copyright Laws of the United States.
*====================================================================*/
/*---------------------------------------------------------------------*
Copyright (C) 1998 Nintendo. (Originated by SGI)
$RCSfile: os_ai.h,v $
$Revision: 1.1 $
$Date: 1998/10/09 08:01:04 $
*---------------------------------------------------------------------*/
#ifndef _OS_AI_H_
#define _OS_AI_H_
#ifdef _LANGUAGE_C_PLUS_PLUS
extern "C" {
#endif
#include <PR/ultratypes.h>
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
/**************************************************************************
*
* Type definitions
*
*/
#endif /* defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) */
/**************************************************************************
*
* Global definitions
*
*/
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
/**************************************************************************
*
* Macro definitions
*
*/
/**************************************************************************
*
* Extern variables
*
*/
/**************************************************************************
*
* Function prototypes
*
*/
/* Audio interface (Ai) */
extern u32 osAiGetStatus(void);
extern u32 osAiGetLength(void);
extern s32 osAiSetFrequency(u32);
extern s32 osAiSetNextBuffer(void *, u32);
#endif /* defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) */
#ifdef _LANGUAGE_C_PLUS_PLUS
}
#endif
#endif /* !_OS_AI_H_ */
src/include/PR/os_cache.h
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@@ -1,96 +0,0 @@
/*====================================================================
* os_cache.h
*
* Copyright 1995, Silicon Graphics, Inc.
* All Rights Reserved.
*
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Silicon Graphics,
* Inc.; the contents of this file may not be disclosed to third
* parties, copied or duplicated in any form, in whole or in part,
* without the prior written permission of Silicon Graphics, Inc.
*
* RESTRICTED RIGHTS LEGEND:
* Use, duplication or disclosure by the Government is subject to
* restrictions as set forth in subdivision (c)(1)(ii) of the Rights
* in Technical Data and Computer Software clause at DFARS
* 252.227-7013, and/or in similar or successor clauses in the FAR,
* DOD or NASA FAR Supplement. Unpublished - rights reserved under the
* Copyright Laws of the United States.
*====================================================================*/
/*---------------------------------------------------------------------*
Copyright (C) 1998 Nintendo. (Originated by SGI)
$RCSfile: os_cache.h,v $
$Revision: 1.1 $
$Date: 1998/10/09 08:01:04 $
*---------------------------------------------------------------------*/
#ifndef _OS_CACHE_H_
#define _OS_CACHE_H_
#ifdef _LANGUAGE_C_PLUS_PLUS
extern "C" {
#endif
#include <PR/ultratypes.h>
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
/**************************************************************************
*
* Type definitions
*
*/
#endif /* defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) */
/**************************************************************************
*
* Global definitions
*
*/
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
/**************************************************************************
*
* Macro definitions
*
*/
#define OS_DCACHE_ROUNDUP_ADDR(x) (void *)(((((u32)(x)+0xf)/0x10)*0x10))
#define OS_DCACHE_ROUNDUP_SIZE(x) (u32)(((((u32)(x)+0xf)/0x10)*0x10))
/**************************************************************************
*
* Extern variables
*
*/
/**************************************************************************
*
* Function prototypes
*
*/
/* Cache operations and macros */
extern void osInvalDCache(void *, s32);
extern void osInvalICache(void *, s32);
extern void osWritebackDCache(void *, s32);
extern void osWritebackDCacheAll(void);
#endif /* defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) */
#ifdef _LANGUAGE_C_PLUS_PLUS
}
#endif
#endif /* !_OS_CACHE_H_ */
src/include/PR/os_cont.h
-338
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@@ -1,338 +0,0 @@
/*====================================================================
* os_cont.h
*
* Copyright 1995, Silicon Graphics, Inc.
* All Rights Reserved.
*
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Silicon Graphics,
* Inc.; the contents of this file may not be disclosed to third
* parties, copied or duplicated in any form, in whole or in part,
* without the prior written permission of Silicon Graphics, Inc.
*
* RESTRICTED RIGHTS LEGEND:
* Use, duplication or disclosure by the Government is subject to
* restrictions as set forth in subdivision (c)(1)(ii) of the Rights
* in Technical Data and Computer Software clause at DFARS
* 252.227-7013, and/or in similar or successor clauses in the FAR,
* DOD or NASA FAR Supplement. Unpublished - rights reserved under the
* Copyright Laws of the United States.
*====================================================================*/
/*---------------------------------------------------------------------*
Copyright (C) 1998 Nintendo. (Originated by SGI)
$RCSfile: os_cont.h,v $
$Revision: 1.1 $
$Date: 1998/10/09 08:01:05 $
*---------------------------------------------------------------------*/
#ifndef _OS_CONT_H_
#define _OS_CONT_H_
#ifdef _LANGUAGE_C_PLUS_PLUS
extern "C" {
#endif
#include <PR/ultratypes.h>
#include "os_message.h"
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
/**************************************************************************
*
* Type definitions
*
*/
/*
* Structure for controllers
*/
typedef struct {
u16 type; /* Controller Type */
u8 status; /* Controller status */
u8 errno;
}OSContStatus;
typedef struct {
u16 button;
s8 stick_x; /* -80 <= stick_x <= 80 */
s8 stick_y; /* -80 <= stick_y <= 80 */
u8 errno;
} OSContPad;
typedef struct {
void *address; /* Ram pad Address: 11 bits */
u8 databuffer[32]; /* address of the data buffer */
u8 addressCrc; /* CRC code for address */
u8 dataCrc; /* CRC code for data */
u8 errno;
} OSContRamIo;
typedef struct
{
/* 0x0 */ u32 ramarray[15];
/* 0x3C */ u32 pifstatus;
} OSPifRam;
typedef struct
{
/* 0x0 */ u8 dummy;
/* 0x1 */ u8 txsize;
/* 0x2 */ u8 rxsize;
/* 0x3 */ u8 cmd;
/* 0x4 */ u16 button;
/* 0x6 */ s8 stick_x;
/* 0x7 */ s8 stick_y;
} __OSContReadFormat;
typedef struct
{
/* 0x0 */ u8 dummy;
/* 0x1 */ u8 txsize;
/* 0x2 */ u8 rxsize;
/* 0x3 */ u8 cmd;
/* 0x4 */ u8 typeh;
/* 0x5 */ u8 typel;
/* 0x6 */ u8 status;
/* 0x7 */ u8 dummy1;
} __OSContRequestFormat;
typedef struct
{
/* 0x0 */ u8 txsize;
/* 0x1 */ u8 rxsize;
/* 0x2 */ u8 cmd;
/* 0x3 */ u8 typeh;
/* 0x4 */ u8 typel;
/* 0x5 */ u8 status;
} __OSContRequestFormatShort;
typedef struct
{
/* 0x0 */ u8 dummy;
/* 0x1 */ u8 txsize;
/* 0x2 */ u8 rxsize;
/* 0x3 */ u8 cmd;
/* 0x4 */ u8 hi;
/* 0x4 */ u8 lo;
/* 0x6 */ u8 data[BLOCKSIZE];
/* 0x26 */ u8 datacrc;
} __OSContRamReadFormat;
typedef union {
/* 0x0 */ struct
{
/* 0x0 */ u8 bank;
/* 0x1 */ u8 page;
} inode_t;
/* 0x0 */ u16 ipage;
} __OSInodeUnit;
typedef struct
{
/* 0x0 */ u32 game_code;
/* 0x4 */ u16 company_code;
/* 0x6 */ __OSInodeUnit start_page;
/* 0x8 */ u8 status;
/* 0x9 */ s8 reserved;
/* 0xA */ u16 data_sum;
/* 0xC */ u8 ext_name[4];
/* 0x10 */ u8 game_name[16];
} __OSDir;
typedef struct
{
/* 0x0 */ __OSInodeUnit inode_page[128];
} __OSInode;
typedef struct
{
/* 0x0 */ u32 repaired;
/* 0x4 */ u32 random;
/* 0x8 */ u64 serial_mid;
/* 0x10 */ u64 serial_low;
/* 0x18 */ u16 deviceid;
/* 0x1A */ u8 banks;
/* 0x1B */ u8 version;
/* 0x1C */ u16 checksum;
/* 0x1E */ u16 inverted_checksum;
} __OSPackId;
typedef struct
{
/* 0x0 */ u8 txsize;
/* 0x1 */ u8 rxsize;
/* 0x2 */ u8 cmd;
/* 0x3 */ u8 address;
/* 0x4 */ u8 data[EEPROM_BLOCK_SIZE];
} __OSContEepromFormat;
#endif /* defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) */
/**************************************************************************
*
* Global definitions
*
*/
/*
* Controllers number
*/
#ifndef _HW_VERSION_1
#define MAXCONTROLLERS 4
#else
#define MAXCONTROLLERS 6
#endif
/* controller errors */
#define CONT_NO_RESPONSE_ERROR 0x8
#define CONT_OVERRUN_ERROR 0x4
#ifdef _HW_VERSION_1
#define CONT_FRAME_ERROR 0x2
#define CONT_COLLISION_ERROR 0x1
#endif
/* Controller type */
#define CONT_ABSOLUTE 0x0001
#define CONT_RELATIVE 0x0002
#define CONT_JOYPORT 0x0004
#define CONT_EEPROM 0x8000
#define CONT_EEP16K 0x4000
#define CONT_TYPE_MASK 0x1f07
#define CONT_TYPE_NORMAL 0x0005
#define CONT_TYPE_MOUSE 0x0002
#define CONT_TYPE_VOICE 0x0100
/* Controller status */
#define CONT_CARD_ON 0x01
#define CONT_CARD_PULL 0x02
#define CONT_ADDR_CRC_ER 0x04
#define CONT_EEPROM_BUSY 0x80
/* Buttons */
#define CONT_A 0x8000
#define CONT_B 0x4000
#define CONT_G 0x2000
#define CONT_START 0x1000
#define CONT_UP 0x0800
#define CONT_DOWN 0x0400
#define CONT_LEFT 0x0200
#define CONT_RIGHT 0x0100
#define CONT_L 0x0020
#define CONT_R 0x0010
#define CONT_E 0x0008
#define CONT_D 0x0004
#define CONT_C 0x0002
#define CONT_F 0x0001
/* Nintendo's official button names */
#define A_BUTTON CONT_A
#define B_BUTTON CONT_B
#define L_TRIG CONT_L
#define R_TRIG CONT_R
#define Z_TRIG CONT_G
#define START_BUTTON CONT_START
#define U_JPAD CONT_UP
#define L_JPAD CONT_LEFT
#define R_JPAD CONT_RIGHT
#define D_JPAD CONT_DOWN
#define U_CBUTTONS CONT_E
#define L_CBUTTONS CONT_C
#define R_CBUTTONS CONT_F
#define D_CBUTTONS CONT_D
/* Controller error number */
#define CONT_ERR_NO_CONTROLLER PFS_ERR_NOPACK /* 1 */
#define CONT_ERR_CONTRFAIL CONT_OVERRUN_ERROR /* 4 */
#define CONT_ERR_INVALID PFS_ERR_INVALID /* 5 */
#define CONT_ERR_DEVICE PFS_ERR_DEVICE /* 11 */
#define CONT_ERR_NOT_READY 12
#define CONT_ERR_VOICE_MEMORY 13
#define CONT_ERR_VOICE_WORD 14
#define CONT_ERR_VOICE_NO_RESPONSE 15
#define CONT_CMD_REQUEST_STATUS 0
#define CONT_CMD_READ_BUTTON 1
#define CONT_CMD_READ_MEMPACK 2
#define CONT_CMD_WRITE_MEMPACK 3
#define CONT_CMD_READ_EEPROM 4
#define CONT_CMD_WRITE_EEPROM 5
#define CONT_CMD_RESET 0xff
#define CONT_CMD_REQUEST_STATUS_TX 1
#define CONT_CMD_READ_BUTTON_TX 1
#define CONT_CMD_READ_MEMPACK_TX 3
#define CONT_CMD_WRITE_MEMPACK_TX 35
#define CONT_CMD_READ_EEPROM_TX 2
#define CONT_CMD_WRITE_EEPROM_TX 10
#define CONT_CMD_RESET_TX 1
#define CONT_CMD_REQUEST_STATUS_RX 3
#define CONT_CMD_READ_BUTTON_RX 4
#define CONT_CMD_READ_MEMPACK_RX 33
#define CONT_CMD_WRITE_MEMPACK_RX 1
#define CONT_CMD_READ_EEPROM_RX 8
#define CONT_CMD_WRITE_EEPROM_RX 1
#define CONT_CMD_RESET_RX 3
#define CONT_CMD_NOP 0xff
#define CONT_CMD_END 0xfe //indicates end of a command
#define CONT_CMD_EXE 1 //set pif ram status byte to this to do a command
#define DIR_STATUS_EMPTY 0
#define DIR_STATUS_UNKNOWN 1
#define DIR_STATUS_OCCUPIED 2
#define CHNL_ERR(format) ((format.rxsize & CHNL_ERR_MASK) >> 4)
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
/**************************************************************************
*
* Macro definitions
*
*/
/**************************************************************************
*
* Extern variables
*
*/
/**************************************************************************
*
* Function prototypes
*
*/
/* Controller interface */
extern s32 osContInit(OSMesgQueue *, u8 *, OSContStatus *);
extern s32 osContReset(OSMesgQueue *, OSContStatus *);
extern s32 osContStartQuery(OSMesgQueue *);
extern s32 osContStartReadData(OSMesgQueue *);
#ifndef _HW_VERSION_1
extern s32 osContSetCh(u8);
#endif
extern void osContGetQuery(OSContStatus *);
extern void osContGetReadData(OSContPad *);
#endif /* defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) */
#ifdef _LANGUAGE_C_PLUS_PLUS
}
#endif
#endif /* !_OS_CONT_H_ */
src/include/PR/os_eeprom.h
-107
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@@ -1,107 +0,0 @@
/*====================================================================
* os_eeprom.h
*
* Copyright 1995, Silicon Graphics, Inc.
* All Rights Reserved.
*
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Silicon Graphics,
* Inc.; the contents of this file may not be disclosed to third
* parties, copied or duplicated in any form, in whole or in part,
* without the prior written permission of Silicon Graphics, Inc.
*
* RESTRICTED RIGHTS LEGEND:
* Use, duplication or disclosure by the Government is subject to
* restrictions as set forth in subdivision (c)(1)(ii) of the Rights
* in Technical Data and Computer Software clause at DFARS
* 252.227-7013, and/or in similar or successor clauses in the FAR,
* DOD or NASA FAR Supplement. Unpublished - rights reserved under the
* Copyright Laws of the United States.
*====================================================================*/
/*---------------------------------------------------------------------*
Copyright (C) 1998 Nintendo. (Originated by SGI)
$RCSfile: os_eeprom.h,v $
$Revision: 1.1 $
$Date: 1998/10/09 08:01:06 $
*---------------------------------------------------------------------*/
#ifndef _OS_EEPROM_H_
#define _OS_EEPROM_H_
#ifdef _LANGUAGE_C_PLUS_PLUS
extern "C" {
#endif
#include <PR/ultratypes.h>
#include "os_message.h"
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
/**************************************************************************
*
* Type definitions
*
*/
#endif /* defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) */
/**************************************************************************
*
* Global definitions
*
*/
/* EEPROM TYPE */
#define EEPROM_TYPE_4K 0x01
#define EEPROM_TYPE_16K 0x02
/* definition for EEPROM */
#define EEPROM_MAXBLOCKS 64
#define EEP16K_MAXBLOCKS 256
#define EEPROM_BLOCK_SIZE 8
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
/**************************************************************************
*
* Macro definitions
*
*/
/**************************************************************************
*
* Extern variables
*
*/
/**************************************************************************
*
* Function prototypes
*
*/
/* EEPROM interface */
extern s32 osEepromProbe(OSMesgQueue *);
extern s32 osEepromRead(OSMesgQueue *, u8, u8 *);
extern s32 osEepromWrite(OSMesgQueue *, u8, u8 *);
extern s32 osEepromLongRead(OSMesgQueue *, u8, u8 *, int);
extern s32 osEepromLongWrite(OSMesgQueue *, u8, u8 *, int);
#endif /* defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) */
#ifdef _LANGUAGE_C_PLUS_PLUS
}
#endif
#endif /* !_OS_EEPROM_H_ */
src/include/PR/os_exception.h
-119
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@@ -1,119 +0,0 @@
/*====================================================================
* os_exception.h
*
* Copyright 1995, Silicon Graphics, Inc.
* All Rights Reserved.
*
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Silicon Graphics,
* Inc.; the contents of this file may not be disclosed to third
* parties, copied or duplicated in any form, in whole or in part,
* without the prior written permission of Silicon Graphics, Inc.
*
* RESTRICTED RIGHTS LEGEND:
* Use, duplication or disclosure by the Government is subject to
* restrictions as set forth in subdivision (c)(1)(ii) of the Rights
* in Technical Data and Computer Software clause at DFARS
* 252.227-7013, and/or in similar or successor clauses in the FAR,
* DOD or NASA FAR Supplement. Unpublished - rights reserved under the
* Copyright Laws of the United States.
*====================================================================*/
/*---------------------------------------------------------------------*
Copyright (C) 1998 Nintendo. (Originated by SGI)
$RCSfile: os_exception.h,v $
$Revision: 1.1 $
$Date: 1998/10/09 08:01:07 $
*---------------------------------------------------------------------*/
#ifndef _OS_EXCEPTION_H_
#define _OS_EXCEPTION_H_
#ifdef _LANGUAGE_C_PLUS_PLUS
extern "C" {
#endif
#include <PR/ultratypes.h>
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
/**************************************************************************
*
* Type definitions
*
*/
typedef u32 OSIntMask;
typedef u32 OSHWIntr;
#endif /* defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) */
/**************************************************************************
*
* Global definitions
*
*/
/* Flags for debugging purpose */
#define OS_FLAG_CPU_BREAK 1 /* Break exception has occurred */
#define OS_FLAG_FAULT 2 /* CPU fault has occurred */
/* Interrupt masks */
#define OS_IM_NONE 0x00000001
#define OS_IM_SW1 0x00000501
#define OS_IM_SW2 0x00000601
#define OS_IM_CART 0x00000c01
#define OS_IM_PRENMI 0x00001401
#define OS_IM_RDBWRITE 0x00002401
#define OS_IM_RDBREAD 0x00004401
#define OS_IM_COUNTER 0x00008401
#define OS_IM_CPU 0x0000ff01
#define OS_IM_SP 0x00010401
#define OS_IM_SI 0x00020401
#define OS_IM_AI 0x00040401
#define OS_IM_VI 0x00080401
#define OS_IM_PI 0x00100401
#define OS_IM_DP 0x00200401
#define OS_IM_ALL 0x003fff01
#define RCP_IMASK 0x003f0000
#define RCP_IMASKSHIFT 16
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
/**************************************************************************
*
* Macro definitions
*
*/
/**************************************************************************
*
* Extern variables
*
*/
/**************************************************************************
*
* Function prototypes
*
*/
/* Interrupt operations */
extern OSIntMask osGetIntMask(void);
extern OSIntMask osSetIntMask(OSIntMask);
#endif /* defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) */
#ifdef _LANGUAGE_C_PLUS_PLUS
}
#endif
#endif /* !_OS_EXCEPTION_H_ */
src/include/PR/os_internal.h
-18
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@@ -1,18 +0,0 @@
#ifndef _ULTRA64_OS_INTERNAL_H_
#define _ULTRA64_OS_INTERNAL_H_
/* Internal functions used by the operating system */
/* Do not include this header in application code */
/* Variables */
//extern u64 osClockRate;
/* Functions */
/*u32 __osProbeTLB(void *);
u32 __osDisableInt(void);
void __osRestoreInt(u32);*/
OSThread *__osGetCurrFaultedThread(void);
#endif
src/include/PR/os_libc.h
-98
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@@ -1,98 +0,0 @@
/*====================================================================
* os_libc.h
*
* Copyright 1995, Silicon Graphics, Inc.
* All Rights Reserved.
*
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Silicon Graphics,
* Inc.; the contents of this file may not be disclosed to third
* parties, copied or duplicated in any form, in whole or in part,
* without the prior written permission of Silicon Graphics, Inc.
*
* RESTRICTED RIGHTS LEGEND:
* Use, duplication or disclosure by the Government is subject to
* restrictions as set forth in subdivision (c)(1)(ii) of the Rights
* in Technical Data and Computer Software clause at DFARS
* 252.227-7013, and/or in similar or successor clauses in the FAR,
* DOD or NASA FAR Supplement. Unpublished - rights reserved under the
* Copyright Laws of the United States.
*====================================================================*/
/*---------------------------------------------------------------------*
Copyright (C) 1998 Nintendo. (Originated by SGI)
$RCSfile: os_libc.h,v $
$Revision: 1.3 $
$Date: 1999/07/13 01:43:47 $
*---------------------------------------------------------------------*/
#ifndef _OS_LIBC_H_
#define _OS_LIBC_H_
#ifdef _LANGUAGE_C_PLUS_PLUS
extern "C" {
#endif
#include <PR/ultratypes.h>
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
/**************************************************************************
*
* Type definitions
*
*/
#endif /* defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) */
/**************************************************************************
*
* Global definitions
*
*/
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
/**************************************************************************
*
* Macro definitions
*
*/
/**************************************************************************
*
* Extern variables
*
*/
/**************************************************************************
*
* Function prototypes
*
*/
/* byte string operations */
extern void bcopy(const void *, void *, int);
extern int bcmp(const void *, const void *, int);
extern void bzero(void *, int);
/* Printf */
extern int sprintf(char *s, const char *fmt, ...);
extern void osSyncPrintf(const char *fmt, ...);
#endif /* defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) */
#ifdef _LANGUAGE_C_PLUS_PLUS
}
#endif
#endif /* !_OS_LIBC_H_ */
src/include/PR/os_message.h
-178
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@@ -1,178 +0,0 @@
/*====================================================================
* os_message.h
*
* Copyright 1995, Silicon Graphics, Inc.
* All Rights Reserved.
*
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Silicon Graphics,
* Inc.; the contents of this file may not be disclosed to third
* parties, copied or duplicated in any form, in whole or in part,
* without the prior written permission of Silicon Graphics, Inc.
*
* RESTRICTED RIGHTS LEGEND:
* Use, duplication or disclosure by the Government is subject to
* restrictions as set forth in subdivision (c)(1)(ii) of the Rights
* in Technical Data and Computer Software clause at DFARS
* 252.227-7013, and/or in similar or successor clauses in the FAR,
* DOD or NASA FAR Supplement. Unpublished - rights reserved under the
* Copyright Laws of the United States.
*====================================================================*/
/*---------------------------------------------------------------------*
Copyright (C) 1998 Nintendo. (Originated by SGI)
$RCSfile: os_message.h,v $
$Revision: 1.1 $
$Date: 1998/10/09 08:01:15 $
*---------------------------------------------------------------------*/
#ifndef _OS_MESSAGE_H_
#define _OS_MESSAGE_H_
#ifdef _LANGUAGE_C_PLUS_PLUS
extern "C" {
#endif
#include <PR/ultratypes.h>
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
/**************************************************************************
*
* Type definitions
*
*/
typedef u32 OSEvent;
/*
* Structure for message
*/
typedef void * OSMesg;
/*
* Structure for message queue
*/
typedef struct OSMesgQueue_s {
OSThread *mtqueue; /* Queue to store threads blocked
on empty mailboxes (receive) */
OSThread *fullqueue; /* Queue to store threads blocked
on full mailboxes (send) */
s32 validCount; /* Contains number of valid message */
s32 first; /* Points to first valid message */
s32 msgCount; /* Contains total # of messages */
OSMesg *msg; /* Points to message buffer array */
} OSMesgQueue;
typedef struct __OSEventState {
OSMesgQueue *messageQueue;
OSMesg message;
} __OSEventState;
#endif /* defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) */
/**************************************************************************
*
* Global definitions
*
*/
/* Events */
#ifdef _FINALROM
#define OS_NUM_EVENTS 15
#else
#define OS_NUM_EVENTS 23
#endif
#define OS_EVENT_SW1 0 /* CPU SW1 interrupt */
#define OS_EVENT_SW2 1 /* CPU SW2 interrupt */
#define OS_EVENT_CART 2 /* Cartridge interrupt: used by rmon */
#define OS_EVENT_COUNTER 3 /* Counter int: used by VI/Timer Mgr */
#define OS_EVENT_SP 4 /* SP task done interrupt */
#define OS_EVENT_SI 5 /* SI (controller) interrupt */
#define OS_EVENT_AI 6 /* AI interrupt */
#define OS_EVENT_VI 7 /* VI interrupt: used by VI/Timer Mgr */
#define OS_EVENT_PI 8 /* PI interrupt: used by PI Manager */
#define OS_EVENT_DP 9 /* DP full sync interrupt */
#define OS_EVENT_CPU_BREAK 10 /* CPU breakpoint: used by rmon */
#define OS_EVENT_SP_BREAK 11 /* SP breakpoint: used by rmon */
#define OS_EVENT_FAULT 12 /* CPU fault event: used by rmon */
#define OS_EVENT_THREADSTATUS 13 /* CPU thread status: used by rmon */
#define OS_EVENT_PRENMI 14 /* Pre NMI interrupt */
#ifndef _FINALROM
#define OS_EVENT_RDB_READ_DONE 15 /* RDB read ok event: used by rmon */
#define OS_EVENT_RDB_LOG_DONE 16 /* read of log data complete */
#define OS_EVENT_RDB_DATA_DONE 17 /* read of hostio data complete */
#define OS_EVENT_RDB_REQ_RAMROM 18 /* host needs ramrom access */
#define OS_EVENT_RDB_FREE_RAMROM 19 /* host is done with ramrom access */
#define OS_EVENT_RDB_DBG_DONE 20
#define OS_EVENT_RDB_FLUSH_PROF 21
#define OS_EVENT_RDB_ACK_PROF 22
#endif
/* Flags to turn blocking on/off when sending/receiving message */
#define OS_MESG_NOBLOCK 0
#define OS_MESG_BLOCK 1
/*
* I/O message types
*/
#define OS_MESG_TYPE_BASE (10)
#define OS_MESG_TYPE_LOOPBACK (OS_MESG_TYPE_BASE+0)
#define OS_MESG_TYPE_DMAREAD (OS_MESG_TYPE_BASE+1)
#define OS_MESG_TYPE_DMAWRITE (OS_MESG_TYPE_BASE+2)
#define OS_MESG_TYPE_VRETRACE (OS_MESG_TYPE_BASE+3)
#define OS_MESG_TYPE_COUNTER (OS_MESG_TYPE_BASE+4)
#define OS_MESG_TYPE_EDMAREAD (OS_MESG_TYPE_BASE+5)
#define OS_MESG_TYPE_EDMAWRITE (OS_MESG_TYPE_BASE+6)
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
/**************************************************************************
*
* Macro definitions
*
*/
/* Get count of valid messages in queue */
#define MQ_GET_COUNT(mq) ((mq)->validCount)
/* Figure out if message queue is empty or full */
#define MQ_IS_EMPTY(mq) (MQ_GET_COUNT(mq) == 0)
#define MQ_IS_FULL(mq) (MQ_GET_COUNT(mq) >= (mq)->msgCount)
/**************************************************************************
*
* Extern variables
*
*/
/**************************************************************************
*
* Function prototypes
*
*/
/* Message operations */
extern void osCreateMesgQueue(OSMesgQueue *, OSMesg *, s32);
extern s32 osSendMesg(OSMesgQueue *, OSMesg, s32);
extern s32 osJamMesg(OSMesgQueue *, OSMesg, s32);
extern s32 osRecvMesg(OSMesgQueue *, OSMesg *, s32);
/* Event operations */
extern void osSetEventMesg(OSEvent, OSMesgQueue *, OSMesg);
#endif /* defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) */
#ifdef _LANGUAGE_C_PLUS_PLUS
}
#endif
#endif /* !_OS_MESSAGE_H_ */
src/include/PR/os_misc.h
-132
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@@ -1,132 +0,0 @@
#ifndef _ULTRA64_OS_MISC_H_
#define _ULTRA64_OS_MISC_H_
/* float properties */
#define _D0 0
#define _DBIAS 0x3ff
#define _DLONG 1
#define _DOFF 4
#define _FBIAS 0x7e
#define _FOFF 7
#define _FRND 1
#define _LBIAS 0x3ffe
#define _LOFF 15
/* integer properties */
#define _C2 1
#define _CSIGN 1
#define _ILONG 0
#define _MBMAX 8
#define NAN 2
#define INF 1
#define FINITE -1
#define _DFRAC ((1 << _DOFF) - 1)
#define _DMASK (0x7fff & ~_DFRAC)
#define _DMAX ((1 << (15 - _DOFF)) - 1)
#define _DNAN (0x8000 | _DMAX << _DOFF | 1 << (_DOFF - 1))
#define _DSIGN 0x8000
#define _D1 1 /* big-endian order */
#define _D2 2
#define _D3 3
#define FLAGS_SPACE 1
#define FLAGS_PLUS 2
#define FLAGS_MINUS 4
#define FLAGS_HASH 8
#define FLAGS_ZERO 16
#define BLOCKSIZE 32
#define ARRLEN(x) ((s32)(sizeof(x) / sizeof(x[0])))
#define ERRCK(fn) \
ret = fn; \
if (ret != 0) \
return ret;
typedef struct {
union {
/* 00 */ long long s64;
double f64;
} value;
/* 08 */ char *buff;
/* 0c */ int n0;
/* 10 */ int num_leading_zeros;
/* 14 */ int part2_len;
/* 18 */ int num_mid_zeros;
/* 1c */ int part3_len;
/* 20 */ int num_trailing_zeros;
/* 24 */ int precision;
/* 28 */ int width;
/* 2c */ unsigned int size;
/* 30 */ unsigned int flags;
/* 34 */ char length;
} printf_struct;
typedef char *va_list;
#define _FP 1
#define _INT 0
#define _STRUCT 2
#define _VA_FP_SAVE_AREA 0x10
#define _VA_ALIGN(p, a) (((unsigned int)(((char *)p) + ((a) > 4 ? (a) : 4) - 1)) & -((a) > 4 ? (a) : 4))
#define va_start(vp, parmN) (vp = ((va_list)&parmN + sizeof(parmN)))
#define __va_stack_arg(list, mode) \
( \
((list) = (char *)_VA_ALIGN(list, __builtin_alignof(mode)) + \
_VA_ALIGN(sizeof(mode), 4)), \
(((char *)list) - (_VA_ALIGN(sizeof(mode), 4) - sizeof(mode))))
#define __va_double_arg(list, mode) \
( \
(((long)list & 0x1) /* 1 byte aligned? */ \
? (list = (char *)((long)list + 7), (char *)((long)list - 6 - _VA_FP_SAVE_AREA)) \
: (((long)list & 0x2) /* 2 byte aligned? */ \
? (list = (char *)((long)list + 10), (char *)((long)list - 24 - _VA_FP_SAVE_AREA)) \
: __va_stack_arg(list, mode))))
#define va_arg(list, mode) ((mode *)(((__builtin_classof(mode) == _FP && \
__builtin_alignof(mode) == sizeof(double)) \
? __va_double_arg(list, mode) \
: __va_stack_arg(list, mode))))[-1]
#define va_end(__list)
#define EEPROM_MAXBLOCKS 64
#define EEP16K_MAXBLOCKS 256
#define EEPROM_BLOCK_SIZE 8
/*
* PI/EPI
*/
#define PI_DOMAIN1 0
#define PI_DOMAIN2 1
#define OS_CLOCK_RATE 62500000LL
#define OS_CPU_COUNTER (OS_CLOCK_RATE*3/4)
#define OS_NSEC_TO_CYCLES(n) (((u64)(n)*(OS_CPU_COUNTER/15625000LL))/(1000000000LL/15625000LL))
#define OS_USEC_TO_CYCLES(n) (((u64)(n)*(OS_CPU_COUNTER/15625LL))/(1000000LL/15625LL))
#define OS_CYCLES_TO_NSEC(c) (((u64)(c)*(1000000000LL/15625000LL))/(OS_CPU_COUNTER/15625000LL))
#define OS_CYCLES_TO_USEC(c) (((u64)(c)*(1000000LL/15625LL))/(OS_CPU_COUNTER/15625LL))
#define LEO_BLOCK_MODE 1
#define LEO_TRACK_MODE 2
#define LEO_SECTOR_MODE 3
/* Miscellaneous OS functions */
void osInitialize(void);
u32 osGetCount(void);
u32 osVirtualToPhysical(void *);
f32 cosf(f32 arg0);
f32 sinf(f32 arg0);
f32 sqrtf(f32 arg0);
void *memcpy(void *, const void *, size_t);
size_t strlen(const char *s);
char *strchr(const char *s, int c);
#endif
src/include/PR/os_pfs.h
-220
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@@ -1,220 +0,0 @@
/*====================================================================
* os_pfs.h
*
* Copyright 1995, Silicon Graphics, Inc.
* All Rights Reserved.
*
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Silicon Graphics,
* Inc.; the contents of this file may not be disclosed to third
* parties, copied or duplicated in any form, in whole or in part,
* without the prior written permission of Silicon Graphics, Inc.
*
* RESTRICTED RIGHTS LEGEND:
* Use, duplication or disclosure by the Government is subject to
* restrictions as set forth in subdivision (c)(1)(ii) of the Rights
* in Technical Data and Computer Software clause at DFARS
* 252.227-7013, and/or in similar or successor clauses in the FAR,
* DOD or NASA FAR Supplement. Unpublished - rights reserved under the
* Copyright Laws of the United States.
*====================================================================*/
/*---------------------------------------------------------------------*
Copyright (C) 1998 Nintendo. (Originated by SGI)
$RCSfile: os_pfs.h,v $
$Revision: 1.1 $
$Date: 1998/10/09 08:01:05 $
*---------------------------------------------------------------------*/
#ifndef _OS_PFS_H_
#define _OS_PFS_H_
#ifdef _LANGUAGE_C_PLUS_PLUS
extern "C" {
#endif
#include <PR/ultratypes.h>
#include "os_message.h"
/**************************************************************************
*
* Type definitions
*
*/
typedef struct {
int status;
OSMesgQueue *queue;
int channel;
u8 id[32];
u8 label[32];
int version;
int dir_size;
int inode_table; /* block location */
int minode_table; /* mirrioring inode_table */
int dir_table; /* block location */
int inode_start_page; /* page # */
u8 banks;
u8 activebank;
} OSPfs;
typedef struct {
u32 file_size; /* bytes */
u32 game_code;
u16 company_code;
char ext_name[4];
char game_name[16];
} OSPfsState;
typedef struct {
u16 fixed1; /* Fixed data (0x00, 0xc3) */
u16 start_address; /* Program start address */
u8 nintendo_chr[0x30]; /* "Nintendo" character data */
u8 game_title[16]; /* Game title */
u16 company_code; /* Company code */
u8 body_code; /* Body code */
u8 cart_type; /* Game pak type */
u8 rom_size; /* ROM size */
u8 ram_size; /* RAM size */
u8 country_code; /* country code */
u8 fixed_data; /* fixed data(0x33) */
u8 version; /* Mask ROM version number */
u8 isum; /* Complement check */
u16 sum; /* Sum check */
} OSGbpakId;
/**************************************************************************
*
* Global definitions
*
*/
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
#define PFS_ERR_NOPACK 1 /* no memory card is plugged */
#define PFS_ERR_NEW_PACK 2 /* ram pack has been changed to a different one */
#define PFS_ERR_INCONSISTENT 3 /* need to run Pfschecker */
#define PFS_ERR_CONTRFAIL 4
#define PFS_ERR_INVALID 5 /* invalid parameter or file not exist */
#define PFS_ERR_BAD_DATA 6 /* the data read from pack are bad */
#define PFS_DATA_FULL 7 /* no free pages on ram pack */
#define PFS_DIR_FULL 8 /* no free directories on ram pack */
#define PFS_ERR_EXIST 9 /* file exists */
#define PFS_ERR_ID_FATAL 10 /* dead ram pack */
#define PFS_ERR_DEVICE 11 /* wrong device type */
#define PFS_ERR_NO_GBCART 12 /* no gb cartridge (64GB-PAK) */
#define PFS_ERR_NEW_GBCART 13 /* gb cartridge may be changed */
#define OS_PFS_VERSION 0x0200
#define OS_PFS_VERSION_HI (OS_PFS_VERSION >> 8)
#define OS_PFS_VERSION_LO (OS_PFS_VERSION & 255)
#define OS_GBPAK_POWER 0x01
#define OS_GBPAK_RSTB_DETECTION 0x04
#define OS_GBPAK_RSTB_STATUS 0x08
#define OS_GBPAK_GBCART_PULL 0x40
#define OS_GBPAK_GBCART_ON 0x80
#define OS_GBPAK_POWER_OFF 0
#define OS_GBPAK_POWER_ON 1
#define PFS_FILE_NAME_LEN 16
#define PFS_FILE_EXT_LEN 4
#define BLOCKSIZE 32 /* bytes */
#define PFS_ONE_PAGE 8 /* blocks */
#define PFS_MAX_BANKS 62
#define PFS_LABEL_AREA 7
#define PFS_INODE_SIZE_PER_PAGE 128
#define PFS_PAGE_NOT_USED 3
#define PFS_WRITTEN 2
#define PFS_PAGE_SIZE (BLOCKSIZE * PFS_ONE_PAGE)
#define PFS_READ 0
#define PFS_WRITE 1
#define PFS_CREATE 2
#define PFS_INITIALIZED 0x01
#define PFS_CORRUPTED 0x02
#define PFS_ID_BROKEN 0x04
#define PFS_MOTOR_INITIALIZED 0x08
#define PFS_GBPAK_INITIALIZED 0x10
/**************************************************************************
*
* Macro definitions
*
*/
#define osMotorStop(pfs) osMotorAccess(pfs, 0)
#define osMotorStart(pfs) osMotorAccess(pfs, 1)
#define SET_ACTIVEBANK_TO_ZERO \
if (pfs->activebank != 0) \
{ \
pfs->activebank = 0; \
ERRCK(__osPfsSelectBank(pfs)) \
}
#define PFS_CHECK_ID \
if (__osCheckId(pfs) == PFS_ERR_NEW_PACK) \
return PFS_ERR_NEW_PACK;
#define PFS_CHECK_STATUS \
if ((pfs->status & PFS_INITIALIZED) == 0) \
return PFS_ERR_INVALID;
#define PFS_GET_STATUS \
__osSiGetAccess(); \
ret = __osPfsGetStatus(queue, channel); \
__osSiRelAccess(); \
if (ret != 0) \
return ret;
/**************************************************************************
*
* Extern variables
*
*/
/**************************************************************************
*
* Function prototypes
*
*/
s32 osPfsIsPlug(OSMesgQueue *, u8 *);
s32 osPfsAllocateFile(OSPfs *pfs, u16 company_code, u32 game_code, char *game_name, char *ext_name, s32 num_bytes, s32 *file_no);
s32 osPfsFindFile(OSPfs *pfs, u16 company_code, u32 game_code, char *game_name, char *ext_name, s32 *file_no);
s32 osPfsDeleteFile(OSPfs *pfs, u16 company_code, u32 game_code, char *game_name, char *ext_name);
s32 osPfsFileState(OSPfs *pfs, s32 file_no, OSPfsState *state);
s32 osPfsReadWriteFile(OSPfs* pfs, s32 fileNo, u8 flag, s32 offset, s32 size, u8* data);
s32 osPfsFreeBlocks(OSPfs* pfs, s32 *bytes_not_used);
s32 osPfsReSizeFile(OSPfs *pfs, u16 company_code, u32 game_code, u8 *game_name, u8 *ext_name, u32 numbytes);
#if VERSION >= VERSION_NTSC_1_0
s32 osPfsInitPak(OSMesgQueue *mq, OSPfs *pfs, s32 channel, s32 *arg3);
#else
s32 osPfsInitPak(OSMesgQueue *mq, OSPfs *pfs, s32 channel);
#endif
s32 osMotorAccess(OSPfs *pfs, u32 vibrate);
void osSetUpMempakWrite(s32 channel, OSPifRam* buf);
s32 osMotorProbe(OSMesgQueue *mq, OSPfs *pfs, s32 channel);
s32 osGbpakCheckConnector(OSPfs *pfs, u8 *status);
s32 osGbpakGetStatus(OSPfs *pfs, u8 *status);
s32 osGbpakInit(OSMesgQueue *siMessegeQ, OSPfs *pfs, s32 channel);
s32 osGbpakPower(OSPfs *pfs, s32 flag);
s32 osGbpakReadId(OSPfs *pfs, OSGbpakId *id, u8 *status);
s32 osGbpakReadWrite(OSPfs *pfs, u16 flag, u16 address, u8 *buffer, u16 size);
#endif /* defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) */
#ifdef _LANGUAGE_C_PLUS_PLUS
}
#endif
#endif /* !_OS_PFS_H_ */
src/include/PR/os_pi.h
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#ifndef _ULTRA64_PI_H_
#define _ULTRA64_PI_H_
/* Ultra64 Parallel Interface */
/* Types */
typedef struct
{
u32 errStatus;
void *dramAddr;
void *C2Addr;
u32 sectorSize;
u32 C1ErrNum;
u32 C1ErrSector[4];
} __OSBlockInfo;
typedef struct
{
u32 cmdType;
u16 transferMode;
u16 blockNum;
s32 sectorNum;
u32 devAddr;
u32 bmCtlShadow;
u32 seqCtlShadow;
__OSBlockInfo block[2];
} __OSTranxInfo;
typedef struct OSPiHandle_s
{
struct OSPiHandle_s *next;
u8 type;
u8 latency;
u8 pageSize;
u8 relDuration;
u8 pulse;
u8 domain;
u32 baseAddress;
u32 speed;
__OSTranxInfo transferInfo;
} OSPiHandle;
typedef struct
{
u8 type;
u32 address;
} OSPiInfo;
typedef struct
{
u16 type;
u8 pri;
u8 status;
OSMesgQueue *retQueue;
} OSIoMesgHdr;
typedef struct
{
/*0x00*/ OSIoMesgHdr hdr;
/*0x08*/ void *dramAddr;
/*0x0C*/ u32 devAddr;
/*0x10*/ u32 size;
OSPiHandle *piHandle; //from the official definition
} OSIoMesg;
typedef struct {
s32 active; /* Status flag */
OSThread *thread; /* Calling thread */
OSMesgQueue *cmdQueue; /* Command queue */
OSMesgQueue *evtQueue; /* Event queue */
OSMesgQueue *acsQueue; /* Access queue */
/* Raw DMA routine */
s32 (*dma)(s32, u32, void *, u32);
s32 (*edma)(OSPiHandle *, s32, u32, void *, u32);
} OSDevMgr;
/* Definitions */
#define OS_READ 0 // device -> RDRAM
#define OS_WRITE 1 // device <- RDRAM
#define OS_MESG_PRI_NORMAL 0
#define OS_MESG_PRI_HIGH 1
#define WAIT_ON_IOBUSY(stat) \
stat = IO_READ(PI_STATUS_REG); \
while (stat & (PI_STATUS_IO_BUSY | PI_STATUS_DMA_BUSY)) \
stat = IO_READ(PI_STATUS_REG);
#define UPDATE_REG(reg, var) \
if (cHandle->var != pihandle->var) \
IO_WRITE(reg, pihandle->var);
#define LEO_BASE_REG 0x05000000
#define LEO_CMD (LEO_BASE_REG + 0x508)
#define LEO_STATUS (LEO_BASE_REG + 0x508)
#define LEO_BM_CTL (LEO_BASE_REG + 0x510)
#define LEO_BM_STATUS (LEO_BASE_REG + 0x510)
#define LEO_SEQ_CTL (LEO_BASE_REG + 0x518)
#define LEO_SEQ_STATUS (LEO_BASE_REG + 0x518)
#define LEO_C2_BUFF (LEO_BASE_REG + 0x000) //C2 Sector Buffer
#define LEO_SECTOR_BUFF (LEO_BASE_REG + 0x400) //Data Sector Buffer
#define LEO_DATA (LEO_BASE_REG + 0x500) //Data
#define LEO_MISC_REG (LEO_BASE_REG + 0x504) //Misc Register
#define LEO_CUR_TK (LEO_BASE_REG + 0x50C) //Current Track
#define LEO_ERR_SECTOR (LEO_BASE_REG + 0x514) //Sector Error Status
#define LEO_CUR_SECTOR (LEO_BASE_REG + 0x51C) //Current Sector
#define LEO_HARD_RESET (LEO_BASE_REG + 0x520) //Hard Reset
#define LEO_C1_S0 (LEO_BASE_REG + 0x524) //C1
#define LEO_HOST_SECBYTE (LEO_BASE_REG + 0x528) //Sector Size (in bytes)
#define LEO_C1_S2 (LEO_BASE_REG + 0x52C) //C1
#define LEO_SEC_BYTE (LEO_BASE_REG + 0x530) //Sectors per Block, Full Size
#define LEO_C1_S4 (LEO_BASE_REG + 0x534) //C1
#define LEO_C1_S6 (LEO_BASE_REG + 0x538) //C1
#define LEO_CUR_ADDR (LEO_BASE_REG + 0x53C) //Current Address?
#define LEO_ID_REG (LEO_BASE_REG + 0x540) //ID
#define LEO_TEST_REG (LEO_BASE_REG + 0x544) //Test Read
#define LEO_TEST_PIN_SEL (LEO_BASE_REG + 0x548) //Test Write
#define LEO_RAM_ADDR (LEO_BASE_REG + 0x580) //Microsequencer RAM
#define LEO_STATUS_PRESENCE_MASK 0xFFFF
#define LEO_STATUS_DATA_REQUEST 0x40000000
#define LEO_STATUS_C2_TRANSFER 0x10000000
#define LEO_STATUS_BUFFER_MANAGER_ERROR 0x08000000
#define LEO_STATUS_BUFFER_MANAGER_INTERRUPT 0x04000000
#define LEO_STATUS_MECHANIC_INTERRUPT 0x02000000
#define LEO_STATUS_DISK_PRESENT 0x01000000
#define LEO_STATUS_BUSY_STATE 0x00800000
#define LEO_STATUS_RESET_STATE 0x00400000
#define LEO_STATUS_MOTOR_NOT_SPINNING 0x00100000
#define LEO_STATUS_HEAD_RETRACTED 0x00080000
#define LEO_STATUS_WRITE_PROTECT_ERROR 0x00040000
#define LEO_STATUS_MECHANIC_ERROR 0x00020000
#define LEO_STATUS_DISK_CHANGE 0x00010000
#define LEO_STATUS_MODE_MASK (LEO_STATUS_MOTOR_NOT_SPINNING | LEO_STATUS_HEAD_RETRACTED)
#define LEO_STATUS_MODE_SLEEP (LEO_STATUS_MOTOR_NOT_SPINNING | LEO_STATUS_HEAD_RETRACTED)
#define LEO_STATUS_MODE_STANDBY (LEO_STATUS_HEAD_RETRACTED)
#define LEO_STATUS_MODE_ACTIVE 0
#define LEO_CUR_TK_INDEX_LOCK 0x60000000
#define LEO_BM_STATUS_RUNNING 0x80000000
#define LEO_BM_STATUS_ERROR 0x04000000
#define LEO_BM_STATUS_MICRO 0x02000000
#define LEO_BM_STATUS_BLOCK 0x01000000
#define LEO_BM_STATUS_C1CORRECTION 0x00800000
#define LEO_BM_STATUS_C1DOUBLE 0x00400000
#define LEO_BM_STATUS_C1SINGLE 0x00200000
#define LEO_BM_STATUS_C1ERROR 0x00010000
#define LEO_BM_CTL_START 0x80000000
#define LEO_BM_CTL_MODE 0x40000000
#define LEO_BM_CTL_IMASK 0x20000000
#define LEO_BM_CTL_RESET 0x10000000
#define LEO_BM_CTL_DISABLE_OR 0x08000000
#define LEO_BM_CTL_DISABLE_C1 0x04000000
#define LEO_BM_CTL_BLOCK 0x02000000
#define LEO_BM_CTL_CLR_MECHANIC_INTR 0x01000000
#define LEO_BM_CTL_CONTROL_MASK 0xFF000000
#define LEO_BM_CTL_SECTOR_MASK 0x00FF0000
#define LEO_BM_CTL_SECTOR_SHIFT 16
#define LEO_CMD_TYPE_0 0
#define LEO_CMD_TYPE_1 1
#define LEO_CMD_TYPE_2 2
#define LEO_ERROR_GOOD 0
#define LEO_ERROR_4 4
#define LEO_ERROR_22 22
#define LEO_ERROR_23 23
#define LEO_ERROR_24 24
#define LEO_ERROR_29 29
/* Functions */
s32 osPiStartDma(OSIoMesg *mb, s32 priority, s32 direction,
u32 devAddr, void *vAddr, u32 nbytes, OSMesgQueue *mq);
void osCreatePiManager(OSPri pri, OSMesgQueue *cmdQ, OSMesg *cmdBuf,
s32 cmdMsgCnt);
OSMesgQueue *osPiGetCmdQueue(void);
s32 osPiWriteIo(u32 devAddr, u32 data);
s32 osPiReadIo(u32 devAddr, u32 *data);
s32 osPiRawStartDma(s32 direction, u32 devAddr, void *dramAddr, u32 size);
s32 osEPiRawStartDma(OSPiHandle *pihandle, s32 direction, u32 devAddr, void *dramAddr, u32 size);
void __osDevMgrMain(void *args);
#endif
src/include/PR/os_rdp.h
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/*====================================================================
* os_rdp.h
*
* Copyright 1995, Silicon Graphics, Inc.
* All Rights Reserved.
*
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Silicon Graphics,
* Inc.; the contents of this file may not be disclosed to third
* parties, copied or duplicated in any form, in whole or in part,
* without the prior written permission of Silicon Graphics, Inc.
*
* RESTRICTED RIGHTS LEGEND:
* Use, duplication or disclosure by the Government is subject to
* restrictions as set forth in subdivision (c)(1)(ii) of the Rights
* in Technical Data and Computer Software clause at DFARS
* 252.227-7013, and/or in similar or successor clauses in the FAR,
* DOD or NASA FAR Supplement. Unpublished - rights reserved under the
* Copyright Laws of the United States.
*====================================================================*/
/*---------------------------------------------------------------------*
Copyright (C) 1998 Nintendo. (Originated by SGI)
$RCSfile: os_rdp.h,v $
$Revision: 1.1 $
$Date: 1998/10/09 08:01:16 $
*---------------------------------------------------------------------*/
#ifndef _OS_RDP_H_
#define _OS_RDP_H_
#ifdef _LANGUAGE_C_PLUS_PLUS
extern "C" {
#endif
#include <PR/ultratypes.h>
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
/**************************************************************************
*
* Type definitions
*
*/
#endif /* defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) */
/**************************************************************************
*
* Global definitions
*
*/
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
/**************************************************************************
*
* Macro definitions
*
*/
/**************************************************************************
*
* Extern variables
*
*/
/**************************************************************************
*
* Function prototypes
*
*/
/* Display processor interface (Dp) */
extern u32 osDpGetStatus(void);
extern void osDpSetStatus(u32);
extern void osDpGetCounters(u32 *);
extern s32 osDpSetNextBuffer(void *, u64);
#endif /* defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) */
#ifdef _LANGUAGE_C_PLUS_PLUS
}
#endif
#endif /* !_OS_RDP_H_ */
src/include/PR/os_thread.h
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#ifndef _ULTRA64_THREAD_H_
#define _ULTRA64_THREAD_H_
/* Recommended priorities for system threads */
#define OS_PRIORITY_MAX 255
#define OS_PRIORITY_VIMGR 254
#define OS_PRIORITY_RMON 250
#define OS_PRIORITY_RMONSPIN 200
#define OS_PRIORITY_PIMGR 150
#define OS_PRIORITY_SIMGR 140
#define OS_PRIORITY_APPMAX 127
#define OS_PRIORITY_IDLE 0
#define OS_STATE_STOPPED 1
#define OS_STATE_RUNNABLE 2
#define OS_STATE_RUNNING 4
#define OS_STATE_WAITING 8
/* Types */
typedef s32 OSPri;
typedef s32 OSId;
typedef union
{
struct {
f32 f_odd2;
f32 f_odd;
f32 f_even2;
f32 f_even;
} f;
} __OSfp;
typedef struct
{
u64 at, v0, v1, a0, a1, a2, a3;
u64 t0, t1, t2, t3, t4, t5, t6, t7;
u64 s0, s1, s2, s3, s4, s5, s6, s7;
u64 t8, t9, gp, sp, s8, ra;
u64 lo, hi;
u32 sr, pc, cause, badvaddr, rcp;
u32 fpcsr;
__OSfp fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14;
__OSfp fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30;
} __OSThreadContext;
typedef struct
{
u32 flag;
u32 count;
u64 time;
} __OSThreadprofile_s;
typedef struct OSThread_s
{
/*0x00*/ struct OSThread_s *next;
/*0x04*/ OSPri priority;
/*0x08*/ struct OSThread_s **queue;
/*0x0C*/ struct OSThread_s *tlnext;
/*0x10*/ u16 state;
/*0x12*/ u16 flags;
/*0x14*/ OSId id;
/*0x18*/ int fp;
/*0x1C*/ __OSThreadprofile_s *thprof;
/*0x20*/ __OSThreadContext context;
} OSThread;
/* Functions */
void osCreateThread(OSThread *thread, OSId id, void (*entry)(void *),
void *arg, void *sp, OSPri pri);
OSId osGetThreadId(OSThread *thread);
OSPri osGetThreadPri(OSThread *thread);
void osSetThreadPri(OSThread *thread, OSPri pri);
void osStartThread(OSThread *thread);
void osStopThread(OSThread *thread);
#endif
src/include/PR/os_time.h
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@@ -1,25 +0,0 @@
#ifndef _ULTRA64_TIME_H_
#define _ULTRA64_TIME_H_
#include <PR/os_message.h>
/* Types */
typedef struct OSTimer_str
{
struct OSTimer_str *next;
struct OSTimer_str *prev;
u64 interval;
u64 remaining;
OSMesgQueue *mq;
OSMesg *msg;
} OSTimer;
typedef u64 OSTime;
/* Functions */
OSTime osGetTime(void);
void osSetTime(OSTime time);
int osSetTimer(OSTimer *t, OSTime value, OSTime interval, OSMesgQueue *mq, OSMesg msg);
#endif
src/include/PR/os_tlb.h
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@@ -1,107 +0,0 @@
/*====================================================================
* os_tlb.h
*
* Copyright 1995, Silicon Graphics, Inc.
* All Rights Reserved.
*
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Silicon Graphics,
* Inc.; the contents of this file may not be disclosed to third
* parties, copied or duplicated in any form, in whole or in part,
* without the prior written permission of Silicon Graphics, Inc.
*
* RESTRICTED RIGHTS LEGEND:
* Use, duplication or disclosure by the Government is subject to
* restrictions as set forth in subdivision (c)(1)(ii) of the Rights
* in Technical Data and Computer Software clause at DFARS
* 252.227-7013, and/or in similar or successor clauses in the FAR,
* DOD or NASA FAR Supplement. Unpublished - rights reserved under the
* Copyright Laws of the United States.
*====================================================================*/
/*---------------------------------------------------------------------*
Copyright (C) 1998 Nintendo. (Originated by SGI)
$RCSfile: os_tlb.h,v $
$Revision: 1.1 $
$Date: 1998/10/09 08:01:20 $
*---------------------------------------------------------------------*/
#ifndef _OS_TLB_H_
#define _OS_TLB_H_
#ifdef _LANGUAGE_C_PLUS_PLUS
extern "C" {
#endif
#include <PR/ultratypes.h>
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
/**************************************************************************
*
* Type definitions
*
*/
typedef u32 OSPageMask;
#endif /* defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) */
/**************************************************************************
*
* Global definitions
*
*/
/*
* Page size argument for TLB routines
*/
#define OS_PM_4K 0x0000000
#define OS_PM_16K 0x0006000
#define OS_PM_64K 0x001e000
#define OS_PM_256K 0x007e000
#define OS_PM_1M 0x01fe000
#define OS_PM_4M 0x07fe000
#define OS_PM_16M 0x1ffe000
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
/**************************************************************************
*
* Macro definitions
*
*/
/**************************************************************************
*
* Extern variables
*
*/
/**************************************************************************
*
* Function prototypes
*
*/
/* TLB management routines */
extern void osMapTLB(s32, OSPageMask, void *, u32, u32, s32);
extern void osMapTLBRdb(void);
extern void osUnmapTLB(s32);
extern void osUnmapTLBAll(void);
extern void osSetTLBASID(s32);
#endif /* defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) */
#ifdef _LANGUAGE_C_PLUS_PLUS
}
#endif
#endif /* !_OS_TLB_H_ */
src/include/PR/os_vi.h
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#ifndef _ULTRA64_VI_H_
#define _ULTRA64_VI_H_
/* Ultra64 Video Interface */
/*
* Video Interface (VI) mode type
*/
#define OS_VI_NTSC_LPN1 0 /* NTSC */
#define OS_VI_NTSC_LPF1 1
#define OS_VI_NTSC_LAN1 2
#define OS_VI_NTSC_LAF1 3
#define OS_VI_NTSC_LPN2 4
#define OS_VI_NTSC_LPF2 5
#define OS_VI_NTSC_LAN2 6
#define OS_VI_NTSC_LAF2 7
#define OS_VI_NTSC_HPN1 8
#define OS_VI_NTSC_HPF1 9
#define OS_VI_NTSC_HAN1 10
#define OS_VI_NTSC_HAF1 11
#define OS_VI_NTSC_HPN2 12
#define OS_VI_NTSC_HPF2 13
#define OS_VI_PAL_LPN1 14 /* PAL */
#define OS_VI_PAL_LPF1 15
#define OS_VI_PAL_LAN1 16
#define OS_VI_PAL_LAF1 17
#define OS_VI_PAL_LPN2 18
#define OS_VI_PAL_LPF2 19
#define OS_VI_PAL_LAN2 20
#define OS_VI_PAL_LAF2 21
#define OS_VI_PAL_HPN1 22
#define OS_VI_PAL_HPF1 23
#define OS_VI_PAL_HAN1 24
#define OS_VI_PAL_HAF1 25
#define OS_VI_PAL_HPN2 26
#define OS_VI_PAL_HPF2 27
#define OS_VI_MPAL_LPN1 28 /* MPAL - mainly Brazil */
#define OS_VI_MPAL_LPF1 29
#define OS_VI_MPAL_LAN1 30
#define OS_VI_MPAL_LAF1 31
#define OS_VI_MPAL_LPN2 32
#define OS_VI_MPAL_LPF2 33
#define OS_VI_MPAL_LAN2 34
#define OS_VI_MPAL_LAF2 35
#define OS_VI_MPAL_HPN1 36
#define OS_VI_MPAL_HPF1 37
#define OS_VI_MPAL_HAN1 38
#define OS_VI_MPAL_HAF1 39
#define OS_VI_MPAL_HPN2 40
#define OS_VI_MPAL_HPF2 41
#define OS_VI_FPAL_LPN1 42 /* FPAL - fullscreen PAL */
#define OS_VI_FPAL_LPF1 43
#define OS_VI_FPAL_LAN1 44
#define OS_VI_FPAL_LAF1 45
#define OS_VI_FPAL_LPN2 46
#define OS_VI_FPAL_LPF2 47
#define OS_VI_FPAL_LAN2 48
#define OS_VI_FPAL_LAF2 49
#define OS_VI_FPAL_HPN1 50
#define OS_VI_FPAL_HPF1 51
#define OS_VI_FPAL_HAN1 52
#define OS_VI_FPAL_HAF1 53
#define OS_VI_FPAL_HPN2 54
#define OS_VI_FPAL_HPF2 55
/* Special Features */
#define OS_VI_GAMMA_ON 0x0001
#define OS_VI_GAMMA_OFF 0x0002
#define OS_VI_GAMMA_DITHER_ON 0x0004
#define OS_VI_GAMMA_DITHER_OFF 0x0008
#define OS_VI_DIVOT_ON 0x0010
#define OS_VI_DIVOT_OFF 0x0020
#define OS_VI_DITHER_FILTER_ON 0x0040
#define OS_VI_DITHER_FILTER_OFF 0x0080
#define OS_VI_GAMMA 0x08
#define OS_VI_GAMMA_DITHER 0x04
#define OS_VI_DIVOT 0x10
#define OS_VI_DITHER_FILTER 0x10000
#define OS_VI_UNK200 0x200
#define OS_VI_UNK100 0x100
#define VI_STATE_01 0x01
#define VI_STATE_XSCALE_UPDATED 0x02
#define VI_STATE_YSCALE_UPDATED 0x04
#define VI_STATE_08 0x08
#define VI_STATE_10 0x10
#define VI_STATE_BLACK 0x20
#define VI_STATE_REPEATLINE 0x40
#define VI_STATE_FADE 0x80
#define VI_STATE_BLACK 0x20
#define VI_CTRL_ANTIALIAS_MODE_3 0x00300 /* Bit [9:8] anti-alias mode */
#define VI_CTRL_ANTIALIAS_MODE_2 0x00200 /* Bit [9:8] anti-alias mode */
#define VI_CTRL_ANTIALIAS_MODE_1 0x00100 /* Bit [9:8] anti-alias mode */
#define VI_SCALE_MASK 0xfff
#define VI_2_10_FPART_MASK 0x3ff
#define VI_SUBPIXEL_SH 0x10
#define BURST(hsync_width, color_width, vsync_width, color_start) \
(hsync_width | (color_width << 8) | (vsync_width << 16) | (color_start << 20))
#define WIDTH(v) v
#define VSYNC(v) v
#define HSYNC(duration, leap) (duration | (leap << 16))
#define LEAP(upper, lower) ((upper << 16) | lower)
#define START(start, end) ((start << 16) | end)
#define FTOFIX(val, i, f) ((u32)(val * (f32)(1 << f)) & ((1 << (i + f)) - 1))
#define F210(val) FTOFIX(val, 2, 10)
#define SCALE(scaleup, off) (F210((1.0f / (f32)scaleup)) | (F210((f32)off) << 16))
#define VCURRENT(v) v //seemingly unused
#define ORIGIN(v) v
#define VINTR(v) v
#define HSTART START
/* Types */
typedef struct
{
u32 ctrl;
u32 width;
u32 burst;
u32 vSync;
u32 hSync;
u32 leap;
u32 hStart;
u32 xScale;
u32 vCurrent;
} OSViCommonRegs;
typedef struct
{
u32 origin;
u32 yScale;
u32 vStart;
u32 vBurst;
u32 vIntr;
} OSViFieldRegs;
typedef struct
{
u8 type;
OSViCommonRegs comRegs;
OSViFieldRegs fldRegs[2];
} OSViMode;
typedef struct
{
/* 0x00 */ u16 unk00; //some kind of flags. swap buffer sets to 0x10
/* 0x02 */ u16 retraceCount;
/* 0x04 */ void* buffer;
/* 0x08 */ OSViMode *unk08;
/* 0x0c */ u32 features;
/* 0x10 */ OSMesgQueue *mq;
/* 0x14 */ OSMesg *msg;
/* 0x18 */ u32 unk18;
/* 0x1c */ u32 unk1c;
/* 0x20 */ u32 unk20;
/* 0x24 */ f32 unk24;
/* 0x28 */ u16 unk28;
/* 0x2c */ u32 unk2c;
} OSViContext;
typedef struct
{
/* 0x0 */ f32 factor;
/* 0x4 */ u16 offset;
/* 0x8 */ u32 scale;
} __OSViScale;
typedef struct
{
/* 0x0 */ u16 state;
/* 0x2 */ u16 retraceCount;
/* 0x4 */ void *framep;
/* 0x8 */ OSViMode *modep;
/* 0xC */ u32 control;
/* 0x10 */ OSMesgQueue *msgq;
/* 0x14 */ OSMesg msg;
/* 0x18 */ __OSViScale x;
/* 0x24 */ __OSViScale y;
} __OSViContext;
void osCreateViManager(OSPri pri);
void osViSetMode(OSViMode *mode);
void osViSetEvent(OSMesgQueue *mq, OSMesg msg, u32 retraceCount);
void osViBlack(u8 active);
void osViSetSpecialFeatures(u32 func);
void osViSwapBuffer(void *vaddr);
void osViSetXScale(f32 scale);
void osViSetYScale(f32 scale);
#define OS_VI_NTSC_LPN1 0 /* NTSC */
#define OS_VI_NTSC_LPF1 1
#define OS_VI_NTSC_LAN1 2
#define OS_VI_NTSC_LAF1 3
#define OS_VI_NTSC_LPN2 4
#define OS_VI_NTSC_LPF2 5
#define OS_VI_NTSC_LAN2 6
#define OS_VI_NTSC_LAF2 7
#define OS_VI_NTSC_HPN1 8
#define OS_VI_NTSC_HPF1 9
#define OS_VI_NTSC_HAN1 10
#define OS_VI_NTSC_HAF1 11
#define OS_VI_NTSC_HPN2 12
#define OS_VI_NTSC_HPF2 13
#define OS_VI_PAL_LPN1 14 /* PAL */
#define OS_VI_PAL_LPF1 15
#define OS_VI_PAL_LAN1 16
#define OS_VI_PAL_LAF1 17
#define OS_VI_PAL_LPN2 18
#define OS_VI_PAL_LPF2 19
#define OS_VI_PAL_LAN2 20
#define OS_VI_PAL_LAF2 21
#define OS_VI_PAL_HPN1 22
#define OS_VI_PAL_HPF1 23
#define OS_VI_PAL_HAN1 24
#define OS_VI_PAL_HAF1 25
#define OS_VI_PAL_HPN2 26
#define OS_VI_PAL_HPF2 27
extern OSViMode osViModeTable[]; /* Global VI mode table */
#endif
src/include/PR/rcp.h
-882
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@@ -1,882 +0,0 @@
#ifndef _RCP_H_
#define _RCP_H_
/**************************************************************************
* *
* Copyright (C) 1995, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
**************************************************************************/
/**************************************************************************
*
* File: rcp.h
*
* This file contains register and bit definitions for RCP memory map.
* $Revision: 1.20 $
* $Date: 1997/07/23 08:35:21 $
* $Source: /disk6/Master/cvsmdev2/PR/include/rcp.h,v $
*
**************************************************************************/
#include <PR/R4300.h>
#include <PR/ultratypes.h>
/**********************************************************************
*
* Here is a quick overview of the RCP memory map:
*
0x0000_0000 .. 0x03ef_ffff RDRAM memory
0x03f0_0000 .. 0x03ff_ffff RDRAM registers
RCP registers (see below)
0x0400_0000 .. 0x040f_ffff SP registers
0x0410_0000 .. 0x041f_ffff DP command registers
0x0420_0000 .. 0x042f_ffff DP span registers
0x0430_0000 .. 0x043f_ffff MI registers
0x0440_0000 .. 0x044f_ffff VI registers
0x0450_0000 .. 0x045f_ffff AI registers
0x0460_0000 .. 0x046f_ffff PI registers
0x0470_0000 .. 0x047f_ffff RI registers
0x0480_0000 .. 0x048f_ffff SI registers
0x0490_0000 .. 0x04ff_ffff unused
0x0500_0000 .. 0x05ff_ffff cartridge domain 2
0x0600_0000 .. 0x07ff_ffff cartridge domain 1
0x0800_0000 .. 0x0fff_ffff cartridge domain 2
0x1000_0000 .. 0x1fbf_ffff cartridge domain 1
0x1fc0_0000 .. 0x1fc0_07bf PIF Boot Rom (1984 bytes)
0x1fc0_07c0 .. 0x1fc0_07ff PIF (JoyChannel) RAM (64 bytes)
0x1fc0_0800 .. 0x1fcf_ffff Reserved
0x1fd0_0000 .. 0x7fff_ffff cartridge domain 1
0x8000_0000 .. 0xffff_ffff external SysAD device
The Indy development board use cartridge domain 1:
0x1000_0000 .. 0x10ff_ffff RAMROM
0x1800_0000 .. 0x1800_0003 GIO interrupt (6 bits valid in 4 bytes)
0x1800_0400 .. 0x1800_0403 GIO sync (6 bits valid in 4 bytes)
0x1800_0800 .. 0x1800_0803 CART interrupt (6 bits valid in 4 bytes)
**************************************************************************/
/*************************************************************************
* RDRAM Memory (Assumes that maximum size is 4 MB)
*/
#define RDRAM_0_START 0x00000000
#define RDRAM_0_END 0x001FFFFF
#define RDRAM_1_START 0x00200000
#define RDRAM_1_END 0x003FFFFF
#define RDRAM_START RDRAM_0_START
#define RDRAM_END RDRAM_1_END
/*************************************************************************
* Address predicates
*/
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
#define IS_RDRAM(x) ((unsigned)(x) >= RDRAM_START && \
(unsigned)(x) < RDRAM_END)
#endif
/*************************************************************************
* RDRAM Registers (0x03f0_0000 .. 0x03ff_ffff)
*/
#define RDRAM_BASE_REG 0x03F00000
#define RDRAM_CONFIG_REG (RDRAM_BASE_REG+0x00)
#define RDRAM_DEVICE_TYPE_REG (RDRAM_BASE_REG+0x00)
#define RDRAM_DEVICE_ID_REG (RDRAM_BASE_REG+0x04)
#define RDRAM_DELAY_REG (RDRAM_BASE_REG+0x08)
#define RDRAM_MODE_REG (RDRAM_BASE_REG+0x0c)
#define RDRAM_REF_INTERVAL_REG (RDRAM_BASE_REG+0x10)
#define RDRAM_REF_ROW_REG (RDRAM_BASE_REG+0x14)
#define RDRAM_RAS_INTERVAL_REG (RDRAM_BASE_REG+0x18)
#define RDRAM_MIN_INTERVAL_REG (RDRAM_BASE_REG+0x1c)
#define RDRAM_ADDR_SELECT_REG (RDRAM_BASE_REG+0x20)
#define RDRAM_DEVICE_MANUF_REG (RDRAM_BASE_REG+0x24)
#define RDRAM_0_DEVICE_ID 0
#define RDRAM_1_DEVICE_ID 1
#define RDRAM_RESET_MODE 0
#define RDRAM_ACTIVE_MODE 1
#define RDRAM_STANDBY_MODE 2
#define RDRAM_LENGTH (2*512*2048)
#define RDRAM_0_BASE_ADDRESS (RDRAM_0_DEVICE_ID*RDRAM_LENGTH)
#define RDRAM_1_BASE_ADDRESS (RDRAM_1_DEVICE_ID*RDRAM_LENGTH)
#define RDRAM_0_CONFIG 0x00000
#define RDRAM_1_CONFIG 0x00400
#define RDRAM_GLOBAL_CONFIG 0x80000
/*************************************************************************
* PIF Physical memory map (total size = 2 KB)
*
* Size Description Mode
* 1FC007FF +-------+-----------------+-----+
* | 64 B | JoyChannel RAM | R/W |
* 1FC007C0 +-------+-----------------+-----+
* |1984 B | Boot ROM | * | * = Reserved
* 1FC00000 +-------+-----------------+-----+
*
*/
#define PIF_ROM_START 0x1FC00000
#define PIF_ROM_END 0x1FC007BF
#define PIF_RAM_START 0x1FC007C0
#define PIF_RAM_END 0x1FC007FF
/*************************************************************************
* Controller channel
* Each game controller channel has 4 error bits that are defined in bit 6-7 of
* the Rx and Tx data size area bytes. Programmers need to clear these bits
* when setting the Tx/Rx size area values for a channel
*/
#define CHNL_ERR_NORESP 0x80 /* Bit 7 (Rx): No response error */
#define CHNL_ERR_OVERRUN 0x40 /* Bit 6 (Rx): Overrun error */
#define CHNL_ERR_FRAME 0x80 /* Bit 7 (Tx): Frame error */
#define CHNL_ERR_COLLISION 0x40 /* Bit 6 (Tx): Collision error */
#define CHNL_ERR_MASK 0xC0 /* Bit 6-7: channel errors */
/*************************************************************************
* External device info
*/
#define DEVICE_TYPE_CART 0 /* ROM cartridge */
#define DEVICE_TYPE_BULK 1 /* ROM bulk */
#define DEVICE_TYPE_64DD 2 /* 64 Disk Drive */
#define DEVICE_TYPE_SRAM 3 /* SRAM */
/*************************************************************************
* SP Memory
*/
#define SP_DMEM_START 0x04000000 /* read/write */
#define SP_DMEM_END 0x04000FFF
#define SP_IMEM_START 0x04001000 /* read/write */
#define SP_IMEM_END 0x04001FFF
/*************************************************************************
* SP CP0 Registers
*/
#define SP_BASE_REG 0x04040000
/* SP memory address (R/W): [11:0] DMEM/IMEM address; [12] 0=DMEM,1=IMEM */
#define SP_MEM_ADDR_REG (SP_BASE_REG+0x00) /* Master */
/* SP DRAM DMA address (R/W): [23:0] RDRAM address */
#define SP_DRAM_ADDR_REG (SP_BASE_REG+0x04) /* Slave */
/* SP read DMA length (R/W): [11:0] length, [19:12] count, [31:20] skip */
/* direction: I/DMEM <- RDRAM */
#define SP_RD_LEN_REG (SP_BASE_REG+0x08) /* R/W: read len */
/* SP write DMA length (R/W): [11:0] length, [19:12] count, [31:20] skip */
/* direction: I/DMEM -> RDRAM */
#define SP_WR_LEN_REG (SP_BASE_REG+0x0C) /* R/W: write len */
/* SP status (R/W): [14:0] valid bits; see below for write/read mode */
#define SP_STATUS_REG (SP_BASE_REG+0x10)
/* SP DMA full (R): [0] valid bit; dma full */
#define SP_DMA_FULL_REG (SP_BASE_REG+0x14)
/* SP DMA busy (R): [0] valid bit; dma busy */
#define SP_DMA_BUSY_REG (SP_BASE_REG+0x18)
/* SP semaphore (R/W): Read: [0] semaphore flag (set on read) */
/* Write: [] clear semaphore flag */
#define SP_SEMAPHORE_REG (SP_BASE_REG+0x1C)
/* SP PC (R/W): [11:0] program counter */
#define SP_PC_REG 0x04080000
/* SP MEM address: bit 12 specifies if address is IMEM or DMEM */
#define SP_DMA_DMEM 0x0000 /* Bit 12: 0=DMEM, 1=IMEM */
#define SP_DMA_IMEM 0x1000 /* Bit 12: 0=DMEM, 1=IMEM */
/*
* Values to clear/set bit in status reg (SP_STATUS_REG - write)
*/
#define SP_CLR_HALT 0x00001 /* Bit 0: clear halt */
#define SP_SET_HALT 0x00002 /* Bit 1: set halt */
#define SP_CLR_BROKE 0x00004 /* Bit 2: clear broke */
#define SP_CLR_INTR 0x00008 /* Bit 3: clear intr */
#define SP_SET_INTR 0x00010 /* Bit 4: set intr */
#define SP_CLR_SSTEP 0x00020 /* Bit 5: clear sstep */
#define SP_SET_SSTEP 0x00040 /* Bit 6: set sstep */
#define SP_CLR_INTR_BREAK 0x00080 /* Bit 7: clear intr on break */
#define SP_SET_INTR_BREAK 0x00100 /* Bit 8: set intr on break */
#define SP_CLR_SIG0 0x00200 /* Bit 9: clear signal 0 */
#define SP_SET_SIG0 0x00400 /* Bit 10: set signal 0 */
#define SP_CLR_SIG1 0x00800 /* Bit 11: clear signal 1 */
#define SP_SET_SIG1 0x01000 /* Bit 12: set signal 1 */
#define SP_CLR_SIG2 0x02000 /* Bit 13: clear signal 2 */
#define SP_SET_SIG2 0x04000 /* Bit 14: set signal 2 */
#define SP_CLR_SIG3 0x08000 /* Bit 15: clear signal 3 */
#define SP_SET_SIG3 0x10000 /* Bit 16: set signal 3 */
#define SP_CLR_SIG4 0x20000 /* Bit 17: clear signal 4 */
#define SP_SET_SIG4 0x40000 /* Bit 18: set signal 4 */
#define SP_CLR_SIG5 0x80000 /* Bit 19: clear signal 5 */
#define SP_SET_SIG5 0x100000 /* Bit 20: set signal 5 */
#define SP_CLR_SIG6 0x200000 /* Bit 21: clear signal 6 */
#define SP_SET_SIG6 0x400000 /* Bit 22: set signal 6 */
#define SP_CLR_SIG7 0x800000 /* Bit 23: clear signal 7 */
#define SP_SET_SIG7 0x1000000 /* Bit 24: set signal 7 */
/*
* Patterns to interpret status reg (SP_STATUS_REG - read)
*/
#define SP_STATUS_HALT 0x001 /* Bit 0: halt */
#define SP_STATUS_BROKE 0x002 /* Bit 1: broke */
#define SP_STATUS_DMA_BUSY 0x004 /* Bit 2: dma busy */
#define SP_STATUS_DMA_FULL 0x008 /* Bit 3: dma full */
#define SP_STATUS_IO_FULL 0x010 /* Bit 4: io full */
#define SP_STATUS_SSTEP 0x020 /* Bit 5: single step */
#define SP_STATUS_INTR_BREAK 0x040 /* Bit 6: interrupt on break */
#define SP_STATUS_SIG0 0x080 /* Bit 7: signal 0 set */
#define SP_STATUS_SIG1 0x100 /* Bit 8: signal 1 set */
#define SP_STATUS_SIG2 0x200 /* Bit 9: signal 2 set */
#define SP_STATUS_SIG3 0x400 /* Bit 10: signal 3 set */
#define SP_STATUS_SIG4 0x800 /* Bit 11: signal 4 set */
#define SP_STATUS_SIG5 0x1000 /* Bit 12: signal 5 set */
#define SP_STATUS_SIG6 0x2000 /* Bit 13: signal 6 set */
#define SP_STATUS_SIG7 0x4000 /* Bit 14: signal 7 set */
/*
* Use of SIG bits
*/
#define SP_CLR_YIELD SP_CLR_SIG0
#define SP_SET_YIELD SP_SET_SIG0
#define SP_STATUS_YIELD SP_STATUS_SIG0
#define SP_CLR_YIELDED SP_CLR_SIG1
#define SP_SET_YIELDED SP_SET_SIG1
#define SP_STATUS_YIELDED SP_STATUS_SIG1
#define SP_CLR_TASKDONE SP_CLR_SIG2
#define SP_SET_TASKDONE SP_SET_SIG2
#define SP_STATUS_TASKDONE SP_STATUS_SIG2
#define SP_CLR_RSPSIGNAL SP_CLR_SIG3
#define SP_SET_RSPSIGNAL SP_SET_SIG3
#define SP_STATUS_RSPSIGNAL SP_STATUS_SIG3
#define SP_CLR_CPUSIGNAL SP_CLR_SIG4
#define SP_SET_CPUSIGNAL SP_SET_SIG4
#define SP_STATUS_CPUSIGNAL SP_STATUS_SIG4
/* SP IMEM BIST REG (R/W): [6:0] BIST status bits; see below for detail */
#define SP_IBIST_REG 0x04080004
/*
* Patterns to interpret status reg (SP_BIST_REG - write)
*/
#define SP_IBIST_CHECK 0x01 /* Bit 0: BIST check */
#define SP_IBIST_GO 0x02 /* Bit 1: BIST go */
#define SP_IBIST_CLEAR 0x04 /* Bit 2: BIST clear */
/*
* Patterns to interpret status reg (SP_BIST_REG - read)
*/
/* First 2 bits are same as in write mode:
* Bit 0: BIST check; Bit 1: BIST go
*/
#define SP_IBIST_DONE 0x04 /* Bit 2: BIST done */
#define SP_IBIST_FAILED 0x78 /* Bit [6:3]: BIST fail */
/*************************************************************************
* DP Command Registers
*/
#define DPC_BASE_REG 0x04100000
/* DP CMD DMA start (R/W): [23:0] DMEM/RDRAM start address */
#define DPC_START_REG (DPC_BASE_REG+0x00)
/* DP CMD DMA end (R/W): [23:0] DMEM/RDRAM end address */
#define DPC_END_REG (DPC_BASE_REG+0x04)
/* DP CMD DMA end (R): [23:0] DMEM/RDRAM current address */
#define DPC_CURRENT_REG (DPC_BASE_REG+0x08)
/* DP CMD status (R/W): [9:0] valid bits - see below for definitions */
#define DPC_STATUS_REG (DPC_BASE_REG+0x0C)
/* DP clock counter (R): [23:0] clock counter */
#define DPC_CLOCK_REG (DPC_BASE_REG+0x10)
/* DP buffer busy counter (R): [23:0] clock counter */
#define DPC_BUFBUSY_REG (DPC_BASE_REG+0x14)
/* DP pipe busy counter (R): [23:0] clock counter */
#define DPC_PIPEBUSY_REG (DPC_BASE_REG+0x18)
/* DP TMEM load counter (R): [23:0] clock counter */
#define DPC_TMEM_REG (DPC_BASE_REG+0x1C)
/*
* Values to clear/set bit in status reg (DPC_STATUS_REG - write)
*/
#define DPC_CLR_XBUS_DMEM_DMA 0x0001 /* Bit 0: clear xbus_dmem_dma */
#define DPC_SET_XBUS_DMEM_DMA 0x0002 /* Bit 1: set xbus_dmem_dma */
#define DPC_CLR_FREEZE 0x0004 /* Bit 2: clear freeze */
#define DPC_SET_FREEZE 0x0008 /* Bit 3: set freeze */
#define DPC_CLR_FLUSH 0x0010 /* Bit 4: clear flush */
#define DPC_SET_FLUSH 0x0020 /* Bit 5: set flush */
#define DPC_CLR_TMEM_CTR 0x0040 /* Bit 6: clear tmem ctr */
#define DPC_CLR_PIPE_CTR 0x0080 /* Bit 7: clear pipe ctr */
#define DPC_CLR_CMD_CTR 0x0100 /* Bit 8: clear cmd ctr */
#define DPC_CLR_CLOCK_CTR 0x0200 /* Bit 9: clear clock ctr */
/*
* Patterns to interpret status reg (DPC_STATUS_REG - read)
*/
#define DPC_STATUS_XBUS_DMEM_DMA 0x001 /* Bit 0: xbus_dmem_dma */
#define DPC_STATUS_FREEZE 0x002 /* Bit 1: freeze */
#define DPC_STATUS_FLUSH 0x004 /* Bit 2: flush */
/*#define DPC_STATUS_FROZEN 0x008*/ /* Bit 3: frozen */
#define DPC_STATUS_START_GCLK 0x008 /* Bit 3: start gclk */
#define DPC_STATUS_TMEM_BUSY 0x010 /* Bit 4: tmem busy */
#define DPC_STATUS_PIPE_BUSY 0x020 /* Bit 5: pipe busy */
#define DPC_STATUS_CMD_BUSY 0x040 /* Bit 6: cmd busy */
#define DPC_STATUS_CBUF_READY 0x080 /* Bit 7: cbuf ready */
#define DPC_STATUS_DMA_BUSY 0x100 /* Bit 8: dma busy */
#define DPC_STATUS_END_VALID 0x200 /* Bit 9: end valid */
#define DPC_STATUS_START_VALID 0x400 /* Bit 10: start valid */
/*************************************************************************
* DP Span Registers
*/
#define DPS_BASE_REG 0x04200000
/* DP tmem bist (R/W): [10:0] BIST status bits; see below for detail */
#define DPS_TBIST_REG (DPS_BASE_REG+0x00)
/* DP span test mode (R/W): [0] Span buffer test access enable */
#define DPS_TEST_MODE_REG (DPS_BASE_REG+0x04)
/* DP span buffer test address (R/W): [6:0] bits; see below for detail */
#define DPS_BUFTEST_ADDR_REG (DPS_BASE_REG+0x08)
/* DP span buffer test data (R/W): [31:0] span buffer data */
#define DPS_BUFTEST_DATA_REG (DPS_BASE_REG+0x0C)
/*
* Patterns to interpret status reg (DPS_TMEM_BIST_REG - write)
*/
#define DPS_TBIST_CHECK 0x01 /* Bit 0: BIST check */
#define DPS_TBIST_GO 0x02 /* Bit 1: BIST go */
#define DPS_TBIST_CLEAR 0x04 /* Bit 2: BIST clear */
/*
* Patterns to interpret status reg (DPS_TMEM_BIST_REG - read)
*/
/* First 2 bits are same as in write mode:
* Bit 0: BIST check; Bit 1: BIST go
*/
#define DPS_TBIST_DONE 0x004 /* Bit 2: BIST done */
#define DPS_TBIST_FAILED 0x7F8 /* Bit [10:3]: BIST fail */
/*************************************************************************
* MIPS Interface (MI) Registers
*/
#define MI_BASE_REG 0x04300000
/*
* MI init mode (W): [6:0] init length, [7] clear init mode, [8] set init mode
* [9/10] clear/set ebus test mode, [11] clear DP interrupt
* (R): [6:0] init length, [7] init mode, [8] ebus test mode
*/
#define MI_INIT_MODE_REG (MI_BASE_REG+0x00)
#define MI_MODE_REG MI_INIT_MODE_REG
/*
* Values to clear/set bit in mode reg (MI_MODE_REG - write)
*/
#define MI_CLR_INIT 0x0080 /* Bit 7: clear init mode */
#define MI_SET_INIT 0x0100 /* Bit 8: set init mode */
#define MI_CLR_EBUS 0x0200 /* Bit 9: clear ebus test */
#define MI_SET_EBUS 0x0400 /* Bit 10: set ebus test mode */
#define MI_CLR_DP_INTR 0x0800 /* Bit 11: clear dp interrupt */
#define MI_CLR_RDRAM 0x1000 /* Bit 12: clear RDRAM reg */
#define MI_SET_RDRAM 0x2000 /* Bit 13: set RDRAM reg mode */
/*
* Patterns to interpret mode reg (MI_MODE_REG - read)
*/
#define MI_MODE_INIT 0x0080 /* Bit 7: init mode */
#define MI_MODE_EBUS 0x0100 /* Bit 8: ebus test mode */
#define MI_MODE_RDRAM 0x0200 /* Bit 9: RDRAM reg mode */
/* MI version (R): [7:0] io, [15:8] rac, [23:16] rdp, [31:24] rsp */
#define MI_VERSION_REG (MI_BASE_REG+0x04)
#define MI_NOOP_REG MI_VERSION_REG
/* MI interrupt (R): [5:0] valid bits - see below for bit patterns */
#define MI_INTR_REG (MI_BASE_REG+0x08)
/*
* MI interrupt mask (W): [11:0] valid bits - see below for bit patterns
* (R): [5:0] valid bits - see below for bit patterns
*/
#define MI_INTR_MASK_REG (MI_BASE_REG+0x0C)
/*
* The following are values to check for interrupt setting (MI_INTR_REG)
*/
#define MI_INTR_SP 0x01 /* Bit 0: SP intr */
#define MI_INTR_SI 0x02 /* Bit 1: SI intr */
#define MI_INTR_AI 0x04 /* Bit 2: AI intr */
#define MI_INTR_VI 0x08 /* Bit 3: VI intr */
#define MI_INTR_PI 0x10 /* Bit 4: PI intr */
#define MI_INTR_DP 0x20 /* Bit 5: DP intr */
/*
* The following are values to clear/set various interrupt bit mask
* They can be ORed together to manipulate multiple bits
* (MI_INTR_MASK_REG - write)
*/
#define MI_INTR_MASK_CLR_SP 0x0001 /* Bit 0: clear SP mask */
#define MI_INTR_MASK_SET_SP 0x0002 /* Bit 1: set SP mask */
#define MI_INTR_MASK_CLR_SI 0x0004 /* Bit 2: clear SI mask */
#define MI_INTR_MASK_SET_SI 0x0008 /* Bit 3: set SI mask */
#define MI_INTR_MASK_CLR_AI 0x0010 /* Bit 4: clear AI mask */
#define MI_INTR_MASK_SET_AI 0x0020 /* Bit 5: set AI mask */
#define MI_INTR_MASK_CLR_VI 0x0040 /* Bit 6: clear VI mask */
#define MI_INTR_MASK_SET_VI 0x0080 /* Bit 7: set VI mask */
#define MI_INTR_MASK_CLR_PI 0x0100 /* Bit 8: clear PI mask */
#define MI_INTR_MASK_SET_PI 0x0200 /* Bit 9: set PI mask */
#define MI_INTR_MASK_CLR_DP 0x0400 /* Bit 10: clear DP mask */
#define MI_INTR_MASK_SET_DP 0x0800 /* Bit 11: set DP mask */
/*
* The following are values to check for interrupt mask setting
* (MI_INTR_MASK_REG - read)
*/
#define MI_INTR_MASK_SP 0x01 /* Bit 0: SP intr mask */
#define MI_INTR_MASK_SI 0x02 /* Bit 1: SI intr mask */
#define MI_INTR_MASK_AI 0x04 /* Bit 2: AI intr mask */
#define MI_INTR_MASK_VI 0x08 /* Bit 3: VI intr mask */
#define MI_INTR_MASK_PI 0x10 /* Bit 4: PI intr mask */
#define MI_INTR_MASK_DP 0x20 /* Bit 5: DP intr mask */
/*************************************************************************
* Video Interface (VI) Registers
*/
#define VI_BASE_REG 0x04400000
/* VI status/control (R/W): [15-0] valid bits:
* [1:0] = type[1:0] (pixel size)
* 0: blank (no data, no sync)
* 1: reserved
* 2: 5/5/5/3 ("16" bit)
* 3: 8/8/8/8 (32 bit)
* [2] = gamma_dither_enable (normally on, unless "special effect")
* [3] = gamma_enable (normally on, unless MPEG/JPEG)
* [4] = divot_enable (normally on if antialiased, unless decal lines)
* [5] = reserved - always off
* [6] = serrate (always on if interlaced, off if not)
* [7] = reserved - diagnostics only
* [9:8] = anti-alias (aa) mode[1:0]
* 0: aa & resamp (always fetch extra lines)
* 1: aa & resamp (fetch extra lines if needed)
* 2: resamp only (treat as all fully covered)
* 3: neither (replicate pixels, no interpolate)
* [11] = reserved - diagnostics only
* [15:12] = reserved
*
*/
#define VI_STATUS_REG (VI_BASE_REG+0x00)
#define VI_CONTROL_REG VI_STATUS_REG
/* VI origin (R/W): [23:0] frame buffer origin in bytes */
#define VI_ORIGIN_REG (VI_BASE_REG+0x04)
#define VI_DRAM_ADDR_REG VI_ORIGIN_REG
/* VI width (R/W): [11:0] frame buffer line width in pixels */
#define VI_WIDTH_REG (VI_BASE_REG+0x08)
#define VI_H_WIDTH_REG VI_WIDTH_REG
/* VI vertical intr (R/W): [9:0] interrupt when current half-line = V_INTR */
#define VI_INTR_REG (VI_BASE_REG+0x0C)
#define VI_V_INTR_REG VI_INTR_REG
/*
* VI current vertical line (R/W): [9:0] current half line, sampled once per
* line (the lsb of V_CURRENT is constant within a field, and in
* interlaced modes gives the field number - which is constant for non-
* interlaced modes)
* - Any write to this register will clear interrupt line
*/
#define VI_CURRENT_REG (VI_BASE_REG+0x10)
#define VI_V_CURRENT_LINE_REG VI_CURRENT_REG
/*
* VI video timing (R/W): [ 7: 0] horizontal sync width in pixels,
* [15: 8] color burst width in pixels,
* [19:16] vertical sync width in half lines,
* [29:20] start of color burst in pixels from h-sync
*/
#define VI_BURST_REG (VI_BASE_REG+0x14)
#define VI_TIMING_REG VI_BURST_REG
/* VI vertical sync (R/W): [9:0] number of half-lines per field */
#define VI_V_SYNC_REG (VI_BASE_REG+0x18)
/* VI horizontal sync (R/W): [11: 0] total duration of a line in 1/4 pixel
* [20:16] a 5-bit leap pattern used for PAL only
* (h_sync_period)
*/
#define VI_H_SYNC_REG (VI_BASE_REG+0x1C)
/*
* VI horizontal sync leap (R/W): [11: 0] identical to h_sync_period
* [27:16] identical to h_sync_period
*/
#define VI_LEAP_REG (VI_BASE_REG+0x20)
#define VI_H_SYNC_LEAP_REG VI_LEAP_REG
/*
* VI horizontal video (R/W): [ 9: 0] end of active video in screen pixels
* : [25:16] start of active video in screen pixels
*/
#define VI_H_START_REG (VI_BASE_REG+0x24)
#define VI_H_VIDEO_REG VI_H_START_REG
/*
* VI vertical video (R/W): [ 9: 0] end of active video in screen half-lines
* : [25:16] start of active video in screen half-lines
*/
#define VI_V_START_REG (VI_BASE_REG+0x28)
#define VI_V_VIDEO_REG VI_V_START_REG
/*
* VI vertical burst (R/W): [ 9: 0] end of color burst enable in half-lines
* : [25:16] start of color burst enable in half-lines
*/
#define VI_V_BURST_REG (VI_BASE_REG+0x2C)
/* VI x-scale (R/W): [11: 0] 1/horizontal scale up factor (2.10 format)
* [27:16] horizontal subpixel offset (2.10 format)
*/
#define VI_X_SCALE_REG (VI_BASE_REG+0x30)
/* VI y-scale (R/W): [11: 0] 1/vertical scale up factor (2.10 format)
* [27:16] vertical subpixel offset (2.10 format)
*/
#define VI_Y_SCALE_REG (VI_BASE_REG+0x34)
/*
* Patterns to interpret VI_CONTROL_REG
*/
#define VI_CTRL_TYPE_16 0x00002 /* Bit [1:0] pixel size: 16 bit */
#define VI_CTRL_TYPE_32 0x00003 /* Bit [1:0] pixel size: 32 bit */
#define VI_CTRL_GAMMA_DITHER_ON 0x00004 /* Bit 2: default = on */
#define VI_CTRL_GAMMA_ON 0x00008 /* Bit 3: default = on */
#define VI_CTRL_DIVOT_ON 0x00010 /* Bit 4: default = on */
#define VI_CTRL_SERRATE_ON 0x00040 /* Bit 6: on if interlaced */
#define VI_CTRL_ANTIALIAS_MASK 0x00300 /* Bit [9:8] anti-alias mode */
#define VI_CTRL_DITHER_FILTER_ON 0x10000 /* Bit 16: dither-filter mode */
/*
* Possible video clocks (NTSC or PAL)
*/
#define VI_NTSC_CLOCK 48681812 /* Hz = 48.681812 MHz */
#define VI_PAL_CLOCK 49656530 /* Hz = 49.656530 MHz */
#define VI_MPAL_CLOCK 48628316 /* Hz = 48.628316 MHz */
/*************************************************************************
* Audio Interface (AI) Registers
*
* The address and length registers are double buffered; that is, they
* can be written twice before becoming full.
* The address must be written before the length.
*/
#define AI_BASE_REG 0x04500000
/* AI DRAM address (W): [23:0] starting RDRAM address (8B-aligned) */
#define AI_DRAM_ADDR_REG (AI_BASE_REG+0x00) /* R0: DRAM address */
/* AI length (R/W): [14:0] transfer length (v1.0) - Bottom 3 bits are ignored */
/* [17:0] transfer length (v2.0) - Bottom 3 bits are ignored */
#define AI_LEN_REG (AI_BASE_REG+0x04) /* R1: Length */
/* AI control (W): [0] DMA enable - if LSB == 1, DMA is enabled */
#define AI_CONTROL_REG (AI_BASE_REG+0x08) /* R2: DMA Control */
/*
* AI status (R): [31]/[0] ai_full (addr & len buffer full), [30] ai_busy
* Note that a 1->0 transition in ai_full will set interrupt
* (W): clear audio interrupt
*/
#define AI_STATUS_REG (AI_BASE_REG+0x0C) /* R3: Status */
/*
* AI DAC sample period register (W): [13:0] dac rate
* - vid_clock/(dperiod + 1) is the DAC sample rate
* - (dperiod + 1) >= 66 * (aclockhp + 1) must be true
*/
#define AI_DACRATE_REG (AI_BASE_REG+0x10) /* R4: DAC rate 14-lsb*/
/*
* AI bit rate (W): [3:0] bit rate (abus clock half period register - aclockhp)
* - vid_clock/(2 * (aclockhp + 1)) is the DAC clock rate
* - The abus clock stops if aclockhp is zero
*/
#define AI_BITRATE_REG (AI_BASE_REG+0x14) /* R5: Bit rate 4-lsb */
/* Value for control register */
#define AI_CONTROL_DMA_ON 0x01 /* LSB = 1: DMA enable*/
#define AI_CONTROL_DMA_OFF 0x00 /* LSB = 1: DMA enable*/
/* Value for status register */
#define AI_STATUS_FIFO_FULL 0x80000000 /* Bit 31: full */
#define AI_STATUS_DMA_BUSY 0x40000000 /* Bit 30: busy */
/* DAC rate = video clock / audio frequency
* - DAC rate >= (66 * Bit rate) must be true
*/
#define AI_MAX_DAC_RATE 16384 /* 14-bit+1 */
#define AI_MIN_DAC_RATE 132
/* Bit rate <= (DAC rate / 66) */
#define AI_MAX_BIT_RATE 16 /* 4-bit+1 */
#define AI_MIN_BIT_RATE 2
/*
* Maximum and minimum values for audio frequency based on video clocks
* max frequency = (video clock / min dac rate)
* min frequency = (video clock / max dac rate)
*/
#define AI_NTSC_MAX_FREQ 368000 /* 368 KHz */
#define AI_NTSC_MIN_FREQ 3000 /* 3 KHz ~ 2971 Hz */
#define AI_PAL_MAX_FREQ 376000 /* 376 KHz */
#define AI_PAL_MIN_FREQ 3050 /* 3 KHz ~ 3031 Hz */
#define AI_MPAL_MAX_FREQ 368000 /* 368 KHz */
#define AI_MPAL_MIN_FREQ 3000 /* 3 KHz ~ 2968 Hz */
/*************************************************************************
* Peripheral Interface (PI) Registers
*/
#define PI_BASE_REG 0x04600000
/* PI DRAM address (R/W): [23:0] starting RDRAM address */
#define PI_DRAM_ADDR_REG (PI_BASE_REG+0x00) /* DRAM address */
/* PI pbus (cartridge) address (R/W): [31:0] starting AD16 address */
#define PI_CART_ADDR_REG (PI_BASE_REG+0x04)
/* PI read length (R/W): [23:0] read data length */
#define PI_RD_LEN_REG (PI_BASE_REG+0x08)
/* PI write length (R/W): [23:0] write data length */
#define PI_WR_LEN_REG (PI_BASE_REG+0x0C)
/*
* PI status (R): [0] DMA busy, [1] IO busy, [2], error
* (W): [0] reset controller (and abort current op), [1] clear intr
*/
#define PI_STATUS_REG (PI_BASE_REG+0x10)
/* PI dom1 latency (R/W): [7:0] domain 1 device latency */
#define PI_BSD_DOM1_LAT_REG (PI_BASE_REG+0x14)
/* PI dom1 pulse width (R/W): [7:0] domain 1 device R/W strobe pulse width */
#define PI_BSD_DOM1_PWD_REG (PI_BASE_REG+0x18)
/* PI dom1 page size (R/W): [3:0] domain 1 device page size */
#define PI_BSD_DOM1_PGS_REG (PI_BASE_REG+0x1C) /* page size */
/* PI dom1 release (R/W): [1:0] domain 1 device R/W release duration */
#define PI_BSD_DOM1_RLS_REG (PI_BASE_REG+0x20)
/* PI dom2 latency (R/W): [7:0] domain 2 device latency */
#define PI_BSD_DOM2_LAT_REG (PI_BASE_REG+0x24) /* Domain 2 latency */
/* PI dom2 pulse width (R/W): [7:0] domain 2 device R/W strobe pulse width */
#define PI_BSD_DOM2_PWD_REG (PI_BASE_REG+0x28) /* pulse width */
/* PI dom2 page size (R/W): [3:0] domain 2 device page size */
#define PI_BSD_DOM2_PGS_REG (PI_BASE_REG+0x2C) /* page size */
/* PI dom2 release (R/W): [1:0] domain 2 device R/W release duration */
#define PI_BSD_DOM2_RLS_REG (PI_BASE_REG+0x30) /* release duration */
#define PI_DOMAIN1_REG PI_BSD_DOM1_LAT_REG
#define PI_DOMAIN2_REG PI_BSD_DOM2_LAT_REG
#define PI_DOM_LAT_OFS 0x00
#define PI_DOM_PWD_OFS 0x04
#define PI_DOM_PGS_OFS 0x08
#define PI_DOM_RLS_OFS 0x0C
/*
* PI status register has 3 bits active when read from (PI_STATUS_REG - read)
* Bit 0: DMA busy - set when DMA is in progress
* Bit 1: IO busy - set when IO is in progress
* Bit 2: Error - set when CPU issues IO request while DMA is busy
*/
#define PI_STATUS_ERROR 0x04
#define PI_STATUS_IO_BUSY 0x02
#define PI_STATUS_DMA_BUSY 0x01
/* PI status register has 2 bits active when written to:
* Bit 0: When set, reset PIC
* Bit 1: When set, clear interrupt flag
* The values of the two bits can be ORed together to both reset PIC and
* clear interrupt at the same time.
*
* Note:
* - The PIC does generate an interrupt at the end of each DMA. CPU
* needs to clear the interrupt flag explicitly (from an interrupt
* handler) by writing into the STATUS register with bit 1 set.
*
* - When a DMA completes, the interrupt flag is set. CPU can issue
* another request even while the interrupt flag is set (as long as
* PIC is idle). However, it is the CPU's responsibility for
* maintaining accurate correspondence between DMA completions and
* interrupts.
*
* - When PIC is reset, if PIC happens to be busy, an interrupt will
* be generated as PIC returns to idle. Otherwise, no interrupt will
* be generated and PIC remains idle.
*/
/*
* Values to clear interrupt/reset PIC (PI_STATUS_REG - write)
*/
#define PI_STATUS_RESET 0x01
#define PI_SET_RESET PI_STATUS_RESET
#define PI_STATUS_CLR_INTR 0x02
#define PI_CLR_INTR PI_STATUS_CLR_INTR
#define PI_DMA_BUFFER_SIZE 128
#define PI_DOM1_ADDR1 0x06000000 /* to 0x07FFFFFF */
#define PI_DOM1_ADDR2 0x10000000 /* to 0x1FBFFFFF */
#define PI_DOM1_ADDR3 0x1FD00000 /* to 0x7FFFFFFF */
#define PI_DOM2_ADDR1 0x05000000 /* to 0x05FFFFFF */
#define PI_DOM2_ADDR2 0x08000000 /* to 0x0FFFFFFF */
/*************************************************************************
* RDRAM Interface (RI) Registers
*/
#define RI_BASE_REG 0x04700000
/* RI mode (R/W): [1:0] operating mode, [2] stop T active, [3] stop R active */
#define RI_MODE_REG (RI_BASE_REG+0x00)
/* RI config (R/W): [5:0] current control input, [6] current control enable */
#define RI_CONFIG_REG (RI_BASE_REG+0x04)
/* RI current load (W): [] any write updates current control register */
#define RI_CURRENT_LOAD_REG (RI_BASE_REG+0x08)
/* RI select (R/W): [2:0] receive select, [2:0] transmit select */
#define RI_SELECT_REG (RI_BASE_REG+0x0C)
/* RI refresh (R/W): [7:0] clean refresh delay, [15:8] dirty refresh delay,
* [16] refresh bank, [17] refresh enable
* [18] refresh optimize
*/
#define RI_REFRESH_REG (RI_BASE_REG+0x10)
#define RI_COUNT_REG RI_REFRESH_REG
/* RI latency (R/W): [3:0] DMA latency/overlap */
#define RI_LATENCY_REG (RI_BASE_REG+0x14)
/* RI error (R): [0] nack error, [1] ack error */
#define RI_RERROR_REG (RI_BASE_REG+0x18)
/* RI error (W): [] any write clears all error bits */
#define RI_WERROR_REG (RI_BASE_REG+0x1C)
/*************************************************************************
* Serial Interface (SI) Registers
*/
#define SI_BASE_REG 0x04800000
/* SI DRAM address (R/W): [23:0] starting RDRAM address */
#define SI_DRAM_ADDR_REG (SI_BASE_REG+0x00) /* R0: DRAM address */
/* SI address read 64B (W): [] any write causes a 64B DMA write */
#define SI_PIF_ADDR_RD64B_REG (SI_BASE_REG+0x04) /* R1: 64B PIF->DRAM */
/* Address SI_BASE_REG + (0x08, 0x0c, 0x14) are reserved */
/* SI address write 64B (W): [] any write causes a 64B DMA read */
#define SI_PIF_ADDR_WR64B_REG (SI_BASE_REG+0x10) /* R4: 64B DRAM->PIF */
/*
* SI status (W): [] any write clears interrupt
* (R): [0] DMA busy, [1] IO read busy, [2] reserved
* [3] DMA error, [12] interrupt
*/
#define SI_STATUS_REG (SI_BASE_REG+0x18) /* R6: Status */
/* SI status register has the following bits active:
* 0: DMA busy - set when DMA is in progress
* 1: IO busy - set when IO access is in progress
* 3: DMA error - set when there are overlapping DMA requests
* 12: Interrupt - Interrupt set
*/
#define SI_STATUS_DMA_BUSY 0x0001
#define SI_STATUS_RD_BUSY 0x0002
#define SI_STATUS_DMA_ERROR 0x0008
#define SI_STATUS_INTERRUPT 0x1000
/*************************************************************************
* Development Board GIO Control Registers
*/
#define GIO_BASE_REG 0x18000000
/* Game to Host Interrupt */
#define GIO_GIO_INTR_REG (GIO_BASE_REG+0x000)
/* Game to Host SYNC */
#define GIO_GIO_SYNC_REG (GIO_BASE_REG+0x400)
/* Host to Game Interrupt */
#define GIO_CART_INTR_REG (GIO_BASE_REG+0x800)
/*************************************************************************
* Common macros
*/
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
#define IO_READ(addr) (*(vu32 *)PHYS_TO_K1(addr))
#define IO_WRITE(addr,data) (*(vu32 *)PHYS_TO_K1(addr)=(u32)(data))
#define RCP_STAT_PRINT \
rmonPrintf("current=%x start=%x end=%x dpstat=%x spstat=%x\n", \
IO_READ(DPC_CURRENT_REG), \
IO_READ(DPC_START_REG), \
IO_READ(DPC_END_REG), \
IO_READ(DPC_STATUS_REG), \
IO_READ(SP_STATUS_REG))
#endif
#endif /* _RCP_H_ */
src/include/PR/sched.h
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#ifndef _ULTRA64_SCHED_H_
#define _ULTRA64_SCHED_H_
#include <ultra64.h>
#define OS_SC_STACKSIZE 0x2000
#define OS_SC_RETRACE_MSG 1
#define OS_SC_DONE_MSG 2
#define OS_SC_RDP_DONE_MSG 3
#define OS_SC_PRE_NMI_MSG 4
#define OS_SC_LAST_MSG 4 /* this should have highest number */
#define OS_SC_MAX_MESGS 8
typedef struct {
short type;
char misc[30];
} OSScMsg;
typedef struct OSScTask_s {
struct OSScTask_s *next; /* note: this must be first */
u32 state;
u32 flags;
void *framebuffer; /* used by graphics tasks */
OSTask list;
OSMesgQueue *msgQ;
OSMesg msg;
} OSScTask;
/*
* OSScTask flags:
*/
#define OS_SC_NEEDS_RDP 0x0001 /* uses the RDP */
#define OS_SC_NEEDS_RSP 0x0002 /* uses the RSP */
#define OS_SC_DRAM_DLIST 0x0004 /* SP & DP communicate through DRAM */
#define OS_SC_PARALLEL_TASK 0x0010 /* must be first gfx task on list */
#define OS_SC_LAST_TASK 0x0020 /* last task in queue for frame */
#define OS_SC_SWAPBUFFER 0x0040 /* swapbuffers when gfx task done */
#define OS_SC_RCP_MASK 0x0003 /* mask for needs bits */
#define OS_SC_TYPE_MASK 0x0007 /* complete type mask */
#define OS_SC_DP 0x0001 /* set if still needs dp */
#define OS_SC_SP 0x0002 /* set if still needs sp */
#define OS_SC_YIELD 0x0010 /* set if yield requested */
#define OS_SC_YIELDED 0x0020 /* set if yield completed */
/*
* OSScTask->flags type identifier
*/
#define OS_SC_XBUS (OS_SC_SP | OS_SC_DP)
#define OS_SC_DRAM (OS_SC_SP | OS_SC_DP | OS_SC_DRAM_DLIST)
#define OS_SC_DP_XBUS (OS_SC_SP)
#define OS_SC_DP_DRAM (OS_SC_SP | OS_SC_DRAM_DLIST)
#define OS_SC_SP_XBUS (OS_SC_DP)
#define OS_SC_SP_DRAM (OS_SC_DP | OS_SC_DRAM_DLIST)
/*
* private typedefs and defines
*/
#define VIDEO_MSG 666
#define RSP_DONE_MSG 667
#define RDP_DONE_MSG 668
#define PRE_NMI_MSG 669
/*
* OSScClient:
*
* Data structure used by threads that wish to communicate to the
* scheduling thread
*
*/
typedef struct SCClient_s {
struct SCClient_s *next; /* next client in the list */
OSMesgQueue *msgQ; /* where to send the frame msg */
} OSScClient;
typedef struct {
OSScMsg retraceMsg;
OSScMsg prenmiMsg;
OSMesgQueue interruptQ;
OSMesg intBuf[OS_SC_MAX_MESGS];
OSMesgQueue cmdQ;
OSMesg cmdMsgBuf[OS_SC_MAX_MESGS];
OSThread *thread;
OSScClient *clientList;
OSScTask *audioListHead;
OSScTask *gfxListHead;
OSScTask *audioListTail;
OSScTask *gfxListTail;
OSScTask *curRSPTask;
OSScTask *curRDPTask;
u32 frameCount;
s32 doAudio;
} OSSched;
void osCreateScheduler(OSSched *s, void *stack, u8 mode, u32 numFields);
void osScAddClient(OSSched *sc, OSScClient *c, OSMesgQueue *msgQ, OSScClient *next);
void osScRemoveClient(OSSched *s, OSScClient *c);
OSMesgQueue *osScGetCmdQ(OSSched *s);
#endif
src/include/PR/seqp.h
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#define KILL_TIME 50000 /* 50 ms */
#ifndef MIN
#define MIN(a,b) (((a)<(b))?(a):(b))
#endif
#ifndef MAX
#define MAX(a,b) (((a)>(b))?(a):(b))
#endif
ALVoiceState *__mapVoice(ALSeqPlayer *, u8, u8, u8);
void __unmapVoice(ALSeqPlayer *seqp, ALVoice *voice);
char __n_voiceNeedsNoteKill(ALSeqPlayer *seqp, ALVoice *voice, ALMicroTime killTime); /* sct 1/5/96 */
ALVoiceState *__lookupVoice(ALSeqPlayer *, u8, u8);
ALSound *__lookupSound(ALSeqPlayer *, u8, u8, u8);
ALSound *__lookupSoundQuick(ALSeqPlayer *, u8, u8, u8);
s16 __vsVol(ALVoiceState *voice, ALSeqPlayer *seqp);
ALMicroTime __n_vsDelta(ALVoiceState *voice, ALMicroTime t);
ALPan __vsPan(ALVoiceState *voice, ALSeqPlayer *seqp);
void __n_initFromBank(ALSeqPlayer *seqp, ALBank *b);
void __initChanState(ALSeqPlayer *seqp);
void __n_resetPerfChanState(ALSeqPlayer *seqp, s32 chan);
void __n_setInstChanState(ALSeqPlayer *seqp, ALInstrument *inst, s32 chan);
void __seqpPrintVoices(ALSeqPlayer *);
void __seqpReleaseVoice(ALSeqPlayer *seqp, ALVoice *voice,
ALMicroTime deltaTime);
void __n_seqpStopOsc(ALSeqPlayer *seqp, ALVoiceState *vs);
void __postNextSeqEvent(ALSeqPlayer *seqp); /* sct 11/7/95 */
src/include/PR/sptask.h
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#ifndef _ULTRA64_SPTASK_H_
#define _ULTRA64_SPTASK_H_
/* Task Types */
#define M_GFXTASK 1
#define M_AUDTASK 2
#define M_VIDTASK 3
#define M_HVQTASK 6
#define M_HVQMTASK 7
#if (defined(F3DEX_GBI) || defined(F3DLP_GBI) || defined(F3DEX_GBI_2) || 1)
#define OS_YIELD_DATA_SIZE 0xc00
#else
#define OS_YIELD_DATA_SIZE 0x900
#endif
#define OS_YIELD_AUDIO_SIZE 0x400
/* Flags */
#define M_TASK_FLAG0 1
#define M_TASK_FLAG1 2
#define OS_TASK_YIELDED 0x0001
#define OS_TASK_DP_WAIT 0x0002
#define OS_TASK_LOADABLE 0x0004
#define OS_TASK_SP_ONLY 0x0008
#define OS_TASK_USR0 0x0010
#define OS_TASK_USR1 0x0020
#define OS_TASK_USR2 0x0040
#define OS_TASK_USR3 0x0080
/* SpStatus */
#define SPSTATUS_CLEAR_HALT 0x00000001
#define SPSTATUS_SET_HALT 0x00000002
#define SPSTATUS_CLEAR_BROKE 0x00000004
#define SPSTATUS_CLEAR_INTR 0x00000008
#define SPSTATUS_SET_INTR 0x00000010
#define SPSTATUS_CLEAR_SSTEP 0x00000020
#define SPSTATUS_SET_SSTEP 0x00000040
#define SPSTATUS_CLEAR_INTR_ON_BREAK 0x00000080
#define SPSTATUS_SET_INTR_ON_BREAK 0x00000100
#define SPSTATUS_CLEAR_SIGNAL0 0x00000200
#define SPSTATUS_SET_SIGNAL0 0x00000400
#define SPSTATUS_CLEAR_SIGNAL1 0x00000800
#define SPSTATUS_SET_SIGNAL1 0x00001000
#define SPSTATUS_CLEAR_SIGNAL2 0x00002000
#define SPSTATUS_SET_SIGNAL2 0x00004000
#define SPSTATUS_CLEAR_SIGNAL3 0x00008000
#define SPSTATUS_SET_SIGNAL3 0x00010000
#define SPSTATUS_CLEAR_SIGNAL4 0x00020000
#define SPSTATUS_SET_SIGNAL4 0x00040000
#define SPSTATUS_CLEAR_SIGNAL5 0x00080000
#define SPSTATUS_SET_SIGNAL5 0x00100000
#define SPSTATUS_CLEAR_SIGNAL6 0x00200000
#define SPSTATUS_SET_SIGNAL6 0x00800000
#define SPSTATUS_CLEAR_SIGNAL7 0x01000000
#define SPSTATUS_SET_SIGNAL7 0x02000000
#define SPSTATUS_HALT 0x0001
#define SPSTATUS_BROKE 0x0002
#define SPSTATUS_DMA_BUSY 0x0004
#define SPSTATUS_DMA_FULL 0x0008
#define SPSTATUS_IO_FULL 0x0010
#define SPSTATUS_SINGLE_STEP 0x0020
#define SPSTATUS_INTERRUPT_ON_BREAK 0x0040
#define SPSTATUS_SIGNAL0_SET 0x0080
#define SPSTATUS_SIGNAL1_SET 0x0100
#define SPSTATUS_SIGNAL2_SET 0x0200
#define SPSTATUS_SIGNAL3_SET 0x0400
#define SPSTATUS_SIGNAL4_SET 0x0800
#define SPSTATUS_SIGNAL5_SET 0x1000
#define SPSTATUS_SIGNAL6_SET 0x2000
#define SPSTATUS_SIGNAL7_SET 0x4000
/* Types */
/* Types */
typedef struct
{
/*0x00*/ u32 type;
/*0x04*/ u32 flags;
/*0x08*/ u64 *ucode_boot;
/*0x0C*/ u32 ucode_boot_size;
/*0x10*/ u64 *ucode;
/*0x14*/ u32 ucode_size;
/*0x18*/ u64 *ucode_data;
/*0x1C*/ u32 ucode_data_size;
/*0x20*/ u64 *dram_stack;
/*0x24*/ u32 dram_stack_size;
/*0x28*/ u64 *output_buff;
/*0x2C*/ u64 *output_buff_size;
/*0x30*/ u64 *data_ptr;
/*0x34*/ u32 data_size;
/*0x38*/ u64 *yield_data_ptr;
/*0x3C*/ u32 yield_data_size;
} OSTask_t; // size = 0x40
typedef union {
OSTask_t t;
long long int force_structure_alignment;
} OSTask;
typedef u32 OSYieldResult;
/* Functions */
#define osSpTaskStart(p) \
osSpTaskLoad(p); \
osSpTaskStartGo(p);
void osSpTaskLoad(OSTask *task);
void osSpTaskStartGo(OSTask *task);
void osSpTaskYield(void);
OSYieldResult osSpTaskYielded(OSTask *task);
#endif
src/include/PR/synthInternals.h
-337
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/*====================================================================
* audioInternals.h
*
* Synopsis:
*
* Copyright 1993, Silicon Graphics, Inc.
* All Rights Reserved.
*
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Silicon Graphics,
* Inc.; the contents of this file may not be disclosed to third
* parties, copied or duplicated in any form, in whole or in part,
* without the prior written permission of Silicon Graphics, Inc.
*
* RESTRICTED RIGHTS LEGEND:
* Use, duplication or disclosure by the Government is subject to
* restrictions as set forth in subdivision (c)(1)(ii) of the Rights
* in Technical Data and Computer Software clause at DFARS
* 252.227-7013, and/or in similar or successor clauses in the FAR,
* DOD or NASA FAR Supplement. Unpublished - rights reserved under the
* Copyright Laws of the United States.
*====================================================================*/
#ifndef __audioInternals__
#define __audioInternals__
#include <PR/libaudio.h>
/*
* filter message ids
*/
enum {
AL_FILTER_FREE_VOICE,
AL_FILTER_SET_SOURCE,
AL_FILTER_ADD_SOURCE,
AL_FILTER_ADD_UPDATE,
AL_FILTER_RESET,
AL_FILTER_SET_WAVETABLE,
/* AL_FILTER_SET_DMA_PROC,*/
/* AL_FILTER_SKIP_LOOP,*/
AL_FILTER_SET_DRAM,
AL_FILTER_SET_PITCH,
AL_FILTER_SET_UNITY_PITCH,
AL_FILTER_START,
/* AL_FILTER_SET_DECAY,*/
/* AL_FILTER_SET_FC,*/
AL_FILTER_SET_STATE,
AL_FILTER_SET_VOLUME,
AL_FILTER_SET_PAN,
AL_FILTER_START_VOICE_ALT,
AL_FILTER_START_VOICE,
AL_FILTER_STOP_VOICE,
AL_FILTER_SET_FXAMT
};
#define AL_MAX_RSP_SAMPLES 160
/*
* buffer locations based on AL_MAX_RSP_SAMPLES
*/
#define AL_DECODER_IN 0
#define AL_RESAMPLER_OUT 0
#define AL_TEMP_0 0
#define AL_DECODER_OUT 320
#define AL_TEMP_1 320
#define AL_TEMP_2 640
#define AL_MAIN_L_OUT 1088
#define AL_MAIN_R_OUT 1408
#define AL_AUX_L_OUT 1728
#define AL_AUX_R_OUT 2048
/*
* filter types
*/
enum {
AL_ADPCM,
AL_RESAMPLE,
AL_BUFFER,
AL_SAVE,
AL_ENVMIX,
AL_FX,
AL_AUXBUS,
AL_MAINBUS
};
typedef struct ALParam_s {
struct ALParam_s *next;
s32 delta;
s16 type;
union {
f32 f;
s32 i;
} data;
union {
f32 f;
s32 i;
} moredata;
union {
f32 f;
s32 i;
} stillmoredata;
union {
f32 f;
s32 i;
} yetstillmoredata;
} ALParam;
typedef struct {
struct ALParam_s *next;
s32 delta;
s16 type;
s16 unity; /* disable resampler */
f32 pitch;
s16 volume;
ALPan pan;
u8 fxMix;
s32 samples;
struct ALWaveTable_s *wave;
} ALStartParamAlt;
typedef struct {
struct ALParam_s *next;
s32 delta;
s16 type;
s16 unity; /* disable resampler */
struct ALWaveTable_s *wave;
} ALStartParam;
typedef struct {
struct ALParam_s *next;
s32 delta;
s16 type;
struct PVoice_s *pvoice;
} ALFreeParam;
typedef Acmd *(*ALCmdHandler)(void *, s16 *, s32, s32, Acmd *);
typedef s32 (*ALSetParam)(void *, s32, void *);
typedef struct ALFilter_s {
struct ALFilter_s *source;
ALCmdHandler handler;
ALSetParam setParam;
s16 inp;
s16 outp;
s32 type;
} ALFilter;
void alFilterNew(ALFilter *f, ALCmdHandler h, ALSetParam s, s32 type);
#define AL_MAX_ADPCM_STATES 3 /* Depends on number of subframes
* per frame and loop length
*/
typedef struct {
ALFilter filter;
ADPCM_STATE *state;
ADPCM_STATE *lstate;
ALRawLoop loop;
struct ALWaveTable_s *table;
s32 bookSize;
ALDMAproc dma;
void *dmaState;
s32 sample;
s32 lastsam;
s32 first;
s32 memin;
} ALLoadFilter;
void alLoadNew(ALLoadFilter *f, ALDMANew dma, ALHeap *hp);
Acmd *alAdpcmPull(void *f, s16 *outp, s32 byteCount, s32 sampleOffset, Acmd *p);
Acmd *alRaw16Pull(void *f, s16 *outp, s32 byteCount, s32 sampleOffset, Acmd *p);
s32 alLoadParam(void *filter, s32 paramID, void *param);
typedef struct ALResampler_s {
ALFilter filter;
RESAMPLE_STATE *state;
f32 ratio;
s32 upitch;
f32 delta;
s32 first;
ALParam *ctrlList;
ALParam *ctrlTail;
s32 motion;
} ALResampler;
typedef struct {
s16 fc;
s16 fgain;
union {
s16 fccoef[16];
s64 force_aligned;
} fcvec;
POLEF_STATE *fstate;
s32 first;
} ALLowPass;
typedef struct {
u32 input;
u32 output;
s16 ffcoef;
s16 fbcoef;
s16 gain;
f32 rsinc;
f32 rsval;
s32 rsdelta;
f32 rsgain;
ALLowPass *lp;
ALResampler *rs;
} ALDelay;
typedef s32 (*ALSetFXParam)(void *, s32, void *);
typedef struct {
struct ALFilter_s filter;
s16 *base;
s16 *input;
u32 length;
ALDelay *delay;
u8 section_count;
ALSetFXParam paramHdl;
} ALFx;
void alFxNew(ALFx *r, ALSynConfig *c, ALHeap *hp);
Acmd *alFxPull(void *f, s16 *outp, s32 out, s32 sampleOffset, Acmd *p);
s32 alFxParam(void *filter, s32 paramID, void *param);
s32 alFxParamHdl(void *filter, s32 paramID, void *param);
#define AL_MAX_MAIN_BUS_SOURCES 1
typedef struct ALMainBus_s {
ALFilter filter;
s32 sourceCount;
s32 maxSources;
ALFilter **sources;
} ALMainBus;
void alMainBusNew(ALMainBus *m, void *ptr, s32 len);
Acmd *alMainBusPull(void *f, s16 *outp, s32 outCount, s32 sampleOffset, Acmd *p);
s32 alMainBusParam(void *filter, s32 paramID, void *param);
#define AL_MAX_AUX_BUS_SOURCES 8
#define AL_MAX_AUX_BUS_FX 1
typedef struct ALAuxBus_s {
ALFilter filter;
s32 sourceCount;
s32 maxSources;
ALFilter **sources;
ALFx fx[AL_MAX_AUX_BUS_FX];
} ALAuxBus;
void alAuxBusNew(ALAuxBus *m, void *ptr, s32 len);
Acmd *alAuxBusPull(void *f, s16 *outp, s32 outCount, s32 sampleOffset, Acmd *p);
s32 alAuxBusParam(void *filter, s32 paramID, void *param);
void alResampleNew(ALResampler *r, ALHeap *hp);
Acmd *alResamplePull(void *f, s16 *outp, s32 out, s32 sampleOffset, Acmd *p);
s32 alResampleParam(void *f, s32 paramID, void *param);
typedef struct ALSave_s {
ALFilter filter;
s32 dramout;
s32 first;
} ALSave;
void alSaveNew(ALSave *r);
Acmd *alSavePull(void *f, s16 *outp, s32 outCount, s32 sampleOffset, Acmd *p);
s32 alSaveParam(void *f, s32 paramID, void *param);
typedef struct ALEnvMixer_s {
u8 unk00[0x40];
ALFilter filter;
ENVMIX_STATE *state;
s16 pan;
s16 volume;
s16 cvolL;
s16 cvolR;
s16 dryamt;
s16 wetamt;
u16 lratl;
s16 lratm;
s16 ltgt;
u16 rratl;
s16 rratm;
s16 rtgt;
s32 delta;
s32 segEnd;
s32 first;
ALParam *ctrlList;
ALParam *ctrlTail;
//ALFilter **sources;
s32 motion;
} ALEnvMixer;
void alEnvmixerNew(ALEnvMixer *e, ALHeap *hp);
Acmd *alEnvmixerPull(void *f, s16 *outp, s32 out, s32 sampleOffset, Acmd *p);
s32 alEnvmixerParam(void *filter, s32 paramID, void *param);
/*
* heap stuff
*/
typedef struct {
s32 magic; /* check structure integrety */
s32 size; /* size of this allocated block */
u8 *file; /* file that this alloc was called from */
s32 line; /* line that it was called from */
s32 count; /* heap call number */
s32 pad0;
s32 pad1;
s32 pad2; /* Make it 32 bytes */
} HeapInfo;
#define AL_CACHE_ALIGN 15
/*
* synth stuff
*/
typedef struct PVoice_s {
ALLink node;
struct ALVoice_s *vvoice;
ALFilter *channelKnob;
ALLoadFilter decoder;
ALResampler resampler;
ALEnvMixer envmixer;
s32 offset;
} PVoice;
/*
* prototypes for private driver functions
*/
ALParam *__allocParam(void);
void __freeParam(ALParam *param);
void _freePVoice(PVoice *pvoice);
void _collectPVoices(void);
s32 _timeToSamples(s32 micros);
ALMicroTime _samplesToTime(ALSynth *synth, s32 samples);
#endif
src/include/PR/sys/asm.h
-704
View File
@@ -1,704 +0,0 @@
/**************************************************************************
* *
* Copyright (C) 1990, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
**************************************************************************/
/*
* Copyright 1985 by MIPS Computer Systems, Inc.
*/
#ifndef __SYS_ASM_H__
#define __SYS_ASM_H__
#ident "$Revision: 3.33 $"
#include "sgidefs.h"
/*
* asm.h -- cpp definitions for assembler files
*/
/*
* Notes on putting entry pt and frame info into symbol table for debuggers
*
* .ent name,lex-level # name is entry pt, lex-level is 0 for c
* name: # actual entry point
* .frame fp,framesize,saved_pc_reg
* # fp -- register which is pointer to base
* # of previous frame, debuggers are special
* # cased if "sp" to add "framesize"
* # (sp is usually used)
* # framesize -- size of frame
* # the expression:
* # new_sp + framesize == old_sp
* # should be true
* # saved_pc_reg -- either a register which
* # contains callers pc or $0, if $0
* # saved pc is assumed to be in
* # (fp)+framesize-4
*
* Notes regarding multiple entry points:
* LEAF is used when including the profiling header is appropriate
* XLEAF is used when the profiling header is in appropriate (e.g.
* when a entry point is known by multiple names, the profiling call
* should appear only once.) The correct ordering of ENTRY/XENTRY in this
* case is:
* LEAF(copyseg) # declare globl and emit profiling code
* XLEAF(copypage) # declare globl and alternate entry
*/
/*
* LEAF -- declare leaf routine
*/
#define LEAF(x) \
.globl x; \
.ent x,0; \
x:; \
.frame sp,0,ra
/*
* XLEAF -- declare alternate entry to leaf routine
*/
#define XLEAF(x) \
.globl x; \
.aent x,0; \
x:
/*
* VECTOR -- declare exception routine entry
*/
#if _K32U32
#define VECTOR(x, regmask) \
.globl x; \
.ent x,0; \
x:; \
.frame sp,EF_SIZE,$0; \
.mask +(regmask)|M_EXCFRM,-(EF_SIZE-(EF_RA))
#else
#define VECTOR(x, regmask) \
.globl x; \
.ent x,0; \
x:; \
.frame sp,EF_SIZE,$0; \
.mask +(regmask)|M_EXCFRM,-(EF_SIZE-(EF_RA+4))
#endif
/*
* NESTED -- declare nested routine entry point
*/
#define NESTED(x, fsize, rpc) \
.globl x; \
.ent x,0; \
x:; \
.frame sp,fsize, rpc
/*
* XNESTED -- declare alternate entry point to nested routine
*/
#define XNESTED(x) \
.globl x; \
.aent x,0; \
x:
/*
* END -- mark end of procedure
*/
#define END(proc) \
.end proc
/*
* IMPORT -- import external symbol
*/
#define IMPORT(sym, size) \
.extern sym,size
/*
* ABS -- declare absolute symbol
*/
#define ABS(x, y) \
.globl x; \
x = y
/*
* EXPORT -- export definition of symbol
*/
#define EXPORT(x) \
.globl x; \
x:
/*
* BSS -- allocate space in bss
*/
#define BSS(x,y) \
.comm x,y
/*
* LBSS -- allocate static space in bss
*/
#define LBSS(x,y) \
.lcomm x,y
/*
* Macros for writing PIC asm code
*/
#ifdef PIC
#define PICOPT .option pic2
/*
* Set gp when at 1st instruction
*/
#define SETUP_GP \
.set noreorder; \
.cpload t9; \
.set reorder
/*
* Set gp when not at 1st instruction
*/
#define SETUP_GPX(r) \
.set noreorder; \
move r, ra; /* save old ra */ \
bal 10f; /* find addr of cpload */\
nop; \
10: \
.cpload ra; \
move ra, r; \
.set reorder;
#define SAVE_GP(x) \
.cprestore x; /* save gp trigger t9/jalr conversion */
#else /* PIC */
#define PICOPT
#define SETUP_GP
#define SETUP_GPX(r)
#define SAVE_GP(x)
#endif /* PIC */
/*
* Stack Frame Definitions
*/
#if (_MIPS_SIM == _MIPS_SIM_ABI32)
#define NARGSAVE 4 /* space for 4 arg regs must be allocated */
#define ALSZ 7 /* align on 8 byte boundary */
#define ALMASK ~7
#endif
#if (_MIPS_SIM == _MIPS_SIM_ABI64)
#define NARGSAVE 0 /* no caller responsibilities */
#define ALSZ 15 /* align on 16 byte boundary */
#define ALMASK ~0xf
#endif
#if _KERNEL
/* Round the size of a stack frame to fit compiler conventions. */
#define FRAMESZ(size) (((size)+ALSZ) & ALMASK)
#endif
#if (_MIPS_ISA == _MIPS_ISA_MIPS1 || _MIPS_ISA == _MIPS_ISA_MIPS2)
#define SZREG 4
#endif
#if (_MIPS_ISA == _MIPS_ISA_MIPS3 || _MIPS_ISA == _MIPS_ISA_MIPS4)
#define SZREG 8
#endif
/*
* The following macros reserve the usage of the local label '9'
* By convention the caller should put the return addr in a2
* so that the stack backtrace can trace from a leaf
*/
#if defined(STANDALONE) || defined(LOCORE)
#define PANIC(msg) \
sw zero,waittime; \
la a0,9f; \
jal panic; \
MSG(msg)
#define PRINTF(msg) \
la a0,9f; \
jal printf; \
MSG(msg)
#else /* the kernel */
#define PANIC(msg) \
li a0,CE_PANIC; \
la a1,9f; \
jal cmn_err; \
MSG(msg)
#define SPPANIC(msg) \
/* make sure a good frame */\
lw sp,VPDA_LBOOTSTACK(zero); \
li a0,CE_PANIC; \
la a1,9f; \
jal cmn_err; \
MSG(msg)
#define ASMASSFAIL(msg) \
la a0,9f; \
la a1,lmsg; \
move a2,zero; \
j assfail; \
MSG(msg)
#define PRINTF(msg) \
la a0,9f; \
jal dprintf; \
MSG(msg)
#endif /* defined(STANDALONE) || defined(LOCORE) */
#define MSG(msg) \
.data; \
9: .asciiz msg; \
.text
#define SYSMAP(mname, vname, page, len) \
.globl mname; \
mname: \
.space len*4; \
.globl vname; \
vname = ((page)*NBPG)
#if !defined(_MIPSEB) && !defined(_MIPSEL)
.error Must define either _MIPSEB or _MIPSEL
#endif
#if defined(_MIPSEB) && defined(_MIPSEL)
.error Only one of _MIPSEB and _MIPSEL may be defined
#endif
/*
* The following macros deal with the coprocessor 0 scheduling
* hazards, which are different for the R3000 and R4000.
* The first digit in the name refers to the number
* of NOPs in the R2000/R3000 case, while the second digit
* refers to the number of NOPs in the R4000 case.
* NOTE: For now use R4000 values for TFP too. This at least
* lets us make the kernel.
*/
#if R4000
#define NOP_0_1 nop
#define NOP_0_2 nop; nop
#define NOP_0_3 nop; nop; nop
#define NOP_0_4 nop; nop; nop; nop
#define NOP_1_0
#define NOP_1_1 nop
#define NOP_1_2 nop; nop
#define NOP_1_3 nop; nop; nop
#define NOP_1_4 nop; nop; nop; nop
#endif
#if TFP
#define NOP_0_1
#define NOP_0_2
#define NOP_0_3
#define NOP_0_4
#define NOP_1_0
#define NOP_1_1 NOP_SSNOP
#define NOP_1_2 NOP_SSNOP
#define NOP_1_3 NOP_SSNOP
#define NOP_1_4 NOP_SSNOP
/* TFP has the following kinds of nops:
*
* NOP_NOP regular old nop -- takes a dispatch slot, but another
* integer instruction could be issued with it. But since
* TFP has only one shifter, two consecutive NOP_NOPs would
* go in separate cycles
* NOP_SSNOP nop which breaks superscalar dispatch. Will be the last
* instruction issued in a cycle. Instruction following
* will be first instruction issued in next cycle.
* NOP_NADA more than one of these can be scheduled per cycle
* since it does not use the shifter
*/
#define NOP_NOP sll zero,zero,0
#define NOP_SSNOP sll zero,zero,1
#define NOP_NADA addu zero,zero,zero
/*
* The following hazards are intended to be the maximum needed so that we
* do not have to worry about the instructions which follow. You may make
* use of the actual restrictions in order to optimize the code.
*
* Theoretically, NOP_MFC1_HAZ and NOP_MTC1_HAZ should not be needed but they
* are here just in case.
*
* NOP_MFC0_HAZ hazard after loading from C0
* NOP_MTC0_HAZ hazard after storing to C0
* NOP_ERET_HAZ hazard before eret after storing C0 registers
* NOP_COM_HAZ hazard following a COM operation -- TLBW, TLBR, etc.
* NOP_MFC1_HAZ hazard after loading from C1
* NOP_MTC1_HAZ hazard after storing to C1
*
* Actual restrictions:
* MFC0
* - two dmfc0 should not be executed in same cycle
* - a dmfc0 should not be issued in cycle following a dmtc0
* MTC0
* - in cycle after dmtc0 VAddr a COM will not correctly execute
* - in cycle after dmtc0 status a COM will not correctly execute
* - in same cycle as dmtc0 TLBSet a COM will not correctly execute
* - integer store should not be execute in same cycle as dmtc0 VAddr
* - two dmtc0 should not be executed in the same cycle
* - a dmfc0 should not be issued in cycle following a dmtc0
*
* - there should be three SSNOPs following a MTC0 which
* is enabling/disabling interrupts in the SR before new mask is
* effective
* - there should be three SSNOPs between a MTC0 which enables a CU
* field (like the FP) before issuing an instruction which uses the
* the FP.
* COM
* - 2 cycles after a COM a memory instruction will not execute properly
* - a TLBR/DCTR followed by a dmfc0 of EntryHi/EntryLo/DCache should
* leave two cycles between TLBR and dmfc0
*
* Additional restriction found executing kernel on RTL simulator:
*--------------------------------------------------------------------------
* jr r31
* dmtc0 r2,sr
* The jr happens to jump to 0x801b9204. However, the jal didn't store the
* proper value (pc + 8) into r31.
* The reason for this behavior is that mtc0's require an internal bus
* (MiscBus to be specific), in the W cycle. However, the jal also requires
* the MiscBus in its E cycle. Thus, the mux select lines for selecting
* the data to go into the GPR was incorrect.
* To make sure something like this won't occur again, it's probably a good
* idea not to have mtc0's in the delay slot, unless you are sure that the
* target quadword of instructions won't cause this internal bus collision.
*--------------------------------------------------------------------------
*/
#define NOP_MFC0_HAZ NOP_SSNOP
#define NOP_MTC0_HAZ NOP_SSNOP; NOP_SSNOP; NOP_SSNOP; NOP_SSNOP
#define NOP_ERET_HAZ
#define NOP_COM_HAZ NOP_SSNOP; NOP_SSNOP; NOP_SSNOP; NOP_SSNOP
/*
* The NOP_MFC1_HAZ and NOP_MTC1_HAZ are here only due to paranoia.
* I am also defining DMFC1 and DMTC1 which use these macros (in ip21prom.h).
* All this will exist until there is established confidence in FPU.
*/
#define NOP_MFC1_HAZ NOP_SSNOP; NOP_SSNOP; NOP_SSNOP; NOP_SSNOP
#define NOP_MTC1_HAZ NOP_SSNOP; NOP_SSNOP; NOP_SSNOP; NOP_SSNOP
#endif
#if R3000
#define NOP_0_1
#define NOP_0_2
#define NOP_0_3
#define NOP_0_4
#define NOP_1_0 nop
#define NOP_1_1 nop
#define NOP_1_2 nop
#define NOP_1_3 nop
#define NOP_1_4 nop
#endif
/*
* register mask bit definitions
*/
#define M_EXCFRM 0x00000001
#define M_AT 0x00000002
#define M_V0 0x00000004
#define M_V1 0x00000008
#define M_A0 0x00000010
#define M_A1 0x00000020
#define M_A2 0x00000040
#define M_A3 0x00000080
#define M_T0 0x00000100
#define M_T1 0x00000200
#define M_T2 0x00000400
#define M_T3 0x00000800
#define M_T4 0x00001000
#define M_T5 0x00002000
#define M_T6 0x00004000
#define M_T7 0x00008000
#define M_S0 0x00010000
#define M_S1 0x00020000
#define M_S2 0x00040000
#define M_S3 0x00080000
#define M_S4 0x00100000
#define M_S5 0x00200000
#define M_S6 0x00400000
#define M_S7 0x00800000
#define M_T8 0x01000000
#define M_T9 0x02000000
#define M_K0 0x04000000
#define M_K1 0x08000000
#define M_GP 0x10000000
#define M_SP 0x20000000
#define M_FP 0x40000000
#define M_RA 0x80000000
/*
* Macros for dealing with 64/32 bit asm files
*/
/*
* Basic register save and restore
*/
#if (_MIPS_ISA == _MIPS_ISA_MIPS1 || _MIPS_ISA == _MIPS_ISA_MIPS2)
#define REG_L lw
#define REG_S sw
#endif
#if (_MIPS_ISA == _MIPS_ISA_MIPS3 || _MIPS_ISA == _MIPS_ISA_MIPS4)
#define REG_L ld
#define REG_S sd
#endif
#if (_MIPS_SZINT == 32)
#define INT_L lw
#define INT_S sw
#define INT_LLEFT lwl /* load left */
#define INT_SLEFT swl /* store left */
#define INT_LRIGHT lwr /* load right */
#define INT_SRIGHT swr /* store right */
#define INT_ADD add
#define INT_ADDI addi
#define INT_ADDIU addiu
#define INT_ADDU addu
#define INT_SUB sub
#define INT_SUBI subi
#define INT_SUBIU subiu
#define INT_SUBU subu
#define INT_SLL sll
#define INT_SRL srl
#define INT_SRA sra
#define INT_SLLV sllv
#define INT_SRLV srlv
#define INT_SRAV srav
#define INT_LL ll
#define INT_SC sc
#endif /* _MIPS_SZINT == 32 */
#if (_MIPS_SZINT == 64)
#define INT_L ld
#define INT_S sd
#define INT_LLEFT ldl /* load left */
#define INT_SLEFT sdl /* store left */
#define INT_LRIGHT ldr /* load right */
#define INT_SRIGHT sdr /* store right */
#define INT_ADD dadd
#define INT_ADDI daddi
#define INT_ADDIU daddiu
#define INT_ADDU daddu
#define INT_SUB dsub
#define INT_SUBI dsubi
#define INT_SUBIU dsubiu
#define INT_SUBU dsubu
#define INT_SLL dsll
#define INT_SRL dsrl
#define INT_SRA dsra
#define INT_SLLV dsllv
#define INT_SRLV dsrlv
#define INT_SRAV dsrav
#define INT_LL lld
#define INT_SC scd
#endif /* _MIPS_SZINT == 64 */
#if (_MIPS_SZLONG == 32)
#define LONG_L lw
#define LONG_S sw
#define LONG_LLEFT lwl /* load left */
#define LONG_SLEFT swl /* store left */
#define LONG_LRIGHT lwr /* load right */
#define LONG_SRIGHT swr /* store right */
#define LONG_ADD add
#define LONG_ADDI addi
#define LONG_ADDIU addiu
#define LONG_ADDU addu
#define LONG_SUB sub
#define LONG_SUBI subi
#define LONG_SUBIU subiu
#define LONG_SUBU subu
#define LONG_SLL sll
#define LONG_SRL srl
#define LONG_SRA sra
#define LONG_SLLV sllv
#define LONG_SRLV srlv
#define LONG_SRAV srav
#define LONG_LL ll
#define LONG_SC sc
#endif /* _MIPS_SZLONG == 32 */
#if (_MIPS_SZLONG == 64)
#define LONG_L ld
#define LONG_S sd
#define LONG_LLEFT ldl /* load left */
#define LONG_SLEFT sdl /* store left */
#define LONG_LRIGHT ldr /* load right */
#define LONG_SRIGHT sdr /* store right */
#define LONG_ADD dadd
#define LONG_ADDI daddi
#define LONG_ADDIU daddiu
#define LONG_ADDU daddu
#define LONG_SUB dsub
#define LONG_SUBI dsubi
#define LONG_SUBIU dsubiu
#define LONG_SUBU dsubu
#define LONG_SLL dsll
#define LONG_SRL dsrl
#define LONG_SRA dsra
#define LONG_SLLV dsllv
#define LONG_SRLV dsrlv
#define LONG_SRAV dsrav
#define LONG_LL lld
#define LONG_SC scd
#endif /* _MIPS_SZLONG == 64 */
#if (_MIPS_SZPTR == 32)
#define PTR_L lw
#define PTR_S sw
#define PTR_LLEFT lwl /* load left */
#define PTR_SLEFT swl /* store left */
#define PTR_LRIGHT lwr /* load right */
#define PTR_SRIGHT swr /* store right */
#define PTR_ADD add
#define PTR_ADDI addi
#define PTR_ADDIU addiu
#define PTR_ADDU addu
#define PTR_SUB sub
#define PTR_SUBI subi
#define PTR_SUBIU subiu
#define PTR_SUBU subu
#define PTR_SLL sll
#define PTR_SRL srl
#define PTR_SRA sra
#define PTR_SLLV sllv
#define PTR_SRLV srlv
#define PTR_SRAV srav
#define PTR_LL ll
#define PTR_SC sc
#define PTR_WORD .word /* psuedo-op to reserve space for a ptr */
#define PTR_SCALESHIFT 2
#define LI li
#define LA la
#endif /* _MIPS_SZPTR == 32 */
#if (_MIPS_SZPTR == 64)
#define PTR_L ld
#define PTR_S sd
#define PTR_LLEFT ldl /* load left */
#define PTR_SLEFT sdl /* store left */
#define PTR_LRIGHT ldr /* load right */
#define PTR_SRIGHT sdr /* store right */
#define PTR_ADD dadd
#define PTR_ADDI daddi
#define PTR_ADDIU daddiu
#define PTR_ADDU daddu
#define PTR_SUB dsub
#define PTR_SUBI dsubi
#define PTR_SUBIU dsubiu
#define PTR_SUBU dsubu
#define PTR_SLL dsll
#define PTR_SRL dsrl
#define PTR_SRA dsra
#define PTR_SLLV dsllv
#define PTR_SRLV dsrlv
#define PTR_SRAV dsrav
#define PTR_LL lld
#define PTR_SC scd
#define PTR_WORD .dword /* psuedo-op to reserve space for a ptr */
#define PTR_SCALESHIFT 3
#define LI dli
#define LA dla
#endif /* _MIPS_SZPTR == 64 */
#if (_MIPS_ISA == _MIPS_ISA_MIPS1 || _MIPS_ISA == _MIPS_ISA_MIPS2)
#define MFC0 mfc0
#define MTC0 mtc0
#endif
#if (_MIPS_ISA == _MIPS_ISA_MIPS3 || _MIPS_ISA == _MIPS_ISA_MIPS4)
#define MFC0 dmfc0
#define MTC0 dmtc0
#endif
#if TFP
#define DMTC0(r,c) dmtc0 r,c; \
NOP_MTC0_HAZ
#define DMFC0(c,r) dmfc0 c,r; \
NOP_MFC0_HAZ
#if _K32U32 || _K32U64
# This code only works for SABLE
# We need to avoid a tlbmiss on the PC address (our pseudo-K0 space)
# because such a fault destroys values loaded into BADVADDR,
# TLBHI, etc.
#define SABLE_GOTO_KP64(reg1,reg2) \
lui reg2,0xa000; \
dsll reg2,32; \
la reg1,1f; \
dsll reg1,35; \
dsrl reg1,35; \
dadd reg1,reg2; \
NOP_SSNOP; \
j reg1; \
NOP_SSNOP; \
NOP_SSNOP; \
1: NOP_SSNOP \
# Now we're executing in Kernel Physical (KP) space
#else
#define SABLE_GOTO_KP64(reg1,reg2)
#endif /* !_K32U32 && ! _K32U64 */
#endif /* TFP */
#if R3000 || R4000
/* These macros let us replace existing mtc0/mfc0 instructions with macros
* that have no additional overhead for non-TFP machines but have the required
* number of scheduling NOPS for TFP.
*/
#define DMTC0(r,c) mtc0 r,c
#define DMFC0(c,r) mfc0 c,r
#define SABLE_GOTO_KP64(reg1,reg2)
#endif /* R3000 || R4000 */
#if TFP_TLBCACHE_WAR
/*
* This problem occurs when there is an I-Cache miss within two cycles of
* a valid tlb or dct (data cache tag) instruction. If the previous contents
* of the I-Cache contained a store instruction, the data cache can be
* corrupted.
*
* This problem can be worked around by putting all tlb/dct instructions on a
* 16-byte boundary. And, the three instructions that follow the tlb/dct
* must be ssnops (super-scalar no-ops). This guarantees that for the two
* cycles following the tlb/dct instruction, there can only be noops in the
* pipeline.
*/
#define TLB_READ .align 4; \
c0 C0_READ; \
NOP_SSNOP; \
NOP_SSNOP; \
NOP_SSNOP
#define TLB_WRITER .align 4; \
c0 C0_WRITER; \
NOP_SSNOP; \
NOP_SSNOP; \
NOP_SSNOP
#define TLB_PROBE .align 4; \
c0 C0_PROBE; \
NOP_SSNOP; \
NOP_SSNOP; \
NOP_SSNOP
#else /* !TFP_TLBCACHE_WAR */
#if TFP
#define TLB_READ c0 C0_READ; \
NOP_COM_HAZ
#define TLB_WRITER c0 C0_WRITER; \
NOP_COM_HAZ
#define TLB_PROBE c0 C0_PROBE; \
NOP_COM_HAZ
#else
#define TLB_READ c0 C0_READ
#define TLB_WRITER c0 C0_WRITER
#endif
#endif /* !TFP_TLBCACHE_WAR */
#endif /* __SYS_ASM_H__ */
src/include/PR/sys/regdef.h
-104
View File
@@ -1,104 +0,0 @@
/**************************************************************************
* *
* Copyright (C) 1990-1992, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
**************************************************************************/
/*
* Copyright 1985 by MIPS Computer Systems, Inc.
*/
#ifndef __SYS_REGDEF_H__
#define __SYS_REGDEF_H__
#ident "$Revision: 3.7 $"
#include "sgidefs.h"
#if (_MIPS_SIM == _MIPS_SIM_ABI32)
#define zero $0 /* wired zero */
#define AT $at /* assembler temp */
#define v0 $2 /* return value */
#define v1 $3
#define a0 $4 /* argument registers */
#define a1 $5
#define a2 $6
#define a3 $7
#define t0 $8 /* caller saved */
#define t1 $9
#define t2 $10
#define t3 $11
#define t4 $12 /* caller saved - 32 bit env arg reg 64 bit */
#define ta0 $12 /* caller saved in 32 bit - arg regs in 64 bit */
#define t5 $13
#define ta1 $13
#define t6 $14
#define ta2 $14
#define t7 $15
#define ta3 $15
#define s0 $16 /* callee saved */
#define s1 $17
#define s2 $18
#define s3 $19
#define s4 $20
#define s5 $21
#define s6 $22
#define s7 $23
#define t8 $24 /* code generator */
#define t9 $25
#define jp $25 /* PIC jump register */
#define k0 $26 /* kernel temporary */
#define k1 $27
#define gp $28 /* global pointer */
#define sp $29 /* stack pointer */
#define fp $30 /* frame pointer */
#define s8 $30 /* calle saved */
#define ra $31 /* return address */
#endif
#if (_MIPS_SIM == _MIPS_SIM_ABI64)
#define zero $0 /* wired zero */
#define AT $at /* assembler temp */
#define v0 $2 /* return value - caller saved */
#define v1 $3
#define a0 $4 /* argument registers */
#define a1 $5
#define a2 $6
#define a3 $7
#define a4 $8 /* arg reg 64 bit; caller saved in 32 bit */
#define ta0 $8
#define a5 $9
#define ta1 $9
#define a6 $10
#define ta2 $10
#define a7 $11
#define ta3 $11
#define t0 $12 /* caller saved */
#define t1 $13
#define t2 $14
#define t3 $15
#define s0 $16 /* callee saved */
#define s1 $17
#define s2 $18
#define s3 $19
#define s4 $20
#define s5 $21
#define s6 $22
#define s7 $23
#define t8 $24 /* caller saved */
#define t9 $25 /* callee address for PIC/temp */
#define jp $25 /* PIC jump register */
#define k0 $26 /* kernel temporary */
#define k1 $27
#define gp $28 /* global pointer - caller saved for PIC */
#define sp $29 /* stack pointer */
#define fp $30 /* frame pointer */
#define s8 $30 /* callee saved */
#define ra $31 /* return address */
#endif
#endif /* __SYS_REGDEF_H__ */
src/include/PR/ucode.h
-23
View File
@@ -1,23 +0,0 @@
#ifndef _ULTRA64_UCODE_H_
#define _ULTRA64_UCODE_H_
#define SP_DRAM_STACK_SIZE8 0x400
#define SP_UCODE_SIZE 0x1000
#define SP_UCODE_DATA_SIZE 0x800
// standard boot ucode
extern u64 rspF3DBootStart[], rspF3DBootEnd[];
// F3D ucode
extern u64 rspF3DStart[], rspF3DEnd[];
// F3D ucode data
extern u64 rspF3DDataStart[], rspF3DDataEnd[];
// aspMain (audio) ucode
extern u64 rspAspMainStart[], rspAspMainEnd[];
// aspMain ucode data
extern u64 rspAspMainDataStart[], rspAspMainDataEnd[];
#endif
src/include/PR/ultratypes.h
-42
View File
@@ -1,42 +0,0 @@
#ifndef _ULTRA64_TYPES_H_
#define _ULTRA64_TYPES_H_
#ifndef NULL
#define NULL (void *)0
#endif
#define TRUE 1
#define FALSE 0
#define OS_TV_PAL 0
#define OS_TV_NTSC 1
#define OS_TV_MPAL 2
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
typedef signed char s8;
typedef unsigned char u8;
typedef signed short int s16;
typedef unsigned short int u16;
typedef signed int s32;
typedef unsigned int u32;
typedef signed long long int s64;
typedef unsigned long long int u64;
typedef volatile u8 vu8;
typedef volatile u16 vu16;
typedef volatile u32 vu32;
typedef volatile u64 vu64;
typedef volatile s8 vs8;
typedef volatile s16 vs16;
typedef volatile s32 vs32;
typedef volatile s64 vs64;
typedef float f32;
typedef double f64;
typedef unsigned long size_t;
#endif
#endif
src/include/asm_helper.h
+4 -4
View File
@@ -1,9 +1,9 @@
#ifndef _ASM_HELPER_H
#define _ASM_HELPER_H
#include "PR/R4300.h"
#include "PR/sys/regdef.h"
#include "PR/sys/asm.h"
#include "PR/rcp.h"
#include <R4300.h>
#include <sys/regdef.h>
#include <sys/asm.h>
#include <rcp.h>
#define STAY1(stmnt) .set noreorder; stmnt; .set reorder;
#define STAY2(stmnt, arg1) .set noreorder; stmnt, arg1; .set reorder;
src/include/bss.h
+1 -5
View File
@@ -11,7 +11,7 @@ extern u32 var8008ae2c;
extern u32 var8008ae30;
extern OSThread g_MainThread;
extern OSMesgQueue var8008db30;
extern OSSched g_SchedThread;
extern OSSched g_Sched;
extern OSViMode var8008dcc0[2];
extern OSViMode *var8008dd60[2];
extern u32 var8008de08;
@@ -21,7 +21,6 @@ extern u8 g_BootBufferDirtyIndexes[3];
extern s32 g_BootBufferIndex0;
extern OSPiHandle CartRomHandle;
extern OSPiHandle LeoDiskHandle;
extern OSPifRam __osPfsPifRam;
extern OSTimer var80090ab0;
extern OSMesgQueue var80090ad0;
extern OSMesg var80090ae8;
@@ -59,19 +58,16 @@ extern u8 *var8009c644;
extern u8 var8009c650[];
extern u8 *var8009c6d8;
extern u8 *var8009c6dc;
extern __OSEventState __osEventStateTab[15];
extern OSTimer var8009c760;
extern OSTime __osCurrentTime;
extern u32 __osBaseCounter;
extern u32 __osViIntrCount;
extern OSMesgQueue __osPiAccessQueue;
extern OSPifRam __osContPifRam;
extern u8 __osContLastCmd;
extern u8 __osMaxControllers;
extern OSTimer __osEepromTimer;
extern OSMesgQueue __osEepromTimerQ;
extern OSMesg __osEepromTimerMsg;
extern OSPifRam __osEepPifRam;
extern u32 var8009ca84;
extern u8 *g_FrameBuffers[2];
extern u8 var8009caec[4];
src/include/constants.h
+1
View File
@@ -1,6 +1,7 @@
#ifndef _IN_CONSTANTS_H
#define _IN_CONSTANTS_H
#include "versions.h"
#include "math.h"
#include "animations.h"
#include "files.h"
#include "sequences.h"
src/include/data.h
-7
View File
@@ -33,7 +33,6 @@ extern OSPiHandle *__osCurrentHandle[2];
extern u32 var8005cf30;
extern OSTime osClockRate;
extern s32 osViClock;
extern u32 _osShutdown;
extern u32 __osGlobalIntMask;
extern u32 var8005cf84;
extern u8 g_LoadType;
@@ -83,8 +82,6 @@ extern u32 var8005f038;
extern u16 *g_RdpOutBufferEnd;
extern u16 *g_RdpOutBufferStart;
extern struct rdptask *g_RdpCurTask;
extern ALGlobals *n_alGlobals;
extern ALGlobals *n_syn;
extern u32 var8005f120;
extern u32 var8005f124;
extern u32 var8005f128;
@@ -107,11 +104,7 @@ extern u32 var8005f704;
extern OSViMode osViModeTable[];
extern u32 var80060890;
extern OSTimer *__osTimerList;
extern __OSViContext var800608b0[2];
extern __OSViContext *__osViCurr;
extern __OSViContext *__osViNext;
extern u32 __osPiAccessQueueEnabled;
extern u32 __osThreadTail;
extern OSThread *__osRunQueue;
extern OSThread *__osActiveQueue;
extern OSThread *__osRunningThread;
src/include/lib/lib_2fba0.h
-2
View File
@@ -4,6 +4,4 @@
#include "data.h"
#include "types.h"
void n_alInit(ALGlobals *g, ALSynConfig *c);
#endif
src/include/lib/lib_30ce0.h
-9
View File
@@ -1,9 +0,0 @@
#ifndef _IN_LIB_LIB_30CE0_H
#define _IN_LIB_LIB_30CE0_H
#include <ultra64.h>
#include "data.h"
#include "types.h"
void n_alSynNew(ALSynConfig *c);
#endif
src/include/lib/lib_34240.h
+1 -2
View File
@@ -4,8 +4,7 @@
#include "data.h"
#include "types.h"
u32 alCSPNew(void);
u32 func00034df8(void);
u32 __n_CSPHandleNextSeqEvent(void);
u32 func00034f0c(void);
u32 func00034fb8(void);
u32 func00035110(void);
src/include/lib/lib_37650.h
+1 -1
View File
@@ -4,6 +4,6 @@
#include "data.h"
#include "types.h"
void func00037650(ALCSPlayer *seqp, ALBank *bank);
void func00037650(N_ALCSPlayer *seqp, ALBank *bank);
#endif
src/include/lib/lib_39c80.h
+1 -1
View File
@@ -4,7 +4,7 @@
#include "data.h"
#include "types.h"
void func00039c80(ALCSPlayer *seqp, s16 volume);
void func00039c80(N_ALCSPlayer *seqp, s16 volume);
void func00039cd0(ALCSPlayer *seqp);
u32 func00039e5c(void);
src/include/lib/lib_3c430.h
+1 -1
View File
@@ -4,6 +4,6 @@
#include "data.h"
#include "types.h"
Acmd *func0003c430(s32 arg0, void *arg1);
Acmd *n_alSavePull(s32 arg0, void *arg1);
#endif
src/include/lib/lib_3d280.h
-1
View File
@@ -10,6 +10,5 @@ u32 func0003d69c(void);
u32 func0003d72c(void);
u32 func0003d8a4(void);
u32 func0003d9cc(void);
void __n_resetPerfChanState(ALSeqPlayer *seqp, s32 chan);
#endif
src/include/lib/lib_3e3e0.h
-1
View File
@@ -8,7 +8,6 @@ u32 func0003e3e0(void);
u32 func0003e490(void);
u32 func0003e540(void);
u32 func0003e5b8(void);
u32 n_alSynSetFXParam(void);
u32 func0003e674(void);
#endif
src/include/lib/sched.h
+1
View File
@@ -1,6 +1,7 @@
#ifndef _IN_BOOT_SCHED_H
#define _IN_BOOT_SCHED_H
#include <ultra64.h>
#include <sched.h>
void func00001b28(u32 arg0);
void __scHandleRetraceViaPri(OSSched *sc, OSScTask *t);
src/include/libultra_internal.h
-73
View File
@@ -1,73 +0,0 @@
#ifndef _LIBULTRA_INTERNAL_H_
#define _LIBULTRA_INTERNAL_H_
#include <ultra64.h>
typedef struct
{
u32 initialized; //probably something like initialized?
OSThread *mgrThread;
OSMesgQueue *unk08;
OSMesgQueue *unk0c;
OSMesgQueue *unk10;
s32 (*dma_func)(s32,u32,void*,size_t);
u64 force_align;
} OSMgrArgs;
typedef struct
{
/* 0x0 */ __OSInode inode;
/* 0x100 */ u8 bank;
/* 0x101 */ u8 map[256];
} __OSInodeCache;
s32 __osDisableInt();
void __osRestoreInt(s32);
s32 __osContRamRead(OSMesgQueue *mq, int channel, u16 address, u8 *buffer);
s32 __osContRamWrite(OSMesgQueue *mq, int channel, u16 address, u8 *buffer, int force);
void __osEnqueueAndYield(OSThread**);
void __osDequeueThread(OSThread**, OSThread*);
void __osEnqueueThread(OSThread**, OSThread*);
OSThread* __osPopThread(OSThread**);
s32 __osSiRawStartDma(s32, void*);
void __osSiCreateAccessQueue();
void __osSiGetAccess();
void __osSiRelAccess();
u32 __osProbeTLB(void*);
void __osPiCreateAccessQueue();
void __osPiGetAccess();
void __osSetSR(u32);
u32 __osGetSR();
void __osSetFpcCsr(u32);
s32 __osSiRawReadIo(u32, u32*);
s32 __osSiRawWriteIo(u32, u32);
s32 osPiRawReadIo(u32 a0, u32 *a1);
void __osSpSetStatus(u32);
u32 __osSpGetStatus();
s32 __osSpSetPc(u32);
s32 __osSpDeviceBusy();
s32 __osSiDeviceBusy();
s32 __osSpRawStartDma(s32 direction, u32 devAddr, void *dramAddr, u32 size);
void __osViInit();
__OSViContext * __osViGetCurrentContext();
void __osViSwapContext();
void __osSetTimerIntr(u64);
u64 __osInsertTimer(OSTimer *);
void __osSetCompare(u32);
s32 __osAiDeviceBusy();
void __osDispatchThread();
u32 __osGetCause();
s32 __osAtomicDec(u32*);
s32 __osPfsSelectBank(OSPfs *pfs, u8 bank);
u16 __osSumCalc(u8 *ptr, int length);
s32 __osIdCheckSum(u16 *ptr, u16 *csum, u16 *icsum);
s32 __osRepairPackId(OSPfs *pfs, __OSPackId *badid, __OSPackId *newid);
s32 __osCheckPackId(OSPfs *pfs, __OSPackId *temp);
s32 __osGetId(OSPfs *pfs);
s32 __osCheckId(OSPfs *pfs);
s32 __osPfsRWInode(OSPfs *pfs, __OSInode *inode, u8 flag, u8 bank);
u8 __osContAddressCrc(u16 inaddr);
u8 __osContDataCrc(u8 *data);
s32 __osPfsReleasePages(OSPfs *pfs, __OSInode *inode, u8 initial_page, u8 bank, __OSInodeUnit *final_page);
s32 __osGbpakSelectBank(OSPfs *pfs, u8 bank);
#endif
src/include/stdarg.h
Executable
+42
View File
@@ -0,0 +1,42 @@
#ifndef STDARG_H
#define STDARG_H
// When not building with IDO, use the builtin vaarg macros for portability.
#ifndef __sgi
#define va_list __builtin_va_list
#define va_start __builtin_va_start
#define va_arg __builtin_va_arg
#define va_end __builtin_va_end
#else
typedef char *va_list;
#define _FP 1
#define _INT 0
#define _STRUCT 2
#define _VA_FP_SAVE_AREA 0x10
#define _VA_ALIGN(p, a) (((unsigned int)(((char *)p) + ((a) > 4 ? (a) : 4) - 1)) & -((a) > 4 ? (a) : 4))
#define va_start(vp, parmN) (vp = ((va_list)&parmN + sizeof(parmN)))
#define __va_stack_arg(list, mode) \
( \
((list) = (char *)_VA_ALIGN(list, __builtin_alignof(mode)) + \
_VA_ALIGN(sizeof(mode), 4)), \
(((char *)list) - (_VA_ALIGN(sizeof(mode), 4) - sizeof(mode))))
#define __va_double_arg(list, mode) \
( \
(((long)list & 0x1) /* 1 byte aligned? */ \
? (list = (char *)((long)list + 7), (char *)((long)list - 6 - _VA_FP_SAVE_AREA)) \
: (((long)list & 0x2) /* 2 byte aligned? */ \
? (list = (char *)((long)list + 10), (char *)((long)list - 24 - _VA_FP_SAVE_AREA)) \
: __va_stack_arg(list, mode))))
#define va_arg(list, mode) ((mode *)(((__builtin_classof(mode) == _FP && \
__builtin_alignof(mode) == sizeof(double)) \
? __va_double_arg(list, mode) \
: __va_stack_arg(list, mode))))[-1]
#define va_end(__list)
#endif
#endif
src/include/lib/libc/ldiv.h → src/include/stdlib.h
Regular → Executable
+6 -4
View File
@@ -1,6 +1,9 @@
#ifndef _IN_LIB_LIBC_LDIV_H
#define _IN_LIB_LIBC_LDIV_H
#ifndef __STDLIB_H__
#define __STDLIB_H__
#ifndef NULL
#define NULL 0
#endif
typedef struct lldiv_t
{
long long quot;
@@ -15,5 +18,4 @@ typedef struct ldiv_t
lldiv_t lldiv(long long num, long long denom);
ldiv_t ldiv(long num, long denom);
#endif
#endif /* !__STDLIB_H__ */
src/include/string.h
Executable
+55
View File
@@ -0,0 +1,55 @@
#ifndef __STRING_H__
#define __STRING_H__
#ifdef __cplusplus
extern "C" {
#endif
#ident "$Revision: 1.23 $"
/*
*
* Copyright 1992, Silicon Graphics, Inc.
* All Rights Reserved.
*
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Silicon Graphics, Inc.;
* the contents of this file may not be disclosed to third parties, copied or
* duplicated in any form, in whole or in part, without the prior written
* permission of Silicon Graphics, Inc.
*
* RESTRICTED RIGHTS LEGEND:
* Use, duplication or disclosure by the Government is subject to restrictions
* as set forth in subdivision (c)(1)(ii) of the Rights in Technical Data
* and Computer Software clause at DFARS 252.227-7013, and/or in similar or
* successor clauses in the FAR, DOD or NASA FAR Supplement. Unpublished -
* rights reserved under the Copyright Laws of the United States.
*/
/* Copyright (c) 1990, 1991 UNIX System Laboratories, Inc. */
/* Copyright (c) 1988 AT&T */
/* All Rights Reserved */
/* THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF */
/* UNIX System Laboratories, Inc. */
/* The copyright notice above does not evidence any */
/* actual or intended publication of such source code. */
#if !defined(_SIZE_T) && !defined(_SIZE_T_)
#define _SIZE_T
#if (_MIPS_SZLONG == 32)
typedef unsigned int size_t;
#endif
#if (_MIPS_SZLONG == 64)
typedef unsigned long size_t;
#endif
#endif
#ifndef NULL
#define NULL 0
#endif
extern void *memcpy(void *, const void *, size_t);
extern char *strchr(const char *, int);
extern size_t strlen(const char *);
#ifdef __cplusplus
}
#endif
#endif /* !__STRING_H__ */
src/include/types.h
+4 -2
View File
@@ -1,6 +1,8 @@
#ifndef _IN_TYPES_H
#define _IN_TYPES_H
#include <ultra64.h>
#include <sched.h>
#include "n_libaudio.h"
#include "constants.h"
#include "gbiex.h"
#include "lang.h"
@@ -6238,7 +6240,7 @@ struct var80094ed8 {
/*0x0ec*/ u32 unk0ec;
/*0x0f0*/ u32 unk0f0;
/*0x0f4*/ u32 unk0f4;
/*0x0f8*/ ALCSPlayer *seqp;
/*0x0f8*/ N_ALCSPlayer *seqp;
/*0x0fc*/ void *unk0fc;
/*0x100*/ u16 unk100;
/*0x104*/ u32 unk104;
@@ -6948,7 +6950,7 @@ typedef struct {
OSMesg audioFrameMsgBuf[8];
OSMesgQueue audioReplyMsgQ;
OSMesg audioReplyMsgBuf[8];
ALGlobals g;
N_ALGlobals g;
} AMAudioMgr;
typedef struct {
src/include/ultra64.h
-37
View File
@@ -1,37 +0,0 @@
#ifndef _ULTRA64_H_
#define _ULTRA64_H_
#include <math.h>
#include <PR/ultratypes.h>
#include <PR/os_exception.h>
#include <PR/os_misc.h>
#include <PR/os_rdp.h>
#include <PR/os_thread.h>
#include <PR/os_time.h>
#include <PR/os_message.h>
#include <PR/os_cont.h>
#include <PR/os_tlb.h>
#include <PR/sptask.h>
#include <PR/ucode.h>
#include <PR/os_cache.h>
#include <PR/os_vi.h>
#include <PR/os_pi.h>
#include <PR/os_pfs.h>
#include <PR/os_internal.h>
#include <PR/mbi.h>
#include <PR/os_eeprom.h>
#include <PR/os_libc.h>
#include <PR/gu.h>
#include <PR/os_ai.h>
#include <PR/libaudio.h>
#include <PR/libultra.h>
#include <PR/rcp.h>
#include <PR/sched.h>
#define OS_K0_TO_PHYSICAL(x) (u32)(((char *)(x)-0x80000000))
#define OS_K1_TO_PHYSICAL(x) (u32)(((char *)(x)-0xa0000000))
#define OS_PHYSICAL_TO_K0(x) (void *)(((u32)(x)+0x80000000))
#define OS_PHYSICAL_TO_K1(x) (void *)(((u32)(x)+0xa0000000))
#endif