From 2df9b84b34ecdf2df8d21b847d84bfbce94c3274 Mon Sep 17 00:00:00 2001 From: Matthew Stanley <1379tech@gmail.com> Date: Sat, 27 Jun 2026 12:41:55 -0700 Subject: [PATCH] docs(timing): log GTE per-command stall + dirty-interp muldiv parity Co-Authored-By: Claude Opus 4.8 --- ACCURACY_BURNDOWN.md | 8 +++++++- FAITHFUL_TIMING_PLAN.md | 11 +++++++++++ 2 files changed, 18 insertions(+), 1 deletion(-) diff --git a/ACCURACY_BURNDOWN.md b/ACCURACY_BURNDOWN.md index 573baace..ba8d5c6d 100644 --- a/ACCURACY_BURNDOWN.md +++ b/ACCURACY_BURNDOWN.md @@ -110,7 +110,13 @@ observe added to the recompiler so ANY block leader is anchorable on both backen - [ ] **Instruction-fetch / I-cache** — ruler #1 shows the residual: Beetle 84 on cold-line hits (I-cache refill) vs native flat 56. Next component. Beetle ReadInstruction (+0 hit / +4 KSEG1 / +3+refill miss). -- [ ] GTE per-command cycles — Beetle gte.cpp GTE_Instruction; DuckStation; psx-spx. +- [x] **GTE per-command cycles — DONE, validated EXACT** (commit ec1fd76). + CPUState.gte_ts_done armed in gte_execute (cost-1 table verified from beetle + gte.cpp op returns; AVSZ4=5 not 6); any COP2 reg access stalls to it; both + emitters + interp. Ruler #2 gte_rtps +15 / gte_nclip +8 == Beetle. FMV no-reg. +- [x] **Mult/div stall — also completed to the dirty-RAM interpreter** (commit + 75d5d1a): backend parity (interp was charging 0 for mult/div). By-construction + + no-regression (no interp-path ruler yet — see below). - [ ] Instruction-fetch / I-cache timing — Beetle ReadInstruction (+0 hit / +4 KSEG1 / +3+refill miss). Ruler's 56→84 cold spread is the I-cache line-refill transient. - [ ] **HW test-ROM ruler (#2)** — Amidog CPU/GTE timing ROMs for hand-crafted diff --git a/FAITHFUL_TIMING_PLAN.md b/FAITHFUL_TIMING_PLAN.md index a26a541f..8b93879e 100644 --- a/FAITHFUL_TIMING_PLAN.md +++ b/FAITHFUL_TIMING_PLAN.md @@ -213,6 +213,17 @@ on a fixed region -> next. ## 5. Status / Log (update every session) +- **2026-06-27 (GTE per-command completion-stall — VALIDATED EXACT):** Modeled + GTE (COP2) command latency + stall-on-COP2-access. New CPUState.gte_ts_done; + a GTE command arms it (now + cost-1, serializing back-to-back ops); any COP2 + reg access (MFC2/CFC2/MTC2/CTC2/LWC2/SWC2) stalls to it. Cost table + (psx_cycles.c) transcribed+verified from beetle gte.cpp op returns (note + AVSZ4=5 not the psx-spx-doc's 6). Set armed in the shared gte_execute (both + backends); stall emitted at every COP2 reg-access site in both emitters + the + interp (offset cancels like muldiv). Added gte_rtps/gte_nclip loops to ruler + #2: native +15/+8 == Beetle +15/+8 EXACT; all other components unchanged; + Tomba2 boots to FMV no-regression. Commit ec1fd76. Required regen. UNPUSHED. + - **2026-06-27 (dirty-interp mult/div completion-stall — backend parity):** Completed the mult/div stall to the SECOND backend. The dirty-RAM interpreter (Tomba2 overlays) charged 0 for mult/div while the compiled emitters already