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# Cycle-driven CPU/peripheral timing — architecture
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Status: design proposal. No code committed against this doc yet.
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## Why
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The runtime currently has no real notion of PSX wall-time. SIO byte
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readiness, ACK timing, IRQ delivery, and VBlank scheduling all infer
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"time" from proxies: MMIO access count, dispatch_count heuristics, host
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wall-clock, or function-boundary callbacks. Every memory-card debugging
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detour this branch has accumulated — burst drains, hard-cap defers,
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SELECT-lifetime owner guards, hybrid sync/async TX paths — has been a
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symptom of the same missing primitive: there is no `psx_cycle_count`.
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Real PSX hardware advances peripherals on every CPU cycle. SIO TX_RDY
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clears for ~1088 cycles per byte regardless of whether the CPU is in an
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exception. ACK arrives ~170 cycles after byte completion. VBlank fires
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on the GPU's own cycle deadline. The CPU is one client of the bus, not
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the master of time.
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Until the runtime models that, every fix to the symptom (pad leaks,
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abort_reselect, etc.) is structurally a guess.
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## Architectural target
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### 1. Central PSX cycle clock
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```c
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extern uint64_t psx_cycle_count;
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```
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- Owned by a new `psx_cycles.c` / `psx_cycles.h`.
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- Monotonically increasing. Never decremented.
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- Advanced by `psx_advance_cycles(int cycles)` (signed int for symmetry
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with sio_tick(int)).
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- All peripherals derive their schedules from this clock.
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### 2. Peripheral scheduler
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```c
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void psx_advance_cycles(int cycles);
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```
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Single entry-point. Internally:
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1. `psx_cycle_count += cycles`
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2. Call `sio_advance(cycles)` — shifter/buffer/ACK timing
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3. Call `gpu_advance(cycles)` — VBlank deadline
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4. Call `timers_advance(cycles)` — root counters (later)
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5. Call `cdrom_advance(cycles)` — CD timing (later)
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Each peripheral exposes its own `*_advance(int cycles)`. The dispatcher
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holds no peripheral knowledge. Order matters only when one peripheral's
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advance can fire an IRQ that affects another's deadline computation —
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not the case for the initial slice.
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**No `in_exception` gating on hardware time.** Real PSX SIO keeps
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shifting while the CPU is in the exception handler. Our peripheral
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advance must reflect that.
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### 3. Interrupt correctness — separate "pending" from "entry"
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Two distinct concepts:
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- **IRQ source pending** = `i_stat & i_mask != 0`. Set by peripherals
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any time their schedule fires. Independent of CPU mode.
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- **CPU may enter exception** = `(SR & 0x401) == 0x401` AND not already
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in a kernel exception frame AND we're at a legal instruction
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boundary.
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`psx_check_interrupts(cpu)` becomes:
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```c
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void psx_check_interrupts(CPUState* cpu) {
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/* hardware time always advances */
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psx_advance_cycles(<block cycles since last check>);
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/* peripheral writes to i_stat already happened in *_advance() */
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/* CPU-side gate: are we at a legal entry point? */
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if (!cpu_can_take_interrupt(cpu)) return;
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if ((i_stat & i_mask) == 0) return;
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/* Enter exception */
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cpu_enter_exception(cpu);
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}
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```
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`cpu_can_take_interrupt(cpu)` checks:
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- `cpu->cop0[SR] & IEc` (bit 0)
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- `cpu->cop0[SR] & IM[2]` (bit 10)
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- not currently inside a previously-entered exception (use `in_exception`
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ONLY as a re-entry guard against host-side recursion through
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`psx_dispatch` from inside the BIOS handler — not as a hardware-time
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gate)
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The handler may now run for a long time without freezing peripheral
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schedules. SIO can fire its ACK IRQ while the CPU is mid-handler; the
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new IRQ pends in `i_stat` and is delivered on the next legal CPU entry
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point after the current exception returns.
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### 4. SIO model — single bus, no device-specific paths
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SIO0 has one shifter, one TX buffer, one ACK pipeline. Card and pad
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share it. Modeling:
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```c
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struct sio_bus {
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int shift_active;
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uint8_t shift_byte;
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int shift_remaining_cycles; /* counts down each advance */
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int tx_buffered; /* per no$psx, single byte */
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uint8_t tx_buffer;
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int ack_remaining_cycles; /* fires IRQ when reaches 0 */
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int ack_pending;
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};
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```
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`sio_write(SIO_TX_DATA)`:
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- if `!shift_active`: load shifter, clear TX_RDY/TX_EMPTY
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- else if `!tx_buffered`: load buffer, clear TX_EMPTY (TX_RDY already 0)
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- else: byte dropped (per no$psx — only the FIRST write while busy
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buffers; subsequent writes ignored)
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`sio_advance(cycles)`:
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- if `shift_active`: `shift_remaining -= cycles`. On <= 0: run state
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machine on the shifted byte (`sio_process_byte`), schedule ACK, promote
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buffer if any, else restore TX_RDY.
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- if `ack_pending`: `ack_remaining -= cycles`. On <= 0: set
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`i_stat |= 1<<7` (gated by `SIO_CTRL.ACK_IRQ_EN`).
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`sio_read(SIO_STAT)`:
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- Returns current shifter/buffer/ACK state. No tick on read.
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Card and pad protocols both use this single mechanism. There is **no**
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"card busy → block pad" check anywhere. The natural timing of TX_RDY
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and TX_EMPTY enforces mutual exclusion via the existing BIOS pad-poll
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behavior — pad's TX writes during card-busy go to the buffer or are
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dropped; their `mc_state` mutation does not happen because the byte is
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held in the SIO buffer until the card's shift completes, at which point
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the buffered byte becomes the next byte processed against `mc_state` in
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its current state. **If real hardware would have lost the pad poll's
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byte**, our model loses it. The pad chain handler retries on next
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VBlank.
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### 5. Recompiler integration — block-level cycle accounting
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Each emitted basic block:
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- gets a precomputed `block_cycles` count (sum of per-instruction
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cycles for the block's MIPS instructions; integer multiplication and
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load-delay penalties accounted for)
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- emits `psx_advance_cycles(<block_cycles>);` before its `psx_dispatch`
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return
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Block boundaries that contain MMIO reads — **option A required** per
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explicit user direction:
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- Split the block at every MMIO read. Cycles up to that point are
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advanced before the read so SIO_STAT (and analogous registers) show
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the elapsed guest time the BIOS expects.
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- The simpler "advance the whole block before the read" was rejected
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because it over-advances and may cause the BIOS to see a TX_RDY
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transition earlier than the real bytes have actually shifted.
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For MMIO writes, advance the block's accumulated cycles before the
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write so peripherals see the same elapsed time the CPU sees.
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Busy-wait loops (e.g., `while (!(STAT & TX_RDY));`) become tight loops
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of small basic blocks. Each loop iteration advances cycles. After
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~1088 cycles total, the SIO shifter completes, TX_RDY restores, the
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loop exits. This is the architectural fix for the access-paced
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`sio_tick` problem.
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### 6. VBlank — cycle-based deadline
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```c
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static uint64_t next_vblank_deadline_cycles;
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void gpu_advance(int cycles) {
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if (psx_cycle_count >= next_vblank_deadline_cycles) {
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next_vblank_deadline_cycles += NTSC_FRAME_CYCLES; /* ~33,868,800 / 60 */
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i_stat |= (1 << IRQ_VBLANK);
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gpu_lcf ^= 1;
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gpu_vblank_callback(); /* SDL present + debug_server_poll */
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}
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}
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```
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`dispatch_count` is removed from the VBlank path. SDL/TCP polling
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still happens on VBlank fire — the host-side cadence is determined by
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how fast the recompiled code runs, but that's correct: VBlank fires at
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the right PSX-visible cycle count regardless of host wall-clock.
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### 7. Migration strategy
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Vertical-slice approach. Each step independently testable, mergeable.
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**1.0e-a: cycle counter scaffold**
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- Add `psx_cycles.c/.h` with `psx_cycle_count` and
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`psx_advance_cycles()`. Empty body except for the count update.
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- All peripherals' `*_advance(cycles)` declared but no-op stubs.
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- No recompiler integration yet.
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- Validation: zero behavior change; build clean; baseline preserved.
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**1.0e-b: SIO scheduler under cycle clock**
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- Implement `sio_advance(cycles)` driven from
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`psx_advance_cycles`. SIO state vars (already on tree from 1.0c-v2)
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become live.
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- TX_DATA writes feed the shifter; sio_process_byte called from
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shift-complete; ACK fires from cycle countdown.
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- Critical: `psx_advance_cycles` is called from a SINGLE site
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initially — `psx_check_interrupts` — using a fixed estimate (e.g.,
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`BLOCK_CYCLES_AVG=8` per call). This isn't accurate per-block but
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proves the time-source plumbing works without recompiler changes.
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- Validation: pad polling at shell still works; card protocol behavior
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may change.
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**1.0e-c: VBlank cycle-based**
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- `gpu_advance` fires VBlank from cycle deadline.
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- Remove `dispatch_count` from interrupts.c. Keep
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`!card_active || progress_stale` defer logic OUT — it becomes
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obsolete once timing is correct.
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- Validation: TCP still responsive; VBlank rate tracks PSX-visible
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cycle-time.
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**1.0e-d: per-block cycle accounting in recompiler**
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- Recompiler emits `psx_advance_cycles(<block_cycles>)` per block.
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- Replace the fixed `BLOCK_CYCLES_AVG` from 1.0e-b with per-block.
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- Validation: accurate timing; SIO bytes shift in cycle-correct
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windows; card txns no longer receive pad TX during READ_DATA.
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**1.0e-e: card-read full-sector validation**
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- Confirm card transactions reach 137 bytes.
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- `[0x72F0]` reaches 0x80.
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- `mc_read_done > 0`.
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- Beetle byte-trace cross-check.
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- Memory-card screen renders directory entries.
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## Open questions to resolve before 1.0e-a
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1. **What's the average cycles-per-block for our recompiled BIOS?**
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Need this for 1.0e-b. Pick the wrong number and pad polling rate is
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off, card-shift duration is wrong. Estimate: profile a few hundred
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blocks and pick a median.
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2. **Where does cycle accounting LIVE in `psx_check_interrupts`?**
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Before or after `dispatch_count++`? Should it replace it entirely
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in 1.0e-b or coexist for one revision?
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3. **Does the dirty_ram_interp need cycle accounting?**
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Probably yes — interpreted blocks should also advance the clock.
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Add a `psx_advance_cycles(N)` call at the end of each interpreted
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block.
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4. **Should `psx_advance_cycles` be allowed to fire IRQs?**
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Yes — that's the whole point. But the IRQ-pending bit is set in
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`i_stat`; CPU exception entry only happens at the next call to
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`psx_check_interrupts`, which checks SR/IM/in_exception. No
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recursive entry.
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5. **VBlank during exception handler — do we still need a defer?**
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No. Real hardware fires VBlank during handler too; the IRQ pends
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until the handler returns. With proper CPU-side gating, our model
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matches without any defer.
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## Hard rules during 1.0e implementation
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- No "drop the pad byte" hacks.
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- No card-specific paths.
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- No multi-slot TX FIFOs without no$psx evidence.
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- No `dispatch_count`-based VBlank.
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- No `in_exception` gating on hardware time advance.
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- No bypassing the chain dispatcher.
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- No edits to generated BIOS C.
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- No fake directory data.
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- All migrations behind `SIO_MODEL_CYCLE_PACED` (already on tree from
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1.0a). Default flips to 1 only when the slice it covers is fully
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validated.
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## Vertical slice for first commit (1.0e-a)
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Smallest possible. Just the scaffold, no behavior change:
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1. New file `runtime/include/psx_cycles.h`:
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```c
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#ifndef PSX_CYCLES_H
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#define PSX_CYCLES_H
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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extern uint64_t psx_cycle_count;
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void psx_advance_cycles(int cycles);
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uint64_t psx_get_cycle_count(void);
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#ifdef __cplusplus
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}
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#endif
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#endif
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```
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2. New file `runtime/src/psx_cycles.c`:
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```c
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#include "psx_cycles.h"
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uint64_t psx_cycle_count = 0;
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void psx_advance_cycles(int cycles) {
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if (cycles <= 0) return;
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psx_cycle_count += (uint64_t)cycles;
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/* Phase 1.0e-a: peripheral hooks empty.
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* 1.0e-b will call sio_advance(cycles); etc. */
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}
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uint64_t psx_get_cycle_count(void) {
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return psx_cycle_count;
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}
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```
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3. Add `psx_cycles.c` to `runtime/CMakeLists.txt` for both targets.
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4. Expose via TCP in `debug_server.c` as a passive read-only field
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(e.g., add `"psx_cycle_count"` to `freeze_check`).
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5. Validation: build clean; baseline behavior unchanged
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(`psx_advance_cycles` not called by anyone yet); `freeze_check`
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shows `psx_cycle_count: 0`.
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That's 1.0e-a. After validation passes, 1.0e-b plugs the SIO scheduler
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in. Each subsequent step adds one capability and re-validates against
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baseline + the previous step.
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Matthew Stanley