From 7118734d047fbe214cda033b7fc82b43e2b7dce9 Mon Sep 17 00:00:00 2001 From: Shokunin <30949000+tetrisgm@users.noreply.github.com> Date: Tue, 29 Sep 2026 12:26:45 -0700 Subject: [PATCH] docs: correct the ruler #2 icache_miss value on the 15-loop ROM The 2026-06-27 MMIO entry in FAITHFUL_TIMING_PLAN.md says the 13 prior loops were unchanged when mmio_timer and mmio_spu were added. icache_miss was not: the two new loops sit before it and move its loop top from 0x80010144 to 0x80010170, so each of its two misses costs one cycle more and it reads +16 on both backends (re-measured against live psx-beetle; the cycle_testrom README already explains the shift). The entry now carries a dated correction, and the beetle-macos.md intro no longer points readers at +14 as the current value. Co-Authored-By: Claude Opus 5.5 --- docs/beetle-macos.md | 4 +++- docs/internal/FAITHFUL_TIMING_PLAN.md | 4 ++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/docs/beetle-macos.md b/docs/beetle-macos.md index 5307e8ad..57b5cf2f 100644 --- a/docs/beetle-macos.md +++ b/docs/beetle-macos.md @@ -12,7 +12,9 @@ starting from a fresh clone of the official Beetle repository: - `ping` answers `backend=beetle`, and `guest_cycles` advances about 565,050 cycles per frame (33.8688 MHz at 59.94 Hz is 565,045); - ruler #2 (`tools/cycle_testrom`) reproduces the oracle values recorded in - `internal/FAITHFUL_TIMING_PLAN.md`, `icache_miss +14` included (see step 6). + `internal/FAITHFUL_TIMING_PLAN.md` on all 13 loops of the 13-loop ROM + (`icache_miss +14`) and on all 15 loops of the current ROM, where + `icache_miss` reads +16 (see step 6). The Linux recipe is in `beetle-linux.md`. The Beetle side of both is the same patch set. diff --git a/docs/internal/FAITHFUL_TIMING_PLAN.md b/docs/internal/FAITHFUL_TIMING_PLAN.md index 3a036f59..c3193c4c 100644 --- a/docs/internal/FAITHFUL_TIMING_PLAN.md +++ b/docs/internal/FAITHFUL_TIMING_PLAN.md @@ -896,6 +896,10 @@ on a fixed region -> next. rebuild runtime/cyctest. New ruler #2 loops `mmio_timer` (Timer0 read → +3 = 1 dev + 2 compl) and `mmio_spu` (32-bit SPU read → +38 = 36 + 2). VALIDATED: cyctest COMPILED (4600) == Beetle (4382) EXACT on ALL 15 loops incl. mmio_timer +3 / mmio_spu +38; the 13 prior loops unchanged. + (Correction, 2026-09-29: except `icache_miss`, which reads +16 on this 15-loop ROM on both + backends, not +14. The two new loops sit before it and move its loop top from 0x80010144 to + 0x80010170, a different offset in its cache line, so each of its two misses costs one cycle + more. Re-measured against live psx-beetle; see tools/cycle_testrom/README.md.) Tomba 2 boots past the BIOS to its "SCEA Presents" intro splash, total_checks advancing, no freeze (the faster-MMIO change did not trigger a device-timing cascade like load=4 did). RESIDUAL (documented, unmodeled dynamic axis): DMACycleSteal — Beetle adds the live DMA