mirror of
https://github.com/RetroPortingToolKit/psxrecomp
synced 2026-10-28 02:56:36 -04:00
mmx6 framework: CD/DMA/MDEC + codegen fixes (Tomba builds+plays, MMX6 boots to intro)
Framework work on codex/mmx6-support that makes Tomba build and play (title screen, 0 dispatch misses) and MMX6 boot through BIOS to its intro. Touches recompiler codegen (code_generator, function_analysis) and runtime CD-ROM/DMA/MDEC/GPU/SIO timing (cdrom, dma, mdec, gpu, psx_cycles, traps, fntrace, debug_server) + headers + runtime.cmake. Milestone snapshot for collapsing onto master. Build dir excluded. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
This commit is contained in:
Matthew Stanley
@@ -1481,82 +1481,70 @@ std::string CodeGenerator::generate_file(
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// in CPUState, but these standalone functions provide correct reference behavior.
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ss << "/* --- Unaligned memory access helper implementations --- */\n";
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ss << "\n";
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ss << "/* LWL: Load Word Left - merges high bytes from aligned word into rt.\n";
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ss << " * addr is the effective (possibly unaligned) address.\n";
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ss << " * rt_value is the current value of the destination register.\n";
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ss << " * MIPS big-endian convention: byte 0 is the most-significant byte.\n";
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ss << " * The PSX (little-endian) maps addr&3==0 -> load entire word,\n";
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ss << " * addr&3==1 -> load 3 bytes into high 24 bits, etc.\n";
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ss << " * Formula:\n";
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ss << " * aligned_addr = addr & ~3;\n";
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ss << " * shift = (addr & 3) * 8;\n";
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ss << " * mask = 0xFFFFFFFF << shift;\n";
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ss << " * result = (rt_value & ~mask) | (word << shift);\n";
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ss << " * where word = read_word(aligned_addr).\n";
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ss << " */\n";
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ss << "static uint32_t psx_lwl(CPUState* cpu, uint32_t addr, uint32_t rt_value) {\n";
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ss << " uint32_t aligned_addr = addr & ~3u;\n";
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ss << " uint32_t word = cpu->read_word(aligned_addr);\n";
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ss << " uint32_t shift = (addr & 3u) * 8u;\n";
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ss << " uint32_t mask = 0xFFFFFFFFu << shift;\n";
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ss << " return (rt_value & ~mask) | (word << shift);\n";
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ss << "}\n";
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ss << "\n";
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ss << "/* LWR: Load Word Right - merges low bytes from aligned word into rt.\n";
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ss << " * addr is the effective (possibly unaligned) address.\n";
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ss << " * rt_value is the current value of the destination register.\n";
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ss << " * Formula:\n";
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ss << " * aligned_addr = addr & ~3;\n";
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ss << " * shift = (3 - (addr & 3)) * 8;\n";
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ss << " * mask = 0xFFFFFFFF >> shift;\n";
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ss << " * result = (rt_value & ~mask) | (word >> shift);\n";
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ss << " * where word = read_word(aligned_addr).\n";
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ss << " */\n";
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ss << "static uint32_t psx_lwr(CPUState* cpu, uint32_t addr, uint32_t rt_value) {\n";
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ss << " uint32_t aligned_addr = addr & ~3u;\n";
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ss << " uint32_t word = cpu->read_word(aligned_addr);\n";
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ss << " uint32_t shift = (3u - (addr & 3u)) * 8u;\n";
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ss << " uint32_t mask = 0xFFFFFFFFu >> shift;\n";
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ss << " return (rt_value & ~mask) | (word >> shift);\n";
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ss << "}\n";
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ss << "\n";
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ss << "/* SWL: Store Word Left - stores the high bytes of rt_value into memory.\n";
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ss << " * addr is the effective (possibly unaligned) address.\n";
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ss << " * rt_value is the value of the source register.\n";
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ss << " * Formula:\n";
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ss << " * aligned_addr = addr & ~3;\n";
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ss << " * shift = (addr & 3) * 8;\n";
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ss << " * mem_mask = 0xFFFFFFFF >> (32 - shift) [i.e. low 'shift' bits preserved]\n";
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ss << " * Actually:\n";
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ss << " * mask = 0xFFFFFFFF >> shift; [bits to take from rt]\n";
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ss << " * write_word(aligned_addr,\n";
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ss << " * (read_word(aligned_addr) & ~mask) | (rt_value >> shift));\n";
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ss << " */\n";
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ss << "static void psx_swl(CPUState* cpu, uint32_t addr, uint32_t rt_value) {\n";
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ss << " uint32_t aligned_addr = addr & ~3u;\n";
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ss << " uint32_t existing = cpu->read_word(aligned_addr);\n";
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ss << " uint32_t shift = (addr & 3u) * 8u;\n";
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ss << " uint32_t mask = 0xFFFFFFFFu >> shift;\n";
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ss << " cpu->write_word(aligned_addr, (existing & ~mask) | (rt_value >> shift));\n";
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ss << "}\n";
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ss << "\n";
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ss << "/* SWR: Store Word Right - stores the low bytes of rt_value into memory.\n";
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ss << " * addr is the effective (possibly unaligned) address.\n";
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ss << " * rt_value is the value of the source register.\n";
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ss << " * Formula:\n";
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ss << " * aligned_addr = addr & ~3;\n";
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ss << " * shift = (3 - (addr & 3)) * 8;\n";
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ss << " * mask = 0xFFFFFFFF << shift;\n";
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ss << " * write_word(aligned_addr,\n";
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ss << " * (read_word(aligned_addr) & ~mask) | (rt_value << shift));\n";
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ss << " */\n";
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ss << "static void psx_swr(CPUState* cpu, uint32_t addr, uint32_t rt_value) {\n";
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ss << " uint32_t aligned_addr = addr & ~3u;\n";
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ss << " uint32_t existing = cpu->read_word(aligned_addr);\n";
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ss << " uint32_t shift = (3u - (addr & 3u)) * 8u;\n";
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ss << " uint32_t mask = 0xFFFFFFFFu << shift;\n";
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ss << " cpu->write_word(aligned_addr, (existing & ~mask) | (rt_value << shift));\n";
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ss << "}\n";
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ss << "/* LWL/LWR/SWL/SWR implement little-endian R3000A unaligned word\n";
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ss << " * semantics. Keep these switch tables in sync with psx_interpreter.c\n";
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ss << " * and dirty_ram_interp.c.\n";
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ss << " */\n";
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ss << "\n";
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ss << "/* LWL: Load Word Left - merges high bytes from aligned word into rt.\n";
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ss << " * addr is the effective (possibly unaligned) address.\n";
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ss << " * rt_value is the current value of the destination register.\n";
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ss << " */\n";
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ss << "static uint32_t psx_lwl(CPUState* cpu, uint32_t addr, uint32_t rt_value) {\n";
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ss << " uint32_t word = cpu->read_word(addr & ~3u);\n";
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ss << " switch (addr & 3u) {\n";
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ss << " case 0: return (rt_value & 0x00FFFFFFu) | (word << 24);\n";
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ss << " case 1: return (rt_value & 0x0000FFFFu) | (word << 16);\n";
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ss << " case 2: return (rt_value & 0x000000FFu) | (word << 8);\n";
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ss << " default: return word;\n";
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ss << " }\n";
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ss << "}\n";
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ss << "\n";
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ss << "/* LWR: Load Word Right - merges low bytes from aligned word into rt.\n";
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ss << " * addr is the effective (possibly unaligned) address.\n";
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ss << " * rt_value is the current value of the destination register.\n";
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ss << " */\n";
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ss << "static uint32_t psx_lwr(CPUState* cpu, uint32_t addr, uint32_t rt_value) {\n";
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ss << " uint32_t word = cpu->read_word(addr & ~3u);\n";
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ss << " switch (addr & 3u) {\n";
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ss << " case 0: return word;\n";
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ss << " case 1: return (rt_value & 0xFF000000u) | (word >> 8);\n";
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ss << " case 2: return (rt_value & 0xFFFF0000u) | (word >> 16);\n";
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ss << " default: return (rt_value & 0xFFFFFF00u) | (word >> 24);\n";
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ss << " }\n";
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ss << "}\n";
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ss << "\n";
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ss << "/* SWL: Store Word Left - stores the high bytes of rt_value into memory.\n";
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ss << " * addr is the effective (possibly unaligned) address.\n";
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ss << " * rt_value is the value of the source register.\n";
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ss << " */\n";
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ss << "static void psx_swl(CPUState* cpu, uint32_t addr, uint32_t rt_value) {\n";
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ss << " uint32_t aligned_addr = addr & ~3u;\n";
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ss << " uint32_t word = cpu->read_word(aligned_addr);\n";
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ss << " switch (addr & 3u) {\n";
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ss << " case 0: word = (word & 0xFFFFFF00u) | (rt_value >> 24); break;\n";
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ss << " case 1: word = (word & 0xFFFF0000u) | (rt_value >> 16); break;\n";
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ss << " case 2: word = (word & 0xFF000000u) | (rt_value >> 8); break;\n";
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ss << " default: word = rt_value; break;\n";
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ss << " }\n";
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ss << " cpu->write_word(aligned_addr, word);\n";
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ss << "}\n";
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ss << "\n";
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ss << "/* SWR: Store Word Right - stores the low bytes of rt_value into memory.\n";
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ss << " * addr is the effective (possibly unaligned) address.\n";
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ss << " * rt_value is the value of the source register.\n";
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ss << " */\n";
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ss << "static void psx_swr(CPUState* cpu, uint32_t addr, uint32_t rt_value) {\n";
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ss << " uint32_t aligned_addr = addr & ~3u;\n";
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ss << " uint32_t word = cpu->read_word(aligned_addr);\n";
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ss << " switch (addr & 3u) {\n";
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ss << " case 0: word = rt_value; break;\n";
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ss << " case 1: word = (word & 0x000000FFu) | (rt_value << 8); break;\n";
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ss << " case 2: word = (word & 0x0000FFFFu) | (rt_value << 16); break;\n";
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ss << " default: word = (word & 0x00FFFFFFu) | (rt_value << 24); break;\n";
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ss << " }\n";
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ss << " cpu->write_word(aligned_addr, word);\n";
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ss << "}\n";
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ss << "\n";
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// Make mutable copies for potential function splitting
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