psxrecomp

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Author	SHA1	Message	Date
Matthew Stanley	25474410d0	recompiler: state-continuation discovery + psxrecomp-game build target Add Pass 2.6 to FunctionAnalyzer: detect JAL targets whose callee starts with `sw $ra, imm($a0)` (SaveState-style context-save helpers) and force the post-delay-slot PC into the dispatch table. Recovers continuation entries that aren't reached by JAL prologue or jr $ra discovery. Extend find_function_start to recognize `lui rt; lw rt, off(rt)` 8 bytes before jr $ra as a prologue marker. Rewrite analyze_function block-build from std::set boundaries to a sorted std::vector + binary_search. main_psx CLI: --seeds, --out-dir, --strict, --inspect; out_dir support. Add psxrecomp-game executable target alongside PSXRecomp. code_generator: reg_name() now emits cpu->gpr[N] consistently (matching what the rest of the codegen already emitted — the old reg_names[] table returning cpu->v0/cpu->ra was unreachable because CPUState has no named fields, only gpr[32]). LWL/LWR/SWL/SWR moved from cpu->lwl(...) member form to psx_lwl(cpu, ...) free-function form for game-EXE codegen reuse. Remove a stray fmt::print left in build_basic_blocks that spammed stdout on every regen — per the no-stdio-debug rule (memory v4). Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>	2026-05-10 22:50:01 -07:00
Matthew Stanley	7c40d33db3	Phase 1 complete: recompiler proven correct on SCPH1001.BIN Phase 1a (boot slice): 30 instructions at 0xBFC00000, compiles clean. Phase 1b (instruction coverage): 54 opcodes implemented in strict_translator, 44,629 walker-reachable instructions covered, 0 missing. Phase 1c (function discovery): 76 functions from 2 seeds, 2,988 instructions, 199 call edges, 27 indirect jumps. All validated through StrictTranslator. Phase 1d (indirect control flow): 27 sites classified — 21 A0/B0/C0 dispatch stubs, 4 computed calls, 2 computed tail calls. Ghidra cross-referenced with 0 disagreements. Phase 1e (relocation): ROM-to-RAM copy at FUN_bfc00420 proven with both Ghidra (static) and DuckStation (runtime). 69 address aliases, 68/69 function entries match byte-for-byte in RAM. Normalization rule documented. Includes PRINCIPLES.md and DEBUG.md adapted from recomp-template. Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>	2026-04-11 21:26:04 -07:00

Author

SHA1

Message

Date

Matthew Stanley

25474410d0

recompiler: state-continuation discovery + psxrecomp-game build target

Add Pass 2.6 to FunctionAnalyzer: detect JAL targets whose callee starts
with `sw $ra, imm($a0)` (SaveState-style context-save helpers) and force
the post-delay-slot PC into the dispatch table. Recovers continuation
entries that aren't reached by JAL prologue or jr $ra discovery.

Extend find_function_start to recognize `lui rt; lw rt, off(rt)` 8 bytes
before jr $ra as a prologue marker. Rewrite analyze_function block-build
from std::set boundaries to a sorted std::vector + binary_search.

main_psx CLI: --seeds, --out-dir, --strict, --inspect; out_dir support.
Add psxrecomp-game executable target alongside PSXRecomp.

code_generator: reg_name() now emits cpu->gpr[N] consistently (matching
what the rest of the codegen already emitted — the old reg_names[] table
returning cpu->v0/cpu->ra was unreachable because CPUState has no named
fields, only gpr[32]). LWL/LWR/SWL/SWR moved from cpu->lwl(...) member
form to psx_lwl(cpu, ...) free-function form for game-EXE codegen reuse.

Remove a stray fmt::print left in build_basic_blocks that spammed
stdout on every regen — per the no-stdio-debug rule (memory v4).

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

2026-05-10 22:50:01 -07:00

Matthew Stanley

7c40d33db3

Phase 1 complete: recompiler proven correct on SCPH1001.BIN

Phase 1a (boot slice): 30 instructions at 0xBFC00000, compiles clean.
Phase 1b (instruction coverage): 54 opcodes implemented in strict_translator,
  44,629 walker-reachable instructions covered, 0 missing.
Phase 1c (function discovery): 76 functions from 2 seeds, 2,988 instructions,
  199 call edges, 27 indirect jumps. All validated through StrictTranslator.
Phase 1d (indirect control flow): 27 sites classified — 21 A0/B0/C0 dispatch
  stubs, 4 computed calls, 2 computed tail calls. Ghidra cross-referenced
  with 0 disagreements.
Phase 1e (relocation): ROM-to-RAM copy at FUN_bfc00420 proven with both
  Ghidra (static) and DuckStation (runtime). 69 address aliases, 68/69
  function entries match byte-for-byte in RAM. Normalization rule documented.

Includes PRINCIPLES.md and DEBUG.md adapted from recomp-template.

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

2026-04-11 21:26:04 -07:00

2 Commits