mirror of
https://github.com/RetroPortingToolKit/psxrecomp
synced 2026-10-27 10:38:46 -04:00
Matthew Stanley
7c40d33db3
Phase 1a (boot slice): 30 instructions at 0xBFC00000, compiles clean. Phase 1b (instruction coverage): 54 opcodes implemented in strict_translator, 44,629 walker-reachable instructions covered, 0 missing. Phase 1c (function discovery): 76 functions from 2 seeds, 2,988 instructions, 199 call edges, 27 indirect jumps. All validated through StrictTranslator. Phase 1d (indirect control flow): 27 sites classified — 21 A0/B0/C0 dispatch stubs, 4 computed calls, 2 computed tail calls. Ghidra cross-referenced with 0 disagreements. Phase 1e (relocation): ROM-to-RAM copy at FUN_bfc00420 proven with both Ghidra (static) and DuckStation (runtime). 69 address aliases, 68/69 function entries match byte-for-byte in RAM. Normalization rule documented. Includes PRINCIPLES.md and DEBUG.md adapted from recomp-template. Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
81 lines
2.9 KiB
C
81 lines
2.9 KiB
C
/* SPDX-FileCopyrightText: © 2022-2023 Decompollaborate */
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/* SPDX-License-Identifier: MIT */
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#ifndef RABBITIZER_CONFIG_H
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#define RABBITIZER_CONFIG_H
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#include <stdbool.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "generated/Abi_enum.h"
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RabbitizerAbi RabbitizerAbi_fromStr(const char *name);
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typedef struct RabbitizerConfig_RegisterNames {
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bool namedRegisters; // Enables using named registers. This option takes precedence over the other named register options
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RabbitizerAbi gprAbiNames; // The ABI names to be used for general purpose registers when disassembling the main processor's instructions
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RabbitizerAbi fprAbiNames; // The ABI names to be used for floating point registers when disassembling the floating point (coprocessor 1) instructions
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bool userFpcCsr; // Use FpcCsr as register $31 for the FP control/status register
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bool vr4300Cop0NamedRegisters; // Use named registers for VR4300's coprocessor 0 registers
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bool vr4300RspCop0NamedRegisters; // Use named registers for VR4300's RSP's coprocessor 0 registers
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} RabbitizerConfig_RegisterNames;
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typedef struct RabbitizerConfig_PseudoInstr {
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bool enablePseudos; // Produce pseudo instructions (like `move` or `b`) whenever those may match the desired original instruction
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bool pseudoBeqz;
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bool pseudoBnez;
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bool pseudoB;
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bool pseudoMove;
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bool pseudoNot;
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bool pseudoNegu;
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bool pseudoBal;
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} RabbitizerConfig_PseudoInstr;
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typedef struct RabbitizerConfig_ToolchainTweaks {
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bool treatJAsUnconditionalBranch;
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/**
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* Enables a few fixes for SN64's assembler related to div/divu instructions
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*
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* - SN64's assembler doesn't like assembling `div $0, a, b` with .set noat active.
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* Removing the $0 fixes this issue (but not for handwritten asm)
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*
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* - SN64's assembler expands div to have break if dividing by zero
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* However, the break it generates is different than the one it generates with `break N`
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* So we replace break instrutions for SN64 with the exact word that the assembler generates when expanding div
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*/
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bool sn64DivFix;
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/**
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* Enables various tweaks to allow building matching with GNU as which
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* break original compiler behavior and what's specified in the manuals.
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*/
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bool gnuMode;
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} RabbitizerConfig_ToolchainTweaks;
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typedef struct RabbitizerConfig_Misc {
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int opcodeLJust; // The minimal number of characters to left-align the opcode name
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bool unknownInstrComment; // Generate a pseudo-disassembly comment when disassembling non implemented instructions
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bool omit0XOnSmallImm;
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bool upperCaseImm;
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} RabbitizerConfig_Misc;
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typedef struct RabbitizerConfig {
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RabbitizerConfig_RegisterNames regNames;
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RabbitizerConfig_PseudoInstr pseudos;
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RabbitizerConfig_ToolchainTweaks toolchainTweaks;
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RabbitizerConfig_Misc misc;
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} RabbitizerConfig;
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extern RabbitizerConfig RabbitizerConfig_Cfg;
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#ifdef __cplusplus
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}
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#endif
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#endif
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