mirror of
https://github.com/RetroPortingToolKit/psxrecomp
synced 2026-10-26 02:11:36 -04:00
Matthew Stanley
415 lines
16 KiB
C++
415 lines
16 KiB
C++
/*
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* L2 Structural Test — Codegen Pattern Verification
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*
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* For each MIPS instruction form, decodes the instruction, translates it
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* via StrictTranslator, and verifies the generated C code contains the
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* expected register references and operation patterns.
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*
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* This is the "snesrecomp-style" approach: structural pattern matching on
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* the generated C text. It catches wrong register indices, missing
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* operations, and translation gaps. It does NOT verify semantic
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* correctness (that requires L2-semantic with actual execution).
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*
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* Exit codes:
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* 0 all forms pass
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* 1 at least one form fails
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* 2 usage error
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*/
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#include <cstdio>
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#include <cstdint>
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#include <cstring>
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#include <string>
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#include <vector>
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#include <functional>
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#include "mips_decoder.h"
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#include "strict_translator.h"
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#include "gte_register_classification.h"
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#include "fmt/format.h"
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using PSXRecomp::MipsDecoder;
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using PSXRecomp::DecodedInstruction;
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using PSXRecompV4::StrictTranslator;
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using PSXRecompV4::TranslateResult;
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// ── Helpers ─────────────────────────────────────────────────────────────
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static bool contains(const std::string& haystack, const std::string& needle) {
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return haystack.find(needle) != std::string::npos;
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}
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// MIPS instruction encoding helpers
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static constexpr uint32_t R_TYPE(uint8_t rs, uint8_t rt, uint8_t rd, uint8_t sa, uint8_t fn) {
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return (0u << 26) | ((uint32_t)rs << 21) | ((uint32_t)rt << 16)
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| ((uint32_t)rd << 11) | ((uint32_t)sa << 6) | fn;
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}
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static constexpr uint32_t I_TYPE(uint8_t op, uint8_t rs, uint8_t rt, uint16_t imm) {
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return ((uint32_t)op << 26) | ((uint32_t)rs << 21) | ((uint32_t)rt << 16) | imm;
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}
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// Standard test registers: v0(2), v1(3), a0(4)
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static constexpr uint8_t V0 = 2, V1 = 3, A0 = 4;
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// ── Form definition ─────────────────────────────────────────────────────
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struct Form {
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uint32_t word;
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const char* name;
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// Checker: given the TranslateResult, return empty string on pass
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// or an error message on failure.
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std::function<std::string(const TranslateResult&)> check;
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};
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// Shorthand: check that translation is supported and c_code contains all
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// of the given substrings.
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static auto must_contain(std::initializer_list<const char*> needles) {
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std::vector<std::string> v(needles.begin(), needles.end());
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return [v](const TranslateResult& r) -> std::string {
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if (!r.supported)
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return fmt::format("unsupported: {}", r.fail_reason);
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for (auto& n : v) {
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if (!contains(r.c_code, n))
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return fmt::format("missing '{}' in: {}", n, r.c_code);
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}
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return "";
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};
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}
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// Check supported + custom lambda on c_code
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static auto check_code(std::function<std::string(const std::string&)> fn) {
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return [fn](const TranslateResult& r) -> std::string {
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if (!r.supported)
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return fmt::format("unsupported: {}", r.fail_reason);
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return fn(r.c_code);
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};
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}
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// Check that host-visible operations occur in a specific source order. This
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// matters for overlay stores: the DLL-local cycle batch must be published
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// before an MMIO write or SWL/SWR's read-modify-write begins.
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static auto must_contain_in_order(std::initializer_list<const char*> needles) {
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std::vector<std::string> v(needles.begin(), needles.end());
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return check_code([v](const std::string& c) -> std::string {
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std::string::size_type pos = 0;
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for (const auto& n : v) {
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const auto found = c.find(n, pos);
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if (found == std::string::npos)
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return fmt::format("missing/out-of-order '{}' in: {}", n, c);
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pos = found + n.size();
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}
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return "";
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});
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}
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// ── Form table ──────────────────────────────────────────────────────────
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static const Form kForms[] = {
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// === SPECIAL (R-type) ALU ===
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// SLL $v0, $a0, 1
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{ R_TYPE(0, A0, V0, 1, 0x00), "sll_v0_a0_1",
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must_contain({"gpr[2]", "gpr[4]", "<< 1u"}) },
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// SRL $v0, $a0, 1
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{ R_TYPE(0, A0, V0, 1, 0x02), "srl_v0_a0_1",
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must_contain({"gpr[2]", "gpr[4]", ">> 1u"}) },
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// SRA $v0, $a0, 1
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{ R_TYPE(0, A0, V0, 1, 0x03), "sra_v0_a0_1",
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must_contain({"gpr[2]", "int32_t", "gpr[4]", ">> 1u"}) },
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// SLLV $v0, $a0, $v1
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{ R_TYPE(V1, A0, V0, 0, 0x04), "sllv_v0_a0_v1",
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must_contain({"gpr[2]", "gpr[4]", "gpr[3]", "0x1Fu"}) },
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// SRLV $v0, $a0, $v1
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{ R_TYPE(V1, A0, V0, 0, 0x06), "srlv_v0_a0_v1",
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must_contain({"gpr[2]", "gpr[4]", "gpr[3]", "0x1Fu"}) },
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// SRAV $v0, $a0, $v1
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{ R_TYPE(V1, A0, V0, 0, 0x07), "srav_v0_a0_v1",
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must_contain({"gpr[2]", "int32_t", "gpr[4]", "gpr[3]", "0x1Fu"}) },
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// ADDU $v0, $v1, $a0
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{ R_TYPE(V1, A0, V0, 0, 0x21), "addu_v0_v1_a0",
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must_contain({"gpr[2]", "gpr[3]", "gpr[4]", "+"}) },
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// SUBU $v0, $v1, $a0
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{ R_TYPE(V1, A0, V0, 0, 0x23), "subu_v0_v1_a0",
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must_contain({"gpr[2]", "gpr[3]", "gpr[4]", "-"}) },
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// AND $v0, $v1, $a0
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{ R_TYPE(V1, A0, V0, 0, 0x24), "and_v0_v1_a0",
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must_contain({"gpr[2]", "gpr[3]", "gpr[4]", "&"}) },
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// OR $v0, $v1, $a0
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{ R_TYPE(V1, A0, V0, 0, 0x25), "or_v0_v1_a0",
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must_contain({"gpr[2]", "gpr[3]", "gpr[4]", "|"}) },
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// XOR $v0, $v1, $a0
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{ R_TYPE(V1, A0, V0, 0, 0x26), "xor_v0_v1_a0",
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must_contain({"gpr[2]", "gpr[3]", "gpr[4]", "^"}) },
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// NOR $v0, $v1, $a0
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{ R_TYPE(V1, A0, V0, 0, 0x27), "nor_v0_v1_a0",
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must_contain({"gpr[2]", "gpr[3]", "gpr[4]", "~"}) },
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// SLT $v0, $v1, $a0
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{ R_TYPE(V1, A0, V0, 0, 0x2A), "slt_v0_v1_a0",
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must_contain({"gpr[2]", "int32_t", "gpr[3]", "gpr[4]"}) },
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// SLTU $v0, $v1, $a0
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{ R_TYPE(V1, A0, V0, 0, 0x2B), "sltu_v0_v1_a0",
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must_contain({"gpr[2]", "gpr[3]", "gpr[4]", "<"}) },
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// JR $at: target must be snapshotted before its delay slot.
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{ R_TYPE(1, 0, 0, 0, 0x08), "jr_at_latches_target",
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[](const TranslateResult& r) -> std::string {
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if (!r.supported) return fmt::format("unsupported: {}", r.fail_reason);
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if (!contains(r.pre_delay_code, "psx_jt_00000000 = cpu->gpr[1]"))
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return fmt::format("missing pre-delay target latch: {}", r.pre_delay_code);
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if (!contains(r.c_code, "cpu->pc = psx_jt_00000000"))
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return fmt::format("terminator does not use latched target: {}", r.c_code);
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if (contains(r.c_code, "cpu->pc = cpu->gpr[1]"))
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return fmt::format("terminator rereads target after delay: {}", r.c_code);
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return "";
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}},
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// JALR $at,$at: capture must precede link write (rd==rs alias-safe).
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{ R_TYPE(1, 0, 1, 0, 0x09), "jalr_at_at_latches_before_link",
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[](const TranslateResult& r) -> std::string {
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if (!r.supported) return fmt::format("unsupported: {}", r.fail_reason);
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const auto latch = r.pre_delay_code.find("psx_jt_00000000 = cpu->gpr[1]");
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const auto link = r.pre_delay_code.find("cpu->gpr[1] = 0x00000008u");
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if (latch == std::string::npos || link == std::string::npos || latch > link)
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return fmt::format("target not latched before aliased link: {}", r.pre_delay_code);
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if (!contains(r.c_code, "cpu->pc = psx_jt_00000000"))
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return fmt::format("terminator does not use latched target: {}", r.c_code);
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return "";
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}},
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// ADD $v0, $v1, $a0 (with overflow trap)
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{ R_TYPE(V1, A0, V0, 0, 0x20), "add_v0_v1_a0",
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must_contain({"gpr[2]", "gpr[3]", "gpr[4]", "psx_arith_overflow"}) },
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// MULTU $v1, $a0
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{ R_TYPE(V1, A0, 0, 0, 0x19), "multu_v1_a0",
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must_contain({"cpu->hi", "cpu->lo", "gpr[3]", "gpr[4]", "uint64_t"}) },
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// DIV $v1, $a0
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{ R_TYPE(V1, A0, 0, 0, 0x1A), "div_v1_a0",
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must_contain({"cpu->hi", "cpu->lo", "gpr[3]", "gpr[4]"}) },
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// DIVU $v1, $a0
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{ R_TYPE(V1, A0, 0, 0, 0x1B), "divu_v1_a0",
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must_contain({"cpu->hi", "cpu->lo", "gpr[3]", "gpr[4]"}) },
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// MFHI $v0
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{ R_TYPE(0, 0, V0, 0, 0x10), "mfhi_v0",
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must_contain({"gpr[2]", "cpu->hi"}) },
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// MFLO $v0
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{ R_TYPE(0, 0, V0, 0, 0x12), "mflo_v0",
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must_contain({"gpr[2]", "cpu->lo"}) },
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// MTHI $v1
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{ R_TYPE(V1, 0, 0, 0, 0x11), "mthi_v1",
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must_contain({"cpu->hi", "gpr[3]"}) },
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// MTLO $v1
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{ R_TYPE(V1, 0, 0, 0, 0x13), "mtlo_v1",
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must_contain({"cpu->lo", "gpr[3]"}) },
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// === Immediate ALU ===
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// ADDIU $v0, $v1, 42
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{ I_TYPE(0x09, V1, V0, 42), "addiu_v0_v1_42",
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must_contain({"gpr[2]", "gpr[3]", "42"}) },
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// ADDI $v0, $v1, 42 (with overflow trap)
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{ I_TYPE(0x08, V1, V0, 42), "addi_v0_v1_42",
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must_contain({"gpr[2]", "gpr[3]", "42", "psx_arith_overflow"}) },
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// ANDI $v0, $v1, 0xFF
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{ I_TYPE(0x0C, V1, V0, 0xFF), "andi_v0_v1_ff",
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must_contain({"gpr[2]", "gpr[3]", "0xFFu"}) },
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// ORI $v0, $v1, 0xFF
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{ I_TYPE(0x0D, V1, V0, 0xFF), "ori_v0_v1_ff",
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must_contain({"gpr[2]", "gpr[3]", "0xFFu"}) },
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// XORI $v0, $v1, 0xFF
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{ I_TYPE(0x0E, V1, V0, 0xFF), "xori_v0_v1_ff",
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must_contain({"gpr[2]", "gpr[3]", "0xFFu"}) },
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// LUI $v0, 0x8000
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{ I_TYPE(0x0F, 0, V0, 0x8000), "lui_v0_8000",
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must_contain({"gpr[2]", "0x80000000u"}) },
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// SLTI $v0, $v1, 42
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{ I_TYPE(0x0A, V1, V0, 42), "slti_v0_v1_42",
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must_contain({"gpr[2]", "int32_t", "gpr[3]", "42"}) },
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// SLTIU $v0, $v1, 42
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{ I_TYPE(0x0B, V1, V0, 42), "sltiu_v0_v1_42",
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must_contain({"gpr[2]", "gpr[3]", "<"}) },
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// === Load/Store ===
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// LW $v0, 0($v1)
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{ I_TYPE(0x23, V1, V0, 0), "lw_v0_0_v1",
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must_contain({"gpr[2]", "gpr[3]", "load_word"}) },
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// SW $a0, 0($v1)
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{ I_TYPE(0x2B, V1, A0, 0), "sw_a0_0_v1",
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must_contain_in_order({"psx_store_cycle_barrier()", "write_word"}) },
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// LB $v0, 0($v1)
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{ I_TYPE(0x20, V1, V0, 0), "lb_v0_0_v1",
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must_contain({"gpr[2]", "gpr[3]", "load_byte", "int8_t"}) },
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// LBU $v0, 0($v1)
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{ I_TYPE(0x24, V1, V0, 0), "lbu_v0_0_v1",
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must_contain({"gpr[2]", "gpr[3]", "load_byte"}) },
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// LH $v0, 0($v1)
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{ I_TYPE(0x21, V1, V0, 0), "lh_v0_0_v1",
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must_contain({"gpr[2]", "gpr[3]", "load_half", "int16_t"}) },
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// LHU $v0, 0($v1)
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{ I_TYPE(0x25, V1, V0, 0), "lhu_v0_0_v1",
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must_contain({"gpr[2]", "gpr[3]", "load_half"}) },
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// SB $a0, 0($v1)
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{ I_TYPE(0x28, V1, A0, 0), "sb_a0_0_v1",
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must_contain_in_order({"psx_store_cycle_barrier()", "write_byte"}) },
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// SH $a0, 0($v1)
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{ I_TYPE(0x29, V1, A0, 0), "sh_a0_0_v1",
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must_contain_in_order({"psx_store_cycle_barrier()", "write_half"}) },
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// SWL/SWR are read-modify-write stores. Publishing after the raw read is
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// too late because the read itself may be MMIO and host-visible.
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{ I_TYPE(0x2A, V1, A0, 1), "swl_a0_1_v1",
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must_contain_in_order({"psx_store_cycle_barrier()", "read_word", "write_word"}) },
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{ I_TYPE(0x2E, V1, A0, 2), "swr_a0_2_v1",
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must_contain_in_order({"psx_store_cycle_barrier()", "read_word", "write_word"}) },
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// SWC2 must include the GTE stall in the published timestamp, then expose
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// that timestamp before the memory and precision-shadow side effects.
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{ I_TYPE(0x3A, V1, A0, 0), "swc2_a0_0_v1",
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must_contain_in_order({"psx_gte_stall", "psx_store_cycle_barrier()", "write_word",
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"gte_precision_store_word"}) },
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// === COP0 ===
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// MFC0 $v0, $12 (read SR)
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{ I_TYPE(0x10, 0x00, V0, 12 << 11), "mfc0_v0_sr",
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check_code([](const std::string& c) -> std::string {
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if (!contains(c, "gpr[2]")) return "missing gpr[2]";
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if (!contains(c, "cop0[12]")) return "missing cop0[12]";
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return "";
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})},
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// MTC0 $v1, $12 (write SR)
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{ I_TYPE(0x10, 0x04, V1, 12 << 11), "mtc0_v1_sr",
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check_code([](const std::string& c) -> std::string {
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if (!contains(c, "gpr[3]")) return "missing gpr[3]";
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if (!contains(c, "cop0[12]")) return "missing cop0[12]";
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return "";
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})},
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// === $zero writes should be discarded ===
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// ADDIU $zero, $v1, 1 → should be discarded/commented
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{ I_TYPE(0x09, V1, 0, 1), "addiu_zero_v1_1",
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check_code([](const std::string& c) -> std::string {
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// Must not actually write to gpr[0] — should be a comment or no-op
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if (contains(c, "gpr[0] =") && !contains(c, "/*"))
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return "writes to $zero without discard";
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return "";
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})},
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// NOP (SLL $zero, $zero, 0 = 0x00000000)
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{ 0x00000000, "nop",
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check_code([](const std::string& c) -> std::string {
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// NOP should produce empty or nop comment
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if (c.size() > 40 && !contains(c, "nop"))
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return fmt::format("suspicious NOP output: {}", c);
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return "";
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})},
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};
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// ── main ────────────────────────────────────────────────────────────────
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int main(int argc, char** argv) {
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bool verbose = false;
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for (int i = 1; i < argc; i++) {
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if (std::strcmp(argv[i], "-v") == 0 || std::strcmp(argv[i], "--verbose") == 0)
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verbose = true;
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}
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int total = 0, pass = 0, fail = 0;
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for (const auto& form : kForms) {
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total++;
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DecodedInstruction d = MipsDecoder::decode(form.word, 0);
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TranslateResult r = StrictTranslator::translate(d);
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std::string err = form.check(r);
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if (err.empty()) {
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pass++;
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if (verbose)
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fmt::print(" PASS {:<30s} {}\n", form.name, r.c_code);
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} else {
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fail++;
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fmt::print(" FAIL {:<30s} {}\n", form.name, err);
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if (verbose)
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fmt::print(" c_code: {}\n", r.c_code);
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}
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}
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// Exhaustively lock the helper/raw classification for every COP2 register
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// and transfer form. This prevents native BIOS/overlay code from drifting
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// away from the interpreter's canonical register semantics.
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const auto check_gte_helper = [&](uint32_t word, const std::string& call,
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bool expected, const char *kind,
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uint8_t reg) {
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++total;
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const TranslateResult r = StrictTranslator::translate(
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MipsDecoder::decode(word, 0));
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const bool actual = r.supported && contains(r.c_code, call);
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if (actual == expected) {
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++pass;
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} else {
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++fail;
|
|
fmt::print(" FAIL strict GTE {} reg {} helper={} expected={} code={}\n",
|
|
kind, reg, actual, expected, r.c_code);
|
|
}
|
|
};
|
|
for (uint8_t reg = 0; reg < 32; ++reg) {
|
|
const uint32_t cop2 = 0x12u << 26;
|
|
check_gte_helper(cop2 | (0x00u << 21) | (V0 << 16) | (uint32_t(reg) << 11),
|
|
fmt::format("gte_read_data(cpu, {})", reg),
|
|
PSXRecompGTERegisters::data_read_needs_helper(reg), "MFC2", reg);
|
|
check_gte_helper(cop2 | (0x02u << 21) | (V0 << 16) | (uint32_t(reg) << 11),
|
|
fmt::format("gte_read_ctrl(cpu, {})", reg),
|
|
PSXRecompGTERegisters::ctrl_read_needs_helper(reg), "CFC2", reg);
|
|
check_gte_helper(cop2 | (0x04u << 21) | (V0 << 16) | (uint32_t(reg) << 11),
|
|
fmt::format("gte_write_data(cpu, {}", reg),
|
|
PSXRecompGTERegisters::data_write_needs_helper(reg), "MTC2", reg);
|
|
check_gte_helper(cop2 | (0x06u << 21) | (V0 << 16) | (uint32_t(reg) << 11),
|
|
fmt::format("gte_write_ctrl(cpu, {}", reg),
|
|
PSXRecompGTERegisters::ctrl_write_needs_helper(reg), "CTC2", reg);
|
|
check_gte_helper(I_TYPE(0x32, V1, reg, 0),
|
|
fmt::format("gte_write_data(cpu, {}", reg),
|
|
PSXRecompGTERegisters::data_write_needs_helper(reg), "LWC2", reg);
|
|
check_gte_helper(I_TYPE(0x3A, V1, reg, 0),
|
|
fmt::format("gte_read_data(cpu, {})", reg),
|
|
PSXRecompGTERegisters::data_read_needs_helper(reg), "SWC2", reg);
|
|
}
|
|
|
|
fmt::print("\nL2 structural: {}/{} ok", pass, total);
|
|
if (fail > 0) fmt::print(" ({} failures)", fail);
|
|
fmt::print("\n");
|
|
|
|
return fail > 0 ? 1 : 0;
|
|
}
|