mirror of
https://github.com/RetroPortingToolKit/psxrecomp
synced 2026-10-26 10:19:47 -04:00
Matthew Stanley
68 lines
3.5 KiB
C
68 lines
3.5 KiB
C
/* cosim_state.h — full-architectural-state canonical hash for the first-divergence
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* co-simulation oracle. See COSIM_ORACLE.md.
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*
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* The single correctness rule: this hash must cover EVERY piece of state that can
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* influence future guest execution, and NOTHING that is host-only (pointers, padding,
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* jmpbufs, fiber/malloc addresses). A missed execution-relevant field is a blind spot
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* (false "no divergence"); an included host-only field is a false positive. The
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* validation gates in COSIM_ORACLE.md (compiled-vs-compiled == 0, injected-divergence
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* halts at the right field) exist to prove this list is exactly right.
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*/
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#pragma once
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#include <stdint.h>
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#include "cpu_state.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Per-subsystem sub-hashes so a mismatch localizes to a subsystem before a full
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* field/byte diff. All 64-bit FNV-1a over canonical little-endian serialization. */
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typedef struct {
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uint64_t cpu; /* GPRs/HI/LO/PC/COP0/GTE + micro-state (muldiv/gte/load-delay) */
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uint64_t irqctl; /* i_stat/i_mask + interrupts.c timing statics + VBLANK schedule */
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uint64_t ram; /* 2MB main RAM (incremental page-hash) */
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uint64_t scratch; /* 1KB scratchpad */
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uint64_t vram; /* 1MB VRAM (incremental page-hash) */
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uint64_t gpu; /* GPU regs + FIFO + draw budget + deadlines (boot_state blob) */
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uint64_t spu; /* SPU regs + voices + SPU RAM */
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uint64_t cdrom; /* CDROM command/FIFO/phase/next-event */
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uint64_t dma; /* DMA channel regs + in-flight/deadlines */
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uint64_t sio; /* SIO/pad/memcard transaction state */
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uint64_t timers; /* RootCounters counter/mode/target/frac/last-update */
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uint64_t clock; /* psx_cycle_count */
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uint64_t dirty; /* dirty-RAM page bitmap (affects dispatch/interp routing) */
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} CosimSubHashes;
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/* Compute the full canonical state hash of the LIVE machine (debug_cpu_ptr + globals).
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* Fills `sub` (may be NULL) and returns the folded top hash. Cheap per call: RAM/VRAM
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* use incremental page hashes maintained by cosim_note_ram_write/cosim_note_vram_write;
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* everything else is small. */
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uint64_t cosim_state_hash(CosimSubHashes *sub);
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/* Incremental page-hash maintenance. Call from the RAM/VRAM write chokepoints in the
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* cosim build: mark the touched page dirty (cheap); the page hash is recomputed lazily
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* inside cosim_state_hash(). phys is the byte offset into RAM (0..2MB) / VRAM (0..1MB). */
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void cosim_note_ram_write(uint32_t phys, uint32_t nbytes);
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void cosim_note_vram_write(uint32_t byte_off, uint32_t nbytes);
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/* Reset all incremental state (call once at machine init / after a full state load). */
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void cosim_state_reset(void);
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/* ---- engine (cosim.c) ---- */
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void cosim_init(void); /* start the TCP oracle server (call once at startup) */
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void cosim_block(uint32_t pc); /* block-leader pc stash (emitted + interp), reporting */
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uint32_t cosim_last_block(void); /* last block-leader pc, for diagnostic attribution */
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void cosim_tick(void); /* cycle-keyed checkpoint (called from psx_advance_cycles) */
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void cosim_instr(uint32_t pc); /* retire pending cycle checkpoints at an instruction boundary */
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uint32_t cosim_cycles_to_next_checkpoint(void);
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/* Gate-4 fault injection: after this is armed, the next cosim_state_hash perturbs one
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* byte of RAM (addr) or one CPU GPR (reg 0..31, hi=32, lo=33) by XOR val, so the
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* oracle MUST halt at exactly that field. Returns via the same hash path. */
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void cosim_inject_ram(uint32_t phys, uint8_t xor_val);
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void cosim_inject_reg(int reg_index, uint32_t xor_val);
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#ifdef __cplusplus
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}
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#endif
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