Files
psxrecomp/runtime/tests/test_netplay_sim_pad_cache.c
Shokunin a2bbf961ec netplay: expose published seat pads and seat count; unconfirmed load barrier in both modes
- psx_netplay_seat_count() and psx_netplay_sim_pad(seat, out): the pad row
  last published to SIO for each seat at the current simulation tick,
  following delay-sync publication and rollback's sealed overrides, for a
  game hook whose title reads more players than its SIO protocol exposes
  (R4 Link Battle). Host-only cache, never serialized; republished on
  every admitted or replayed tick.
- Load barrier: while a slower peer is still applying a save, neither
  mode waits for confirmation from an already-frozen peer (rollback did
  this already); after mutual ready, both modes resume on a confirmed
  first tick instead of rollback inventing it, so peers cannot run
  different inputs from the identical restored state.

From the R4 Link Battle branch; its headless input probe is dropped
because master already honours debug input on headless peers.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-05 14:17:22 -07:00

25 lines
1.0 KiB
C

#include "netplay_sim_pad_cache.h"
#include <assert.h>
#include <string.h>
int main(void)
{
PsxNetplaySimPadCache cache = {0};
PsxNetPad predicted = {0xFFFEu, 0x80, 0x80, 0x80, 0x80, 0, 1};
PsxNetPad sealed = {0xFFF7u, 0x81, 0x80, 0x80, 0x80, 1, 1};
PsxNetPad out;
memset(&out, 0x5a, sizeof(out));
assert(!psx_netplay_sim_pad_cache_read(&cache, 2, 4, 17, &out));
psx_netplay_sim_pad_cache_publish(&cache, 2, 17, &predicted);
assert(psx_netplay_sim_pad_cache_read(&cache, 2, 4, 17, &out));
assert(memcmp(&out, &predicted, sizeof(out)) == 0);
psx_netplay_sim_pad_cache_publish(&cache, 2, 17, &sealed);
assert(psx_netplay_sim_pad_cache_read(&cache, 2, 4, 17, &out));
assert(memcmp(&out, &sealed, sizeof(out)) == 0);
assert(!psx_netplay_sim_pad_cache_read(&cache, 2, 4, 18, &out));
assert(!psx_netplay_sim_pad_cache_read(&cache, 4, 4, 17, &out));
psx_netplay_sim_pad_cache_reset(&cache);
assert(!psx_netplay_sim_pad_cache_read(&cache, 2, 4, 17, &out));
return 0;
}