mirror of
https://github.com/RetroPortingToolKit/psxrecomp
synced 2026-10-28 10:59:16 -04:00
Shokunin
1c56a8b78c
With the delay-slot fix the Beetle deltas were sane but not comparable: the three unrolled call sequences sat at different I-cache line offsets, and probe_run shared a line with seeded, so the KUSEG run found its first line already filled. Beetle read 59/59/89 (KUSEG/KSEG0/KSEG1), where the fetch model predicts a 23-cycle KSEG1 surcharge. Pad each call sequence so its first T2 read starts a line, and start probe_run on its own line. Beetle (disc boot, OpenBIOS and SCPH-1001 alike) now reads 56/56/82: KUSEG equals KSEG0, and KSEG1 exceeds them by 26 cycles, exactly the Beetle fetch-model difference for the 15 KSEG1 fetches (60 vs a cold cached 34). probe_run moves to 0x000100F0. Ledger ids are unchanged; fetch-tag-segment counts 30 tags and alias-fetch-coherence reads 22 vs Beetle 11, because leaf now straddles two lines. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
249 lines
10 KiB
Python
249 lines
10 KiB
Python
#!/usr/bin/env python3
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"""gen_segment_exe.py - a synthetic KUSEG-linked PS-X EXE for segment-aware code.
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docs/SEGMENT_AWARE_CODE.md is the design this program tests.
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The header carries KUSEG addresses (load and entry 0x00010000), as Alien
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Resurrection (SLUS-00633) and Kula World (SCES-01000) do. On hardware, and in
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Beetle, the whole program then runs with KUSEG PCs. Every `jal` inherits the
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segment of the PC that executes it (Beetle cpu.c DO_BRANCH, mask 0xF0000000).
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So the link values it writes, the EPCs it produces and the I-cache tags it
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fetches with are all KUSEG.
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The program exercises each place the segment reaches:
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R+0x00 $ra seen by `leaf` after `jal` (link, KUSEG)
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R+0x04 $ra seen by `leaf` after `bgezal` (link, KUSEG)
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R+0x08 $ra seen by `seeded` after `jalr` (link, KUSEG)
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R+0x10 T2 ticks around `probe_run` at its KUSEG home (cached fetch)
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R+0x14 `getpc` link inside that run (0x0001xxxx)
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R+0x18 T2 ticks around `probe_run` via its KSEG0 alias (cached fetch)
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R+0x1C `getpc` link inside that run (0x8001xxxx)
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R+0x20 T2 ticks around `probe_run` via its KSEG1 alias (uncached, +4/fetch)
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R+0x24 `getpc` link inside that run (0xA001xxxx)
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`seeded` is entered through a register. The test seeds it in the link
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segment and checks that the recompiler accepts the seed. `probe_run` has a straight run of ten instructions after
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its `getpc` call returns, which is enough to show per-instruction uncached
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fetch charging. The results block R (0x00011000) lies outside the loaded
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image, so the stores never touch code pages. Timer 2 is put in mode 0
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(system clock, free-running) first. The T2 deltas include the call overhead,
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which is the same for all three runs. Each delta is (after - before) & 0xFFFF,
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because T2 is a 16-bit counter that wraps. The subtraction waits one `nop`
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after the second `lw`: it would otherwise sit in the load delay slot and read
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the stale register.
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The deltas compare like with like. Each of the three call sequences starts
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on an I-cache line, so the main-loop fetches between the two T2 reads cost
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the same in every run. `probe_run` starts its own line, so no earlier code
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(`seeded`) leaves one of its lines filled. Beetle tags lines with the full
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virtual address, so every run starts with the probe body cold. The KSEG0 and
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KUSEG deltas are then equal, and the KSEG1 delta exceeds them by the uncached
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fetch surcharge alone. The program ends in a `j .` spin, where an oracle run
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can read R.
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The MIPS is hand-encoded, so the output needs no toolchain and is
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reproducible byte for byte. recompiler/tests/test_segment_aware_codegen.py
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imports build() and probes() from this file.
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Usage: python gen_segment_exe.py [out.exe] (also writes out.probes.json)
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"""
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import json
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import os
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import struct
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import sys
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KUSEG, KSEG0, KSEG1 = 0x00000000, 0x80000000, 0xA0000000
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SEGMENTS = {"kuseg": KUSEG, "kseg0": KSEG0, "kseg1": KSEG1}
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LOAD = 0x00010000 # link segment: KUSEG
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RESULTS = 0x00011000 # outside the image; never a code page
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IO_BASE = 0x1F800000 # T2 count at +0x1120, mode at +0x1124
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STACK_TOP = 0x001FFF00 # KUSEG, like the rest of the header
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REG = {"zero": 0, "at": 1, "v0": 2, "v1": 3, "a0": 4, "t0": 8, "t1": 9,
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"t2": 10, "t3": 11, "s0": 16, "s1": 17, "t9": 25, "sp": 29, "ra": 31}
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def _r(x):
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return REG[x] if isinstance(x, str) else x
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def R(funct, rs=0, rt=0, rd=0, sa=0):
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return (_r(rs) << 21) | (_r(rt) << 16) | (_r(rd) << 11) | (sa << 6) | funct
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def I(op, rs=0, rt=0, imm=0):
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return (op << 26) | (_r(rs) << 21) | (_r(rt) << 16) | (imm & 0xFFFF)
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def nop(): return 0
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def addu(rd, rs, rt): return R(0x21, rs, rt, rd)
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def subu(rd, rs, rt): return R(0x23, rs, rt, rd)
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def or_(rd, rs, rt): return R(0x25, rs, rt, rd)
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def jr(rs): return R(0x08, rs)
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def jalr(rs, rd="ra"): return R(0x09, rs, 0, rd)
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def addiu(rt, rs, imm): return I(0x09, rs, rt, imm)
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def andi(rt, rs, imm): return I(0x0C, rs, rt, imm)
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def ori(rt, rs, imm): return I(0x0D, rs, rt, imm)
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def lui(rt, imm): return I(0x0F, 0, rt, imm)
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def lw(rt, off, base): return I(0x23, base, rt, off)
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def sw(rt, off, base): return I(0x2B, base, rt, off)
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class Asm:
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"""Two-pass assembler: fixups resolve labels once layout is known."""
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def __init__(self, base):
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self.base, self.words, self.labels, self.fixups = base, [], {}, []
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def here(self):
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return self.base + 4 * len(self.words)
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def label(self, name):
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self.labels[name] = self.here()
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def emit(self, *words):
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self.words.extend(words)
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def line_up(self, before=0):
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"""Pad with nops until here() + before starts a 16-byte I-cache line."""
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while (self.here() + before) & 0xF:
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self.words.append(nop())
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def jal(self, name):
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self.fixups.append((len(self.words), "jal", name))
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self.words.append(0)
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def j(self, name):
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self.fixups.append((len(self.words), "j", name))
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self.words.append(0)
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def bgezal(self, rs, name):
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self.fixups.append((len(self.words), "bgezal", (rs, name)))
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self.words.append(0)
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def la(self, rt, name, segment):
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"""lui/ori of label `name` in `segment` (the probe's alias)."""
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self.fixups.append((len(self.words), "la_hi", (rt, name, segment)))
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self.fixups.append((len(self.words) + 1, "la_lo", (rt, name, segment)))
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self.words.extend([0, 0])
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def resolve(self):
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for i, kind, arg in self.fixups:
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pc = self.base + 4 * i
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if kind in ("jal", "j"):
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target = self.labels[arg]
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# J-type keeps PC[31:28]: a target in another segment is not
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# encodable, which is the invariant the design relies on.
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assert (target & 0xF0000000) == ((pc + 4) & 0xF0000000)
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op = 0x03 if kind == "jal" else 0x02
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self.words[i] = (op << 26) | ((target >> 2) & 0x03FFFFFF)
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elif kind == "bgezal":
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rs, name = arg
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off = (self.labels[name] - (pc + 4)) >> 2
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self.words[i] = I(0x01, rs, 0x11, off)
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else:
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rt, name, segment = arg
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va = segment | (self.labels[name] & 0x1FFFFFFF)
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self.words[i] = (lui(rt, va >> 16) if kind == "la_hi"
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else ori(rt, rt, va & 0xFFFF))
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return b"".join(struct.pack("<I", w) for w in self.words)
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def _assemble():
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a = Asm(LOAD)
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a.label("main")
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a.emit(lui("s0", RESULTS >> 16), ori("s0", "s0", RESULTS & 0xFFFF))
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a.emit(lui("s1", IO_BASE >> 16))
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a.emit(sw("zero", 0x1124, "s1")) # T2 mode 0: sysclock, free run
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a.jal("leaf"); a.emit(nop(), sw("v0", 0x00, "s0"))
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a.bgezal("zero", "leaf"); a.emit(nop(), sw("v0", 0x04, "s0"))
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a.la("t0", "seeded", KUSEG)
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a.emit(jalr("t0"), nop(), sw("v0", 0x08, "s0"))
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for n, segment in enumerate((KUSEG, KSEG0, KSEG1)):
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a.line_up(8) # each `lw t1` starts a line
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a.la("t0", "probe_run", segment)
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# T2 before and after the call. The nop keeps subu out of the second
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# lw's load delay slot; T2 is 16 bits, so mask the difference.
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a.emit(lw("t1", 0x1120, "s1"), jalr("t0"), nop(),
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lw("t2", 0x1120, "s1"), nop(), subu("t2", "t2", "t1"),
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andi("t2", "t2", 0xFFFF),
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sw("t2", 0x10 + 8 * n, "s0"), sw("v1", 0x14 + 8 * n, "s0"))
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a.label("spin")
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a.j("spin"); a.emit(nop())
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a.label("leaf")
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a.emit(jr("ra"), addu("v0", "ra", "zero"))
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a.label("seeded") # entered through a register
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a.emit(jr("ra"), or_("v0", "ra", "zero"))
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a.line_up() # no line shared with `seeded`
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a.label("probe_run")
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a.emit(addu("t9", "ra", "zero"))
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a.jal("getpc"); a.emit(nop())
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a.label("probe_run_straight") # leader: getpc returns here
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a.emit(*[addiu("t3", "t3", 1) for _ in range(8)])
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a.emit(jr("t9"), addu("v0", "t9", "zero"))
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a.label("probe_run_end")
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a.label("getpc")
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a.emit(jr("ra"), addu("v1", "ra", "zero"))
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a.label("end")
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return a
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def build():
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"""Return the EXE bytes (2048-byte header + image padded to 2 KiB)."""
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a = _assemble()
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body = a.resolve()
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body += b"\0" * (-len(body) % 0x800)
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h = bytearray(2048)
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h[0:8] = b"PS-X EXE"
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struct.pack_into("<I", h, 0x10, a.labels["main"]) # initial pc (KUSEG)
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struct.pack_into("<I", h, 0x18, LOAD) # load address (KUSEG)
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struct.pack_into("<I", h, 0x1C, len(body))
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struct.pack_into("<I", h, 0x30, STACK_TOP) # stack base (KUSEG)
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return bytes(h) + body
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def probes():
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"""Label addresses (link segment) and probe facts the test checks."""
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a = _assemble()
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a.resolve()
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labels = dict(a.labels)
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return {
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"link_segment": KUSEG,
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"load": LOAD,
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"results": RESULTS,
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"labels": labels,
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# Seeds, written the way a project writes them: `seeded` in the link
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# segment, and `probe_run` (whose direct callee `getpc` follows it)
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# in the two alias segments it is entered through.
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"seeds": {
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"home": [labels["seeded"]],
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"variants": [KSEG0 | labels["probe_run"], KSEG1 | labels["probe_run"]],
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},
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# Straight-line fetch run inside probe_run: runtime PCs, link segment.
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"straight": list(range(labels["probe_run_straight"],
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labels["probe_run_end"], 4)),
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}
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def main():
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out = sys.argv[1] if len(sys.argv) > 1 else "segment_testrom.exe"
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with open(out, "wb") as f:
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f.write(build())
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info = probes()
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with open(os.path.splitext(out)[0] + ".probes.json", "w") as f:
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json.dump({k: ({n: "0x%08X" % v for n, v in info[k].items()}
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if k == "labels" else info[k]) for k in info},
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f, indent=2)
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print("wrote %s (%d bytes), probe_run at 0x%08X" %
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(out, len(build()), info["labels"]["probe_run"]))
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if __name__ == "__main__":
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main()
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