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https://github.com/RetroPortingToolKit/psxrecomp
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Shokunin
3e262c128d
The store policy and the CPU side of the out-of-rect VRAM journal move into render_pass_plan.c as pure functions (render_pass_store_to, render_pass_vram_policy, render_pass_journal_add/_rollback); memory.c and gpu_gl_renderer.c only wire them to their arrays and GL copies. Behaviour is unchanged. render_pass_sandbox_test covers what the plan's U5a list asked for: - every device class a pass may not reach (SPU key-on and control, CD, timer, other DMA channels, GP1, SIO, memory control, MDEC, expansion, KSEG2) is dropped under its class and never delivered, while GP0, GP1 DMA mode/info, I_STAT/I_MASK, GPU/OTC DMA and DPCR reach the device; - a real pass (render_pass.c, psx_cycles.c, timers.c) that makes those stores, acknowledges and masks every interrupt, runs 10^6 cycles while timer 2 is armed to interrupt every 1000, and changes a timer behind the store policy's back: drops counted per class, no device advanced, no interrupt raised, RAM, scratchpad, I_STAT/I_MASK, timers and clock restored, and the timer interrupts again once time is live; - fast-forward and backend status refuse the pass without running it; - VRAM writes inside the rect are allowed, outside ones journaled once (covered writes not twice, clipped to VRAM) and rolled back exactly, newest first; a full journal or a mode that cannot journal refuses. Mutations it catches: SPU or CD mis-classed, device service not frozen, rollback order or entry skipped, I_STAT, timer, RAM or scratchpad restore removed. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>