mirror of
https://github.com/RetroPortingToolKit/psxrecomp
synced 2026-10-25 18:05:12 -04:00
Matthew Stanley
07aaa6e700
Debug reads of RAM/scratchpad/BIOS without MMIO, read hooks or unmapped_fatal. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
106 lines
4.8 KiB
C
106 lines
4.8 KiB
C
#ifndef PSXRECOMP_PSX_MEMORY_H
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#define PSXRECOMP_PSX_MEMORY_H
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* One main-RAM geometry contract for every runtime subsystem.
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*
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* Retail DRAM is 2 MiB, mirrored four times across the 8 MiB decode window
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* (physical 0x00000000-0x007FFFFF of every segment). The opt-in 8 MB main RAM
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* enhancement (builtin mod psx.enhancement.8mb-ram) switches the LIVE geometry
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* to unique decoding of the whole window before memory_init(); with the mod
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* off the live geometry is retail and every helper below folds exactly as
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* retail hardware does. The geometry is one mask, latched once per boot: the
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* retail fold is `phys & 0x1FFFFF`, the expanded map `phys & 0x7FFFFF`.
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*
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* Two identities, never mixed:
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* BYTES -- where an address's data lives: psx_ram_map_read /
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* psx_ram_canonical_offset / psx_ram_resolve fold through the live mask.
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* Every RAM access, DMA cursor, dirty/watch page and code-range CRC uses it.
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* CODE -- which compiled body may run at a PC: the segment-stripped address
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* (addr & 0x1FFFFFFF), NEVER mirror-folded. A compiled function bakes its
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* own PCs into $ra/EPC/branch targets, so running the body compiled for
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* 0x80180000 at a 0x80780000 PC would hand the guest a different $ra than
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* hardware does. Architectural state (PC, $ra, EPC) is never folded; a PC
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* in a retail mirror executes the folded bytes with its own address.
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* (One pre-existing exception is kept bit-identical: the BIOS dispatch
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* table's emitted normalize() still folds retail mirrors onto its RAM
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* keys, via `& g_psx_ram_mask`; the 8 MB map does not fold.)
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*
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* Host storage indexed by a RAM offset is sized with PSX_MAIN_RAM_BACKING_BYTES
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* (the largest geometry); bounds that describe the guest-visible RAM use the
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* live size (psx_ram_live_bytes()). Serialized/digested RAM state covers the
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* live size only, so retail savestates and netplay digests are unchanged. */
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#define PSX_MAIN_RAM_RETAIL_BYTES 0x00200000u
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#define PSX_MAIN_RAM_EXPANDED_BYTES 0x00800000u
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#define PSX_MAIN_RAM_WINDOW_BYTES 0x00800000u
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#define PSX_MAIN_RAM_BACKING_BYTES PSX_MAIN_RAM_EXPANDED_BYTES
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/* Live geometry (psx_ram_geometry.c). Retail until a trusted activation plugin
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* requests expanded RAM (psx_mod_set_main_ram_8mb) and memory_init() applies
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* it. g_psx_ram_mask == g_psx_ram_size - 1 always. */
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extern uint32_t g_psx_ram_size;
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extern uint32_t g_psx_ram_mask;
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uint32_t memory_get_ram_bytes(void);
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int psx_ram_8mb_active(void);
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void psx_ram_reset_size_request(void);
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/* memory_init(): latch the requested geometry for this boot. */
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void psx_ram_apply_size_request(void);
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static inline uint32_t psx_ram_live_bytes(void) { return g_psx_ram_size; }
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/* BYTE offset of a physical address. Inside the decode window it folds through
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* the live mask; addresses at/above the window are returned unchanged (not
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* RAM), so callers may pass any physical address. */
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static inline uint32_t psx_ram_map_read(uint32_t phys) {
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phys &= 0x1FFFFFFFu;
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return phys < PSX_MAIN_RAM_WINDOW_BYTES ? (phys & g_psx_ram_mask) : phys;
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}
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static inline uint32_t psx_ram_map_write(uint32_t phys) {
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return psx_ram_map_read(phys);
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}
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/* Strip KUSEG/KSEG0/KSEG1 and fold within the 8 MiB DRAM decode window through
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* the live mask. Bits above the window are ignored (DMAC-style 24-bit keys). */
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static inline uint32_t psx_ram_canonical_offset(uint32_t address) {
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return address & (PSX_MAIN_RAM_WINDOW_BYTES - 1u) & g_psx_ram_mask;
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}
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/* Resolve [address, address+width) to a live RAM offset. Fails for anything
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* outside the decode window, zero width, or a span past the live RAM end
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* (retail: a span crossing a 2 MiB mirror boundary has no contiguous bytes). */
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static inline int psx_ram_resolve(uint32_t address, uint32_t width,
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uint32_t *offset) {
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const uint32_t phys = address & 0x1FFFFFFFu;
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uint32_t off;
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if (phys >= PSX_MAIN_RAM_WINDOW_BYTES || width == 0u) return 0;
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off = phys & g_psx_ram_mask;
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if (width > g_psx_ram_size - off) return 0;
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if (offset) *offset = off;
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return 1;
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}
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/* Stores made by the host rather than the guest CPU (mods, FMV skip, debug
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* pokes, enhancement fills). They take the psx_write_* path but are never
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* cache-isolated: while SR.IsC is set they still reach memory, as DMA does,
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* instead of acting on the caches as a CPU store would (memory.c isc_store). */
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void psx_host_write_word(uint32_t addr, uint32_t val);
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void psx_host_write_half(uint32_t addr, uint16_t val);
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void psx_host_write_byte(uint32_t addr, uint8_t val);
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/* Side-effect-free aligned word peek (RAM / scratchpad / BIOS ROM only), for
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* the debug path. Returns 0 (and leaves *out alone) for anything else. */
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int psx_peek_word(uint32_t addr, uint32_t *out);
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#ifdef __cplusplus
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}
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#endif
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#endif
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