mirror of
https://github.com/RetroPortingToolKit/psxrecomp
synced 2026-10-25 18:05:12 -04:00
Matthew Stanley
7c40d33db3
Phase 1a (boot slice): 30 instructions at 0xBFC00000, compiles clean. Phase 1b (instruction coverage): 54 opcodes implemented in strict_translator, 44,629 walker-reachable instructions covered, 0 missing. Phase 1c (function discovery): 76 functions from 2 seeds, 2,988 instructions, 199 call edges, 27 indirect jumps. All validated through StrictTranslator. Phase 1d (indirect control flow): 27 sites classified — 21 A0/B0/C0 dispatch stubs, 4 computed calls, 2 computed tail calls. Ghidra cross-referenced with 0 disagreements. Phase 1e (relocation): ROM-to-RAM copy at FUN_bfc00420 proven with both Ghidra (static) and DuckStation (runtime). 69 address aliases, 68/69 function entries match byte-for-byte in RAM. Normalization rule documented. Includes PRINCIPLES.md and DEBUG.md adapted from recomp-template. Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
76 lines
2.6 KiB
C
76 lines
2.6 KiB
C
/* AUTO-GENERATED by psxrecomp-bios. DO NOT EDIT.
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*
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* Source: bios/SCPH1001.BIN sha256=71af94d1e47a68c11e8fdb9f8368040601514a42a5a399cda48c7d3bff1e99d3
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* Slice: 0xBFC00000 .. 0xBFC00074 (30 instructions)
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* Termination: j -> 0xBFC00150
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*
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* This file is a Phase 1a proof artifact. It is intended to compile
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* with `gcc -c` against generated/cpu_state.h. It is NOT linkable into
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* a runnable binary by design — see cpu_state.h for the rationale.
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*/
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#include "cpu_state.h"
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void boot_slice(CPUState* cpu) {
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/* 0xBFC00000: 3C080013 lui $t0, 0x13 */
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cpu->gpr[8] = 0x00130000u;
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/* 0xBFC00004: 3508243F ori $t0, $t0, 0x243F */
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cpu->gpr[8] = cpu->gpr[8] | 0x243Fu;
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/* 0xBFC00008: 3C011F80 lui $at, 0x1F80 */
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cpu->gpr[1] = 0x1F800000u;
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/* 0xBFC0000C: AC281010 sw $t0, 4112($at) */
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{ uint32_t psx_addr = (uint32_t)((int32_t)cpu->gpr[1] + (4112)); if (psx_addr & 3u) { psx_unaligned_access(cpu, psx_addr, 0xBFC0000Cu); return; } cpu->write_word(psx_addr, cpu->gpr[8]); }
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/* 0xBFC00010: 00000000 nop */
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/* nop */
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/* 0xBFC00014: 24080B88 addiu $t0, $zero, 2952 */
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cpu->gpr[8] = (uint32_t)((int32_t)cpu->gpr[0] + (2952));
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/* 0xBFC00018: 3C011F80 lui $at, 0x1F80 */
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cpu->gpr[1] = 0x1F800000u;
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/* 0xBFC0001C: AC281060 sw $t0, 4192($at) */
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{ uint32_t psx_addr = (uint32_t)((int32_t)cpu->gpr[1] + (4192)); if (psx_addr & 3u) { psx_unaligned_access(cpu, psx_addr, 0xBFC0001Cu); return; } cpu->write_word(psx_addr, cpu->gpr[8]); }
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/* 0xBFC00020: 00000000 nop */
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/* nop */
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/* 0xBFC00024: 00000000 nop */
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/* nop */
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/* 0xBFC00028: 00000000 nop */
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/* nop */
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/* 0xBFC0002C: 00000000 nop */
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/* nop */
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/* 0xBFC00030: 00000000 nop */
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/* nop */
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/* 0xBFC00034: 00000000 nop */
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/* nop */
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/* 0xBFC00038: 00000000 nop */
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/* nop */
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/* 0xBFC0003C: 00000000 nop */
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/* nop */
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/* 0xBFC00040: 00000000 nop */
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/* nop */
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/* 0xBFC00044: 00000000 nop */
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/* nop */
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/* 0xBFC00048: 00000000 nop */
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/* nop */
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/* 0xBFC0004C: 00000000 nop */
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/* nop */
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/* 0xBFC00050: 00000000 nop */
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/* nop */
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/* 0xBFC00054: 00000000 nop */
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/* nop */
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/* 0xBFC00058: 00000000 nop */
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/* nop */
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/* 0xBFC0005C: 00000000 nop */
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/* nop */
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/* 0xBFC00060: 00000000 nop */
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/* nop */
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/* 0xBFC00064: 00000000 nop */
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/* nop */
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/* 0xBFC00068: 00000000 nop */
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/* nop */
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/* 0xBFC0006C: 00000000 nop */
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/* nop */
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/* 0xBFC00074: 00000000 [delay slot of 0xBFC00070] nop */
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/* nop */
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/* 0xBFC00070: 0BF00054 j 0xBFC00150 */
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cpu->pc = 0xBFC00150u; /* j 0xBFC00150 -- slice terminator (direct) */ return;
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}
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