mirror of
https://github.com/RetroPortingToolKit/psxrecomp
synced 2026-10-27 10:38:46 -04:00
Matt Stanley
13b7f81d29
Keep selector zero stock and seal all choices until the next session restart. Refuse nonzero online activation, scope non-stock save states by frozen choices, and preserve original instruction guards when combined with effective-address adapters. Use overlay ABI34 on current master without the old menu dependency stack.
486 lines
23 KiB
C
486 lines
23 KiB
C
/* Explicit [widescreen.cull] sites in the dirty-RAM interpreter.
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*
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* Native code compiles bltz_sites, bgez_sites, branch_keep_sites and
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* clip_edge_x_load_sites in (ws_cull_edge_codegen_test covers the emit). A
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* listed site that runs from dirty RAM goes through dirty_ram_interp.c
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* instead, which looks the PC up in gpu.c's sorted explicit-site store. This
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* test runs the production code of both files:
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*
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* - the store: masking to physical addresses, sort, de-duplication, lookups
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* at both ends and between entries, the 256-entry cap and its log line,
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* empty and negative-count lists, the clip-edge width default;
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* - psx_ws_cull_bgez / psx_ws_clip_edge_x through a forced margin;
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* - real interpreted instructions (exec_one_fetched) at margin 0 and at a
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* forced margin: BGEZ and BLTZ sites, BNE and BLEZ branch-keep sites, and
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* LH / LHU / LW clip-edge loads, each next to an unlisted twin that must
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* keep the vanilla result.
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*
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* Both sources are #included so the test can call the interpreter's static
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* entry point and read the store's static arrays; unreferenced code is
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* dropped at link time (LTO plus section GC / dead_strip), so only the stubs
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* below are needed. */
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#include "../src/gpu.c"
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#include "../src/mod_immediate.c"
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#include "../src/dirty_ram_interp.c"
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#include <stdio.h>
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#include <string.h>
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#if defined(_WIN32)
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#include <io.h>
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#define dup _dup
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#define dup2 _dup2
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#define fileno _fileno
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#else
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#include <unistd.h>
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#endif
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/* ---- link stubs for code reachable from exec_one_fetched ------------------ */
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uint64_t s_frame_count;
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uint32_t g_debug_current_func_addr;
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uint32_t g_debug_last_store_pc;
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uint32_t g_dirty_ram_code_gen;
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uint64_t g_dispatch_static_hits;
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uint32_t g_psx_mod_instruction_hooks;
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uint32_t psx_mod_memory_address(const CPUState *cpu, uint32_t pc, uint32_t word, uint32_t address) {
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(void)cpu; (void)pc; (void)word; return address;
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}
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void psx_mod_instruction(CPUState *cpu, uint32_t pc, uint32_t instruction) {
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(void)cpu; (void)pc; (void)instruction; abort();
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}
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int g_rfe_escape_pending;
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int g_exc_escape_reason;
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int g_psx_call_bail;
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uint64_t g_psx_bail_first;
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uint64_t g_psx_bail_resolved;
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uint32_t i_stat;
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uint32_t i_mask;
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uint64_t psx_cycle_count;
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/* Live RAM geometry (memory.c): retail 2 MiB, as the stub RAM below. */
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uint32_t g_psx_ram_size = PSX_MAIN_RAM_RETAIL_BYTES;
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uint32_t g_psx_ram_mask = PSX_MAIN_RAM_RETAIL_BYTES - 1u;
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static uint8_t test_ram[0x00200000u];
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uint8_t *memory_get_ram_ptr(void) { return test_ram; }
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uint8_t psx_read_byte(uint32_t a) { return test_ram[a & 0x1FFFFFu]; }
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uint16_t psx_read_half(uint32_t a) {
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uint16_t v; memcpy(&v, test_ram + (a & 0x1FFFFEu), sizeof v); return v;
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}
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uint32_t psx_read_word(uint32_t a) {
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uint32_t v; memcpy(&v, test_ram + (a & 0x1FFFFCu), sizeof v); return v;
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}
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uint8_t psx_cyc_load_byte(CPUState *cpu, uint32_t a, uint32_t rt, uint32_t m) {
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(void)cpu; (void)rt; (void)m; return psx_read_byte(a);
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}
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uint32_t psx_cyc_lwc2_read(CPUState *cpu, uint32_t a) { (void)cpu; return psx_read_word(a); }
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int dirty_ram_is_dirty(uint32_t phys) { (void)phys; return 1; }
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int mdec_recently_active(uint32_t f) { (void)f; return 0; }
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void gte_execute(CPUState *cpu, uint32_t cmd) { (void)cpu; (void)cmd; }
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static int precise_sign_valid, precise_sign;
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static int previous_sign_valid, previous_sign;
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int gte_nclip_native_wide_sign(int32_t mac0, int* sign) {
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(void)mac0; *sign = precise_sign; return precise_sign_valid;
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}
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int gte_nclip_native_wide_previous_sign(int32_t mac0, int* sign) {
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(void)mac0; *sign = previous_sign; return previous_sign_valid;
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}
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void gte_precision_store_word(uint32_t a, uint8_t r) { (void)a; (void)r; }
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uint32_t gte_read_ctrl(CPUState *cpu, uint8_t r) { (void)cpu; (void)r; return 0; }
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uint32_t gte_read_data(CPUState *cpu, uint8_t r) { (void)cpu; (void)r; return 0; }
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void gte_write_ctrl(CPUState *cpu, uint8_t r, uint32_t v) { (void)cpu; (void)r; (void)v; }
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void gte_write_data(CPUState *cpu, uint8_t r, uint32_t v) { (void)cpu; (void)r; (void)v; }
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int overlay_loader_call_native(CPUState *cpu, uint32_t a) { (void)cpu; (void)a; return 0; }
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void psx_bail_record(uint32_t ra, uint32_t sp, uint32_t pc, uint32_t gsp) {
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(void)ra; (void)sp; (void)pc; (void)gsp;
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}
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void psx_break(CPUState *cpu, uint32_t code, uint32_t pc) { (void)cpu; (void)code; (void)pc; }
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void psx_check_interrupts(struct CPUState *cpu) { (void)cpu; }
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void psx_dispatch_call(CPUState *cpu, uint32_t t, uint32_t r) { (void)cpu; (void)t; (void)r; }
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void psx_fatal_halt(const char *reason) { fprintf(stderr, "fatal: %s\n", reason); exit(2); }
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void psx_get_freeze_diag(uint64_t *a, uint32_t *b, int *c, int *d, uint64_t *e,
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uint64_t *f) {
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(void)a; (void)b; (void)c; (void)d; (void)e; (void)f;
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}
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int psx_get_in_exception(void) { return 0; }
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int psx_interrupts_checked_at_current_cycle(uint32_t pc) { (void)pc; return 1; }
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void psx_pgxp_alu(struct CPUState *c, uint32_t i, uint32_t r, uint32_t a, uint32_t b) {
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(void)c; (void)i; (void)r; (void)a; (void)b;
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}
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void psx_pgxp_cop2(struct CPUState *c, uint32_t i, uint32_t v, uint32_t a) {
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(void)c; (void)i; (void)v; (void)a;
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}
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void psx_pgxp_load(struct CPUState *c, uint32_t i, uint32_t a, uint32_t v) {
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(void)c; (void)i; (void)a; (void)v;
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}
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void psx_pgxp_muldiv(struct CPUState *c, uint32_t i, uint32_t h, uint32_t l,
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uint32_t a, uint32_t b) {
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(void)c; (void)i; (void)h; (void)l; (void)a; (void)b;
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}
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void psx_pgxp_store(struct CPUState *c, uint32_t i, uint32_t a, uint32_t v) {
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(void)c; (void)i; (void)a; (void)v;
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}
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void psx_rfe_mark_escape(void) {}
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int psx_syscall(CPUState *cpu, uint32_t code) { (void)cpu; (void)code; return 0; }
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/* ---- harness --------------------------------------------------------------- */
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static int failures;
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#define CHECK(cond, ...) \
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do { \
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if (!(cond)) { \
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fprintf(stderr, "FAIL %s:%d: ", __FILE__, __LINE__); \
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fprintf(stderr, __VA_ARGS__); \
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fputc('\n', stderr); \
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++failures; \
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} \
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} while (0)
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enum { V0 = 2, V1 = 3, A0 = 4 };
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#define CODE 0x80020000u /* phys 0x20000: outside the BIOS load-delay window */
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static uint32_t i_type(uint32_t op, uint32_t rs, uint32_t rt, uint16_t imm) {
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return (op << 26) | (rs << 21) | (rt << 16) | imm;
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}
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/* Executes one instruction at `pc` (its delay slot, a nop, comes from RAM)
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* and returns the next PC. */
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static uint32_t step(CPUState *cpu, uint32_t pc, uint32_t insn) {
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uint32_t next = 0;
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cpu->pc = pc;
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int transfer = exec_one_fetched(cpu, pc, insn, &next);
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return transfer ? cpu->pc : next;
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}
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/* Branch at `pc` with offset +3 words: taken -> pc+16, fall-through -> pc+8. */
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static int branch_taken(CPUState *cpu, uint32_t pc, uint32_t insn) {
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uint32_t next = step(cpu, pc, insn);
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CHECK(next == pc + 16 || next == pc + 8,
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"branch 0x%08X at 0x%08X went to 0x%08X", insn, pc, next);
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return next == pc + 16;
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}
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static uint32_t load(CPUState *cpu, uint32_t pc, uint32_t insn) {
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cpu->gpr[V0] = 0xDEADBEEFu;
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(void)step(cpu, pc, insn);
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dirty_ram_ld_delay_flush(cpu); /* no pending write outside the BIOS window */
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return cpu->gpr[V0];
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}
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static void put_half(uint32_t addr, uint16_t v) { memcpy(test_ram + (addr & 0x1FFFFFu), &v, 2); }
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static void put_word(uint32_t addr, uint32_t v) { memcpy(test_ram + (addr & 0x1FFFFFu), &v, 4); }
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/* stderr is captured through a named file (argv[1]; ctest passes one in its
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* binary directory) rather than tmpfile(): on MSYS2 MinGW64 (msvcrt)
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* tmpfile() creates its file in the root of the current drive, which fails
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* for a normal account. */
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static const char *s_capture_path = "ws_cull_edge_interp_stderr.txt";
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/* Runs `fn` with stderr captured into `buf`. */
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static void capture_stderr(void (*fn)(void), char *buf, size_t cap) {
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FILE *tmp = fopen(s_capture_path, "w+b");
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buf[0] = '\0';
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if (!tmp) {
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CHECK(0, "cannot open the stderr capture file %s", s_capture_path);
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fn();
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return;
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}
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fflush(stderr);
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int saved = dup(fileno(stderr));
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dup2(fileno(tmp), fileno(stderr));
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fn();
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fflush(stderr);
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dup2(saved, fileno(stderr));
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close(saved);
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rewind(tmp);
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size_t n = fread(buf, 1, cap - 1, tmp);
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buf[n] = '\0';
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fclose(tmp);
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remove(s_capture_path);
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}
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/* ---- store ----------------------------------------------------------------- */
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static uint32_t big_list[300];
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static void set_bltz_300(void) {
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gpu_ws_set_branch_cull_sites(big_list, 300, NULL, 0, NULL, 0);
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}
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static void set_bltz_256(void) {
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gpu_ws_set_branch_cull_sites(big_list, 256, NULL, 0, NULL, 0);
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}
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static void test_store(void) {
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/* Unsorted, duplicated, mixed KUSEG/KSEG0/KSEG1 spellings. */
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const uint32_t bgez[] = { 0x80013F50u, 0x00013F40u, 0xA0013F48u,
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0x80013F40u, 0x8001FFFCu, 0x80013F50u };
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gpu_ws_set_branch_cull_sites(NULL, 0, bgez, 6, NULL, 0);
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CHECK(ws_explicit_bgez_n == 4, "de-duplicated count %d, want 4",
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ws_explicit_bgez_n);
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for (int i = 1; i < ws_explicit_bgez_n; i++)
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CHECK(ws_explicit_bgez_sites[i - 1] < ws_explicit_bgez_sites[i],
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"store not strictly ascending at %d", i);
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CHECK(ws_explicit_bgez_sites[0] == 0x00013F40u, "stored as physical");
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for (int i = 0; i < 6; i++)
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CHECK(psx_ws_is_cull_bgez_site(bgez[i]), "listed 0x%08X missed", bgez[i]);
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CHECK(psx_ws_is_cull_bgez_site(0xA001FFFCu), "last entry via KSEG1");
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CHECK(psx_ws_is_cull_bgez_site(0x00013F48u), "middle entry via KUSEG");
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CHECK(!psx_ws_is_cull_bgez_site(0x80013F3Cu), "below the first entry hit");
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CHECK(!psx_ws_is_cull_bgez_site(0x80013F44u), "between entries hit");
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CHECK(!psx_ws_is_cull_bgez_site(0x80013F4Cu), "between entries hit");
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CHECK(!psx_ws_is_cull_bgez_site(0x80020000u), "above the last entry hit");
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CHECK(!psx_ws_is_cull_bgez_site(0x00000000u), "address 0 hit");
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CHECK(!psx_ws_is_cull_bltz_site(0x80013F40u), "kinds leak into each other");
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CHECK(!psx_ws_is_cull_branch_keep_site(0x80013F40u), "kinds leak into each other");
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/* One entry, empty, negative count, NULL pointer. */
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const uint32_t one = 0x80010040u;
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gpu_ws_set_branch_cull_sites(NULL, 0, NULL, 0, &one, 1);
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CHECK(psx_ws_is_cull_branch_keep_site(one), "single entry missed");
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CHECK(!psx_ws_is_cull_branch_keep_site(one + 4), "single entry neighbour hit");
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CHECK(ws_explicit_bgez_n == 0, "re-set did not clear bgez");
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gpu_ws_set_branch_cull_sites(&one, -3, &one, 0, NULL, 5);
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CHECK(ws_explicit_bltz_n == 0 && ws_explicit_branch_keep_n == 0,
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"negative count or NULL list stored entries");
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CHECK(!psx_ws_is_cull_bltz_site(one), "empty list hit");
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/* The pre-existing setters share the store. */
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const uint32_t slti[] = { 0x80030010u, 0x80030000u };
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gpu_ws_set_explicit_cull_sites(NULL, 0, slti, 2, NULL, 0);
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CHECK(psx_ws_is_cull_slti_site(0x80030000u) &&
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psx_ws_is_cull_slti_site(0x80030010u) &&
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!psx_ws_is_cull_slti_site(0x80030008u), "slti_sites store");
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gpu_ws_set_explicit_cull_sites(NULL, 0, NULL, 0, NULL, 0);
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/* Cap: exactly 256 is silent and complete. */
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for (int i = 0; i < 300; i++)
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big_list[i] = 0x80040000u + 4u * (uint32_t)(299 - i); /* descending */
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char log[512];
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capture_stderr(set_bltz_256, log, sizeof log);
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CHECK(ws_explicit_bltz_n == 256, "256 sites stored %d", ws_explicit_bltz_n);
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CHECK(strstr(log, "exceed") == NULL, "a list at the cap was logged: %s", log);
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int hits = 0;
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for (int i = 0; i < 256; i++) hits += psx_ws_is_cull_bltz_site(big_list[i]);
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CHECK(hits == 256, "only %d of 256 sites found at the cap", hits);
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/* 300: logged, the first 256 in list order kept, the rest vanilla. */
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capture_stderr(set_bltz_300, log, sizeof log);
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CHECK(ws_explicit_bltz_n == 256, "over-long list stored %d", ws_explicit_bltz_n);
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CHECK(strstr(log, "[widescreen] bltz_sites: 300 sites exceed the "
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"interpreter cap of 256") != NULL,
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"overflow not logged (got \"%s\")", log);
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hits = 0;
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for (int i = 0; i < 256; i++) hits += psx_ws_is_cull_bltz_site(big_list[i]);
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CHECK(hits == 256, "only %d of the first 256 sites found", hits);
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hits = 0;
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for (int i = 256; i < 300; i++) hits += psx_ws_is_cull_bltz_site(big_list[i]);
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CHECK(hits == 0, "%d sites past the cap were kept", hits);
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gpu_ws_set_branch_cull_sites(NULL, 0, NULL, 0, NULL, 0);
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/* Clip-edge width: 0 means the 320 default. */
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gpu_ws_set_clip_edge_x_load_sites(&one, 1, 0);
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CHECK(psx_ws_clip_edge_width() == 320u, "default width %u",
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psx_ws_clip_edge_width());
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gpu_ws_set_clip_edge_x_load_sites(&one, 1, 368);
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CHECK(psx_ws_clip_edge_width() == 368u, "explicit width");
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CHECK(psx_ws_is_cull_clip_edge_x_load_site(one), "clip-edge entry missed");
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gpu_ws_set_clip_edge_x_load_sites(NULL, 0, 0);
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}
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/* ---- helpers through a forced margin -------------------------------------- */
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static void test_helpers(void) {
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gpu_ws_set_margin_override(0);
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CHECK(psx_ws_cull_bgez((uint32_t)-1) == 0 && psx_ws_cull_bgez(0) == 1,
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"bgez not vanilla at margin 0");
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CHECK(psx_ws_cull_bltz((uint32_t)-1) == 1, "bltz not vanilla at margin 0");
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CHECK(psx_ws_clip_edge_x(0, 320) == 0 && psx_ws_clip_edge_x(320, 320) == 320,
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"clip edge not identity at margin 0");
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gpu_ws_set_margin_override(53);
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CHECK(psx_ws_x_margin() == 53, "margin override");
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CHECK(psx_ws_cull_bgez((uint32_t)-53) == 1 && psx_ws_cull_bgez((uint32_t)-54) == 0,
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"bgez edge at margin 53");
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CHECK(psx_ws_cull_bltz((uint32_t)-53) == 0 && psx_ws_cull_bltz((uint32_t)-54) == 1,
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"bltz edge at margin 53");
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CHECK(psx_ws_clip_edge_x(0, 320) == (uint32_t)-53, "left bound -> -m");
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CHECK(psx_ws_clip_edge_x(320, 320) == 373u, "right bound -> W+m");
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CHECK(psx_ws_clip_edge_x(98, 320) == 98u && psx_ws_clip_edge_x(222, 320) == 222u,
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"interior (mirror) bounds must not move");
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CHECK(psx_ws_clip_edge_x(368, 368) == 421u && psx_ws_clip_edge_x(320, 368) == 320u,
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"width parameter");
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gpu_ws_set_margin_override(0);
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}
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/* ---- interpreted instructions ---------------------------------------------- */
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static void test_interpreter(void) {
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CPUState cpu;
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memset(&cpu, 0, sizeof cpu);
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memset(test_ram, 0, sizeof test_ram); /* every delay slot is a nop */
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const uint32_t bgez_site = CODE + 0x000, bgez_plain = CODE + 0x100;
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const uint32_t bltz_site = CODE + 0x010, bltz_plain = CODE + 0x110;
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const uint32_t bne_site = CODE + 0x020, bne_plain = CODE + 0x120;
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const uint32_t blez_site = CODE + 0x030, blez_plain = CODE + 0x130;
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const uint32_t lh_site = CODE + 0x040, lh_plain = CODE + 0x140;
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const uint32_t lhu_site = CODE + 0x050, lw_site = CODE + 0x060;
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const uint32_t bgez = i_type(0x01, V0, 0x01, 3); /* bgez v0,+3 */
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const uint32_t bltz = i_type(0x01, V0, 0x00, 3); /* bltz v0,+3 */
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const uint32_t bne = i_type(0x05, A0, 0, 3); /* bne a0,zero,+3 */
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const uint32_t blez = i_type(0x06, A0, 0, 3); /* blez a0,+3 */
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const uint32_t lh = i_type(0x21, A0, V0, 0x70); /* lh v0,0x70(a0) */
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const uint32_t lhu = i_type(0x25, A0, V0, 0x70); /* lhu v0,0x70(a0) */
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const uint32_t lw = i_type(0x23, A0, V0, 0x70); /* lw v0,0x70(a0) */
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const uint32_t bltz_l[] = { bltz_site }, bgez_l[] = { bgez_site };
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const uint32_t keep_l[] = { bne_site, blez_site };
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const uint32_t clip_l[] = { lh_site, lhu_site, lw_site };
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gpu_ws_set_branch_cull_sites(bltz_l, 1, bgez_l, 1, keep_l, 2);
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gpu_ws_set_clip_edge_x_load_sites(clip_l, 3, 320);
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for (int pass = 0; pass < 2; pass++) {
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const int m = pass ? 53 : 0;
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gpu_ws_set_margin_override(m);
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/* bgez: x0 = -10 sits in the revealed band when m = 53. */
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cpu.gpr[V0] = (uint32_t)-10;
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CHECK(branch_taken(&cpu, bgez_site, bgez) == (m > 0),
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"bgez site, x=-10, m=%d", m);
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CHECK(!branch_taken(&cpu, bgez_plain, bgez), "unlisted bgez, m=%d", m);
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cpu.gpr[V0] = (uint32_t)-60;
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CHECK(!branch_taken(&cpu, bgez_site, bgez), "bgez site, x=-60, m=%d", m);
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cpu.gpr[V0] = 5;
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CHECK(branch_taken(&cpu, bgez_site, bgez), "bgez site, x=5, m=%d", m);
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/* bltz: rejects only past -m. */
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cpu.gpr[V0] = (uint32_t)-10;
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CHECK(branch_taken(&cpu, bltz_site, bltz) == (m == 0),
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"bltz site, x=-10, m=%d", m);
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CHECK(branch_taken(&cpu, bltz_plain, bltz), "unlisted bltz, m=%d", m);
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cpu.gpr[V0] = (uint32_t)-60;
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CHECK(branch_taken(&cpu, bltz_site, bltz), "bltz site, x=-60, m=%d", m);
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/* branch_keep: the reject is forced not-taken only while wide. */
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cpu.gpr[A0] = 7;
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CHECK(branch_taken(&cpu, bne_site, bne) == (m == 0),
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"bne keep site, m=%d", m);
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CHECK(branch_taken(&cpu, bne_plain, bne), "unlisted bne, m=%d", m);
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cpu.gpr[A0] = 0;
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CHECK(!branch_taken(&cpu, bne_site, bne), "bne keep site not taken, m=%d", m);
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CHECK(branch_taken(&cpu, blez_site, blez) == (m == 0),
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"blez keep site, m=%d", m);
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CHECK(branch_taken(&cpu, blez_plain, blez), "unlisted blez, m=%d", m);
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/* clip_edge_x_load: edges move out, interior bounds stay. */
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const uint32_t bound = 0x80100000u;
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cpu.gpr[A0] = bound - 0x70u;
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put_half(bound, 0);
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CHECK(load(&cpu, lh_site, lh) == (m ? (uint32_t)-m : 0u), "lh 0, m=%d", m);
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CHECK(load(&cpu, lh_plain, lh) == 0u, "unlisted lh 0, m=%d", m);
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put_half(bound, 320);
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CHECK(load(&cpu, lh_site, lh) == 320u + (uint32_t)m, "lh 320, m=%d", m);
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CHECK(load(&cpu, lhu_site, lhu) == 320u + (uint32_t)m, "lhu 320, m=%d", m);
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CHECK(load(&cpu, lh_plain, lh) == 320u, "unlisted lh 320, m=%d", m);
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put_half(bound, 98);
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CHECK(load(&cpu, lh_site, lh) == 98u, "lh mirror bound 98, m=%d", m);
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put_half(bound, 222);
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CHECK(load(&cpu, lhu_site, lhu) == 222u, "lhu mirror bound 222, m=%d", m);
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put_half(bound, 0xFFFF); /* -1 sign-extends for lh, 65535 for lhu */
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CHECK(load(&cpu, lh_site, lh) == 0xFFFFFFFFu, "lh -1, m=%d", m);
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CHECK(load(&cpu, lhu_site, lhu) == 0xFFFFu, "lhu 65535, m=%d", m);
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put_word(bound, 0);
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CHECK(load(&cpu, lw_site, lw) == (m ? (uint32_t)-m : 0u), "lw 0, m=%d", m);
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put_word(bound, 320);
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CHECK(load(&cpu, lw_site, lw) == 320u + (uint32_t)m, "lw 320, m=%d", m);
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}
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/* A configured width replaces 320 as the right edge. */
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gpu_ws_set_clip_edge_x_load_sites(clip_l, 3, 368);
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gpu_ws_set_margin_override(53);
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const uint32_t bound = 0x80100000u;
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cpu.gpr[A0] = bound - 0x70u;
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put_half(bound, 368);
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CHECK(load(&cpu, lh_site, lh) == 421u, "lh 368 with width 368");
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put_half(bound, 320);
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CHECK(load(&cpu, lh_site, lh) == 320u, "lh 320 is interior with width 368");
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gpu_ws_set_margin_override(-1);
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gpu_ws_set_branch_cull_sites(NULL, 0, NULL, 0, NULL, 0);
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gpu_ws_set_clip_edge_x_load_sites(NULL, 0, 0);
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}
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static void test_masked_reject(void) {
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CPUState cpu = {0};
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memset(test_ram, 0, sizeof test_ram);
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const uint32_t site = CODE + 0x200;
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const uint32_t word = i_type(5, A0, 0, 3);
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const uint32_t mask = 0xFFFF0000u;
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gpu_ws_set_masked_reject_sites(&site, &word, &mask, 1);
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for (int margin = 0; margin <= 53; margin += 53) {
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gpu_ws_set_margin_override(margin);
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cpu.gpr[A0] = 0xFE00u;
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CHECK(branch_taken(&cpu, site, word) == (margin == 0), "packed X reject at margin %d", margin);
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CHECK(cpu.gpr[A0] == 0xFE00u, "packed cull preserves guest flags");
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CHECK(branch_taken(&cpu, site + 0x40, word), "unlisted packed branch stays vanilla");
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cpu.gpr[V0] = 0;
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CHECK(branch_taken(&cpu, site, i_type(5, A0, V0, 3)), "mismatched word stays vanilla");
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cpu.gpr[A0] = 0xFF00FE00u;
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CHECK(branch_taken(&cpu, site, word), "packed Y reject retained at margin %d", margin);
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cpu.gpr[A0] = 0;
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CHECK(!branch_taken(&cpu, site, word), "zero flags stay visible");
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}
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gpu_ws_set_masked_reject_sites(NULL, NULL, NULL, 0);
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gpu_ws_set_margin_override(-1);
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}
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static void test_wide_nclip_branches(void) {
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CPUState cpu = {0};
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ws_xnum = 3; ws_xden = 4; ws_mode = 0;
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ws_precise_nclip_cfg = 1;
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precise_sign_valid = 1; precise_sign = 1;
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const uint32_t sites[] = {CODE+0x300,CODE+0x340,CODE+0x380};
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const uint32_t words[] = {i_type(6,A0,0,3),i_type(7,A0,0,3),i_type(1,A0,1,3)};
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psx_mod_set_native_wide_nclip_sites(sites,words,3);
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for (int margin=0;margin<=53;margin+=53) {
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gpu_ws_set_margin_override(margin);
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cpu.gpr[A0]=0;
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CHECK(branch_taken(&cpu,sites[0],words[0]) == (margin==0), "BLEZ native zero vs precise positive");
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CHECK(branch_taken(&cpu,sites[1],words[1]) == (margin!=0), "BGTZ native zero vs precise positive");
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CHECK(cpu.gpr[A0]==0, "winding helper leaves guest MAC0 register alone");
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cpu.gpr[A0]=(uint32_t)-1;
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CHECK(branch_taken(&cpu,sites[2],words[2]) == (margin!=0), "BGEZ exact keep predicate");
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CHECK(branch_taken(&cpu,sites[0]+4,words[0]), "unlisted twin stays native");
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cpu.gpr[V0]=(uint32_t)-1;
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CHECK(branch_taken(&cpu,sites[0],i_type(6,V0,0,3)), "wrong full word stays native");
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}
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precise_sign_valid=0; gpu_ws_set_margin_override(53); cpu.gpr[A0]=0;
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CHECK(branch_taken(&cpu,sites[0],words[0]), "missing precision stays native");
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precise_sign_valid=1; precise_sign=-1;
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previous_sign_valid=1; previous_sign=1;
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psx_mod_set_native_wide_nclip_previous_site(sites[1],words[1]);
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CHECK(branch_taken(&cpu,sites[1],words[1]), "first quad branch selects preceding positive winding");
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CHECK(!branch_taken(&cpu,sites[2],words[2]), "second quad branch selects latest negative winding");
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previous_sign_valid=0;
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CHECK(!branch_taken(&cpu,sites[1],words[1]), "missing preceding winding cannot use latest result");
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previous_sign_valid=1; gpu_ws_set_margin_override(0);
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CHECK(!branch_taken(&cpu,sites[1],words[1]), "preceding winding is disabled in native 4:3");
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gpu_ws_set_margin_override(53);
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psx_mod_set_native_wide_nclip_sites(sites,words,3);
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CHECK(!branch_taken(&cpu,sites[1],words[1]), "registration resets preceding-result bindings");
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psx_mod_set_native_wide_nclip_sites(NULL,NULL,0);
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ws_precise_nclip_cfg=0; ws_xnum=ws_xden=1;
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gpu_ws_set_margin_override(-1);
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}
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int main(int argc, char **argv) {
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if (argc > 1) s_capture_path = argv[1];
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test_store();
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test_helpers();
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test_interpreter();
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test_masked_reject();
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test_wide_nclip_branches();
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if (failures) {
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fprintf(stderr, "%d check(s) failed\n", failures);
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return 1;
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}
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puts("PASS explicit cull-site store (sort, de-dup, cap, log) and interpreted "
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"bgez/bltz/branch-keep/clip-edge sites at margin 0 and 53");
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return 0;
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}
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