mirror of
https://github.com/RetroPortingToolKit/psxrecomp
synced 2026-10-26 10:19:47 -04:00
Matthew Stanley
7c40d33db3
Phase 1a (boot slice): 30 instructions at 0xBFC00000, compiles clean. Phase 1b (instruction coverage): 54 opcodes implemented in strict_translator, 44,629 walker-reachable instructions covered, 0 missing. Phase 1c (function discovery): 76 functions from 2 seeds, 2,988 instructions, 199 call edges, 27 indirect jumps. All validated through StrictTranslator. Phase 1d (indirect control flow): 27 sites classified — 21 A0/B0/C0 dispatch stubs, 4 computed calls, 2 computed tail calls. Ghidra cross-referenced with 0 disagreements. Phase 1e (relocation): ROM-to-RAM copy at FUN_bfc00420 proven with both Ghidra (static) and DuckStation (runtime). 69 address aliases, 68/69 function entries match byte-for-byte in RAM. Normalization rule documented. Includes PRINCIPLES.md and DEBUG.md adapted from recomp-template. Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
99 lines
3.7 KiB
C++
99 lines
3.7 KiB
C++
#pragma once
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#include <cstdint>
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#include <vector>
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#include <string>
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#include "ps1_exe_parser.h"
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namespace PSXRecomp {
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// MIPS R3000 instruction format types
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enum class InstrFormat {
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R, // Register: op[31:26]=0 rs rt rd shamt funct
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I, // Immediate: op rs rt imm16
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J, // Jump: op target26
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SPECIAL, // SPECIAL opcode (funct field determines op) - alias for R
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REGIMM, // REGIMM opcode (rt field determines op)
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COP0, // Coprocessor 0
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COP2, // GTE coprocessor
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UNKNOWN // Unrecognized/invalid
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};
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// Fully decoded MIPS R3000 instruction
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struct DecodedInstruction {
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uint32_t raw; // Original instruction word
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uint32_t address; // PC address where this was fetched
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InstrFormat format;
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// Register fields (R-type and I-type)
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uint8_t rs; // Source register [25:21]
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uint8_t rt; // Target register [20:16]
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uint8_t rd; // Destination register [15:11]
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uint8_t shamt; // Shift amount [10:6]
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uint8_t funct; // Function code [5:0]
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// Immediate fields (I-type)
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int16_t imm16; // Sign-extended immediate [15:0]
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uint16_t uimm16; // Zero-extended immediate [15:0]
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// Jump field (J-type)
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uint32_t target26; // 26-bit jump target [25:0]
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// Derived fields
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uint8_t opcode; // Top 6 bits [31:26]
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uint32_t jump_target; // Full computed jump address (for J/JAL/JR/JALR)
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uint32_t branch_target; // Full computed branch target (for beq/bne/etc)
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int32_t sign_ext_imm; // Sign-extended 16-bit immediate as int32
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// Classification flags
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bool is_branch; // BEQ/BNE/BLEZ/BGTZ/BLTZ/BGEZ/BLTZAL/BGEZAL
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bool is_jump; // J/JAL/JR/JALR
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bool is_load; // LB/LH/LW/LBU/LHU/LWL/LWR/LWC2
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bool is_store; // SB/SH/SW/SWL/SWR/SWC2
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bool is_alu; // Arithmetic/logic (not load/store/branch/jump)
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bool is_nop; // raw == 0 (SLL $zero,$zero,0)
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bool is_syscall; // SYSCALL instruction
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bool is_break; // BREAK instruction
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bool is_jr_ra; // JR $ra specifically (function return)
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bool is_delay_slot_user; // This instruction is followed by a delay slot
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// Mnemonic for debugging/display
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const char* mnemonic; // e.g. "ADDIU", "LW", "JAL"
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};
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class MipsDecoder {
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public:
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// Decode a single instruction word at a given address
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// address is used to compute branch/jump targets
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static DecodedInstruction decode(uint32_t instr, uint32_t address = 0);
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// Decode all instructions in a PS1 executable sequentially
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static std::vector<DecodedInstruction> decode_executable(
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const PS1Executable& exe
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);
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// Compute branch target: address + 4 + (imm16 << 2)
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static uint32_t compute_branch_target(uint32_t address, int16_t imm16);
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// Compute jump target: (address & 0xF0000000) | (target26 << 2)
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static uint32_t compute_jump_target(uint32_t address, uint32_t target26);
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// Check if instruction is a NOP (0x00000000 = SLL $zero,$zero,0)
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static bool is_nop(uint32_t instr);
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// Get MIPS register name string ("$zero", "$at", "$v0", etc.)
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static const char* register_name(uint8_t reg);
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// Get mnemonic string for a decoded instruction
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static const char* get_mnemonic(const DecodedInstruction& instr);
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private:
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static void decode_special(DecodedInstruction& out);
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static void decode_regimm(DecodedInstruction& out);
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static void decode_cop0(DecodedInstruction& out);
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static void decode_cop2(DecodedInstruction& out);
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static void set_classification_flags(DecodedInstruction& out);
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};
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} // namespace PSXRecomp
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