mirror of
https://github.com/RetroPortingToolKit/psxrecomp
synced 2026-10-26 10:19:47 -04:00
Matthew Stanley
127 lines
3.4 KiB
C
127 lines
3.4 KiB
C
/* dma.h — PS1 DMA controller simulation (Phase 3).
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*
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* 7 DMA channels:
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* Ch0: MDEC in 0x1F801080
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* Ch1: MDEC out 0x1F801090
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* Ch2: GPU 0x1F8010A0
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* Ch3: CDROM 0x1F8010B0
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* Ch4: SPU 0x1F8010C0
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* Ch5: PIO 0x1F8010D0
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* Ch6: OTC 0x1F8010E0
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*
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* Global:
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* DPCR: 0x1F8010F0 (DMA control — enable bits per channel)
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* DICR: 0x1F8010F4 (DMA interrupt control)
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*/
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#ifndef PSXRECOMP_DMA_H
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#define PSXRECOMP_DMA_H
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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void dma_init(void);
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uint32_t dma_read(uint32_t addr);
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void dma_write(uint32_t addr, uint32_t val);
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void dma_write_masked(uint32_t addr, uint32_t val, uint32_t mask);
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void dma_advance(uint32_t cycles);
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/* Cycle-budgeted precise event slicing: guest CPU cycles until a DELIVERABLE
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* DMA IRQ (bit3 unmasked in i_mask). UINT32_MAX if none. */
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uint32_t dma_cycles_to_irq(uint32_t i_mask);
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/* Mask-blind scheduler boundary: next DMA word movement or delayed completion,
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* not merely the final IRQ. RAM-producing DMA must become visible at its
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* per-word due cycle even when guest code polls ordinary RAM instead of DICR. */
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uint32_t dma_cycles_to_internal_event(void);
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/* Strict deliverability form for wait-loop elision: unlike the conservative
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* scheduler bound, ignores channel completions whose DICR IRQ is disabled. */
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uint32_t dma_cycles_to_deliverable_irq(uint32_t i_mask);
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uint32_t dma_get_dicr(void);
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uint32_t dma_get_dpcr(void);
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int dma_cdrom_transfer_active(void);
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typedef struct DMAChannelDebugState {
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uint32_t madr;
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uint32_t bcr;
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uint32_t chcr;
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uint32_t active;
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uint32_t remaining_words;
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uint32_t cycles_accum;
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} DMAChannelDebugState;
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typedef struct DMADebugState {
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uint32_t dpcr;
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uint32_t dicr;
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DMAChannelDebugState channels[7];
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} DMADebugState;
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typedef struct DMATraceEntry {
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uint64_t seq;
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uint32_t frame;
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uint32_t kind;
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uint32_t channel;
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uint32_t total_words;
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uint32_t addr;
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uint32_t val;
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uint32_t mask;
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uint32_t madr;
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uint32_t bcr;
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uint32_t chcr;
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uint32_t dpcr;
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uint32_t dicr_before;
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uint32_t dicr_after;
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uint32_t i_stat_before;
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uint32_t i_stat_after;
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uint32_t func;
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uint32_t pc;
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} DMATraceEntry;
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#define DMA_TRACE_CAP (1 << 14)
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#define DMA_CDROM_HISTORY_CAP (1 << 13)
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#define DMA_CDROM_HISTORY_WORDS 16
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typedef struct DMACDROMHistoryEntry {
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uint64_t seq;
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uint32_t frame_start;
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uint32_t frame_end;
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uint32_t start_addr;
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uint32_t final_addr;
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uint32_t requested_words;
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uint32_t moved_words;
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uint32_t bcr;
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uint32_t chcr;
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uint32_t dpcr;
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uint32_t dicr_start;
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uint32_t dicr_end;
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uint32_t i_stat_start;
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uint32_t i_stat_end;
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uint32_t func;
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uint32_t pc;
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int lba;
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int sector_size;
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int sector_read_pos_start;
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int sector_read_pos_end;
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uint8_t mode;
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uint8_t sector_available_start;
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uint8_t sector_available_end;
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uint8_t completed;
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uint8_t first_count;
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uint8_t last_count;
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uint32_t first_words[DMA_CDROM_HISTORY_WORDS];
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uint32_t last_words[DMA_CDROM_HISTORY_WORDS];
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} DMACDROMHistoryEntry;
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uint64_t dma_debug_get_trace(const DMATraceEntry** out_entries);
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void dma_debug_clear_trace(void);
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void dma_debug_get_state(DMADebugState* out);
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uint64_t dma_debug_get_cdrom_history(const DMACDROMHistoryEntry** out_entries);
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void dma_debug_clear_cdrom_history(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* PSXRECOMP_DMA_H */
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