mirror of
https://github.com/RetroPortingToolKit/psxrecomp
synced 2026-10-26 10:19:47 -04:00
80ff96780a
The overlay capture format DELIBERATELY appends one coherent guard instruction
past the end of a dirty-page run (overlay_capture.c write_json_window, `size
+= 4u`, pinned by runtime/tests/test_interpreter_perf_guards.py:47): a MIPS
branch sitting at the run's final word (...FFC) always executes its delay slot
in the next page (...000), and the shard must be able to emit and hash that
word. So a capture whose size is a page multiple PLUS 4 is a CORRECT capture --
N bytes of overlay plus one guard word. Measured: 36 of 36 Ape Escape
(SCUS-94423) vault records and 846 of 946 Tomba 2 (SCUS-94454) records are that
shape.
The recompiler was never taught the asymmetry: the guard word is a legal
DELAY-SLOT SOURCE but an ILLEGAL BLOCK LEADER, because the word after it does
not exist in the image. It had exactly one bound -- end_address() -- used both
to read words and to decide what is code.
MEASURED on Ape Escape, its own single-source vault at framework
v0.3.2-alpha-139-g1bf70960, 36 variants:
PSX_SHARD_RESULT ok=50 failed=17 skipped=32 capacity_fastpath=0
! [recompiler] overlay 0x80136000 crc 4BAB23C9: what(): cannot emit control
flow at 0x80138000: mandatory delay slot 0x80138004 is outside the input
image
+ 16 x [fragment] interior 0x801360.. @region 0x00136000, identical message
One root cause, seventeen shards. The whole region then falls back to the
dirty-RAM interpreter forever, and nothing at runtime says so.
Causal chain, every step read in source:
1. overlay_capture.c:349-361 appends the guard word; region 0x80136000 gets
size 0x2004, so the image is [0x80136000, 0x80138004).
2. compile_overlays.py make_psxexe wraps those bytes verbatim with text size
= len(data), so PS1Executable::end_address() = 0x80138004.
3. function_analysis.cpp in_exe / in_function admit 0x80138000 as ordinary
code, and the walk reaches it by fall-through from 0x80137FFC
(0x24022000, addiu -- not control flow), so func.end_addr becomes the
image end.
4. control_flow.cpp makes the final block end_addr = func.end_addr - 4 =
0x80138000: the block LEADER is the guard word.
5. control_flow.cpp's "Also check last instruction itself" promotion finds
0x80137FFC is not control flow and therefore promotes read_word(end_addr)
-- the guard word 0x1062005A, a beq -- to block.exit_instr, with
has_delay_slot = true and address == end_addr. THIS IS THE DEFECT.
6. code_generator.cpp computes delay_slot_addr = 0x80138004, read_word
returns nullopt, and it throws.
THE THROW AT STEP 6 IS CORRECT AND IS PRESERVED. Emitting a control transfer
without its architectural delay slot silently corrupts guest state, which is
what the code did before that throw was added. The gap is step 5.
Fix: give the image view two distinct bounds.
end_address() READ bound -- every byte the image supplies, so a
mandatory delay slot living at a guard word resolves.
analysis_end_address() ANALYSIS bound -- one past the last byte that may be
discovered, made a block leader, or made a block's
exit instruction.
read_word() keeps the READ bound. Discovery and block construction move to the
ANALYSIS bound: function_analysis.cpp in_exe / in_exe_p3 / add_forced_entry /
every hard_cap that used to be the image end / the jr-table producer_hi
defaults / the static jr-ra and JAL sweeps; control_flow.cpp gains
analysis_walk_hi(func) and uses it for cfg.function_end, alias entries,
add_boundary, the scan loop, the final block's end_addr and in_func;
code_generator.cpp's mid-function split pre-pass; main_psx.cpp seed admission
and the data-scan pointer promotion; analysis_db.cpp, main_toml.cpp,
main_cli.cpp target/seed admission. The clamp is applied only when it leaves a
non-empty walk, so a degenerate function starting at or past the bound keeps
failing closed rather than silently producing an empty CFG.
HOW THE BOUND IS DERIVED -- the producer STATES it; the recompiler is told.
The alternative was for the recompiler to infer the count from `size % 4096 ==
4`. That fits every capture the current writer has ever produced, but it is a
consumer guessing at a producer's intent, and this tree already has the
counter-example: 52 of the 946 SCUS-94454 records have residues from 112 to
3996 bytes (one not even 4-byte aligned) because they come from the STATIC
extractor, which records an exact file extent and appends no guard word. A rule
keyed to the page-run shape is a rule that shifts the moment a producer
changes.
So the count travels with the image, in a magic-tagged field in the otherwise
zero-filled tail of the 2048-byte PS-EXE header (exe_tag in ps1_exe_parser.h:
"PSXRGRD1" at 0x7E0, uint32 count at 0x7E8). Putting it in the header rather
than on the command line means every consumer gets it automatically and no
future invocation path can forget to pass it -- compile_overlays has three
make_psxexe sites and five recompiler spawn sites. An absent or malformed tag
means ZERO guard bytes, which is exactly what every genuine PS-X EXE is: the
BIOS and every retail main executable have no guard word, their analysis bound
equals their read bound, and their analysis is bit-for-bit unchanged.
Producer side:
overlay_capture.c writes "guard_bytes": 4|0 per region -- the writer
stating its own intent, additive to the v2 schema and
preserved through coverage_vault.py compaction.
compile_overlays.py capture_guard_bytes(): prefer that field; for captures
recorded before it existed, reconstruct the single
shape write_json_window can produce (page multiple + 4)
and return 0 for everything else, which is the
fail-closed answer -- an unrecognised guard word is
analysed as code and the step-6 throw still fires
loudly at generation time.
make_psxexe guard_bytes is keyword-only with NO default, so a new
call site is a TypeError, not a silently mis-analysed
shard. The count is threaded through
compile_fragment_batch / compile_interior_fragment /
generate_interior_fragment_static and into the fragment
fail-memo key (bumped to v3, so a memo recorded under
the old analysis cannot suppress a retry under the
corrected one).
SECOND-ORDER DEFECT FIXED IN THE SAME PASS. generate_ranges_manifest extends a
range by +4 for any block whose exit instruction IS its last word, so the
cloned delay slot joins the candidate CRC and the page-generation watch. That
extension was unclamped. Reachable TODAY, independent of the guard word: a
branch-likely opcode (0x14-0x17, RESERVED on the R3000A) as the image's very
last word is short-circuited by translate_basic_block into an inline RI raise
BEFORE any delay slot is read, so generation succeeds and the manifest claims 4
bytes past the image end. Measured on origin/master with a 28-byte synthetic
image: `R 80010000 20` for an image ending at 0x8001001C. The cache would then
validate the shard against bytes the shard never saw. Now clamped to the READ
bound -- not the analysis bound, because a guard word genuinely IS compiled in
when it serves as a delay slot and must participate in the CRC.
DEAD CODE, documented rather than trusted: basic_block.cpp's BasicBlockAnalyzer
bounds its walk correctly but nothing in the tree constructs it. It is still
compiled and still hashed into the codegen tag, so a change there invalidates
caches without moving an emitted byte. Its bounds move to the analysis bound
too -- wiring it up must not reintroduce this defect -- and a header comment now
says where the live walker actually is.
TESTS. Both registered, so ctest runs them and the configure-time
registration guard is satisfied.
recompiler/tests/test_overlay_guard_word_analysis_bound.py drives
psxrecomp-game over five synthetic images:
A tagged, 2 pages + guard word, last real word not control flow, guard word
IS a beq -- the measured Ape shape. Must generate; the guard word must not
be emitted as an instruction; the block must publish 0x80012000 for the
runtime to dispatch; no range may claim it.
B byte-for-byte the same payload with NO tag. Must still fail closed with
the mandatory-delay-slot diagnostic naming 0x80012000. A and B differ only
in the header tag, which proves the tag is what changed behaviour and that
the throw was not weakened.
B2 a misaligned declaration (6). Must be rejected and behave like B.
C tagged, with a real branch at the last analysable word. The guard word
must be emitted AS the delay slot and must be covered by the manifest.
D branch-likely as the final word. Generation must succeed and no range may
exceed the image end.
Against origin/master's psxrecomp-game the same file reports exactly the two
things this commit changes, and passes B, B2 and C:
FAIL: tagged guard word still fails generation: what(): cannot emit control
flow at 0x80012000: mandatory delay slot 0x80012004 is outside the
input image
FAIL: range [0x80010000,0x80010020) claims 4 byte(s) past the image end
0x8001001C
tools/tests/test_overlay_guard_bytes_declaration.py pins the producer half:
field precedence, the reconstruction table, rejection of nonsense
declarations, the tag's byte offsets, that make_psxexe with guard_bytes=0 is
byte-identical to the pre-fix wrapper, and that overlay_capture.c both appends
the guard word and now declares it.
MEASURED OUTCOME, Ape Escape, same vault, same flags, fresh cache:
before PSX_SHARD_RESULT ok=50 failed=17 skipped=32 capacity_fastpath=0
after PSX_SHARD_RESULT ok=31 failed=0 skipped=57 capacity_fastpath=0
ok falls because 19 isolated island fragment shards at 0x00136000 are no longer
needed once the region variant compiles as one shard. Coverage is what matters,
and it is measured from the DLL exports: 349 -> 361 unique func_XXXXXXXX
entries, ZERO lost, 12 gained -- 0x80136140, 0x8013614C, 0x80136154,
0x80136238, 0x801362D4, 0x801362DC, 0x801362F0, 0x80136324, 0x80136370,
0x80136400, 0x80136480, 0x80137950, all from the failure list. The other four
failing PCs were already served by a sibling variant's shard.
INERTNESS.
BIOS (SCPH1001, psxrecomp-bios --config bios/SCPH1001.toml): all four
generated artifacts BYTE-IDENTICAL, verified by sha256 rather than by exit
code, because tools/regen_bios.sh exits 0 on failure.
Tomba 2 main EXE (psxrecomp-game --config game.toml): all nine generated
artifacts BYTE-IDENTICAL, and the console log is identical too.
Tomba 2 overlays, 82 variants over 6 regions from its own vault: identical
result line (ok=98 failed=0 skipped=103) and identical shard identity set,
4901 unique func exports on both sides -- zero gained, zero lost. 97 of 98
range manifests are byte-identical. The one that differs is region
0x8010A000 variant A32DB188, size 0x2004, whose last function's range goes
from 0x218 to 0x214 bytes: its guard word (0x24840008, addiu) had been
emitted as an ordinary instruction and hashed, and now is not. That is
precisely the intended change and nothing else moved.
Bead beads-eio.3.100.
Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
365 lines
15 KiB
C++
365 lines
15 KiB
C++
// ---------------------------------------------------------------------------
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// BasicBlockAnalyzer is NOT on any live path.
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//
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// Nothing in the tree constructs it: the live basic-block walker is
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// ControlFlowAnalyzer::analyze_function (control_flow.cpp), built at
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// main_psx.cpp:932/954/1138 and rebuilt in
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// CodeGenerator::generate_file's mid-function split pre-pass. This file is
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// still compiled and therefore still hashed into the codegen tag, so a change
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// here invalidates caches without changing any emitted byte.
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//
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// It is kept, and kept CORRECT, rather than deleted: it already bounded its
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// walk properly, and its bounds are now the analysis bound
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// (PS1Executable::analysis_end_address) so wiring it up could never
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// reintroduce the guard-word-as-block-leader defect (bead beads-eio.3.100).
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// Do not "fix" a discovery bug by editing this file — measure which walker
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// runs first.
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// ---------------------------------------------------------------------------
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#include "basic_block.h"
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#include <algorithm>
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namespace PSXRecomp {
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BasicBlockAnalyzer::BasicBlockAnalyzer(const PS1Executable& exe)
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: exe_(exe)
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{
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}
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// ---------------------------------------------------------------------------
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// find_leaders: collect all basic block entry point addresses
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// ---------------------------------------------------------------------------
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std::vector<uint32_t> BasicBlockAnalyzer::find_leaders() {
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std::vector<uint32_t> leaders;
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// Leader 1: entry point of the executable
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leaders.push_back(exe_.entry_point());
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for (size_t i = 0; i < decoded_.size(); ++i) {
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const auto& instr = decoded_[i];
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if (instr.is_branch || instr.is_jump) {
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// The instruction after the delay slot is a leader (fall-through target).
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// Delay slot is at i+1, so i+2 is the next block's start.
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uint32_t fall_through = instr.address + 8; // skip instr + delay slot
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if (fall_through < exe_.analysis_end_address()) {
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leaders.push_back(fall_through);
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}
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// The branch/jump target is also a leader.
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if (instr.is_branch && instr.branch_target != 0 &&
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instr.branch_target >= exe_.load_address() &&
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instr.branch_target < exe_.analysis_end_address()) {
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leaders.push_back(instr.branch_target);
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}
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if (instr.is_jump && instr.jump_target != 0 &&
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instr.jump_target >= exe_.load_address() &&
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instr.jump_target < exe_.analysis_end_address()) {
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leaders.push_back(instr.jump_target);
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}
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}
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}
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// Sort and deduplicate
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std::sort(leaders.begin(), leaders.end());
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leaders.erase(std::unique(leaders.begin(), leaders.end()), leaders.end());
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return leaders;
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}
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// ---------------------------------------------------------------------------
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// build_block: construct a BasicBlock starting at start_addr
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// ---------------------------------------------------------------------------
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BasicBlock BasicBlockAnalyzer::build_block(uint32_t start_addr) {
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BasicBlock block{};
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block.start_addr = start_addr;
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block.end_addr = start_addr;
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block.instr_count = 0;
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block.has_delay_slot = false;
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block.delay_slot_addr = 0;
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auto it = addr_to_idx_.find(start_addr);
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if (it == addr_to_idx_.end()) {
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return block; // Address not in executable range
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}
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size_t idx = it->second;
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bool in_delay_slot = false;
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for (size_t i = idx; i < decoded_.size(); ++i) {
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const auto& instr = decoded_[i];
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block.end_addr = instr.address;
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block.instr_count++;
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if (in_delay_slot) {
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// This instruction is the delay slot — block ends after it
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block.delay_slot_addr = instr.address;
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break;
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}
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if (instr.is_delay_slot_user) {
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// Next instruction is the delay slot
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block.has_delay_slot = true;
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in_delay_slot = true;
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continue;
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}
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// Non-delay-slot end conditions:
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// 1. jr $ra without delay slot consideration (already handled above)
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// 2. Current instruction is followed by a leader in another block
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// Check if the NEXT instruction is a known leader (i.e., new block starts there)
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if (i + 1 < decoded_.size()) {
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uint32_t next_addr = decoded_[i + 1].address;
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// If next_addr is a leader (different block), end here
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if (addr_to_block_.count(next_addr) || next_addr == start_addr) {
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// We'll check this via leader set in analyze()
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// For now: end block if next address is in our block list
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// (This pass is before block map is built, so we check leaders differently)
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}
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}
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// If no successor info yet, fall through to next instruction
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}
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// Compute successors based on terminator instruction
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if (block.instr_count > 0) {
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const auto* term_it = addr_to_idx_.count(block.end_addr)
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? &decoded_[addr_to_idx_.at(block.end_addr)]
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: nullptr;
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// Walk back to the branch/jump instruction (before delay slot)
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const DecodedInstruction* branch_instr = nullptr;
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if (block.has_delay_slot && block.instr_count >= 2) {
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uint32_t branch_addr = block.end_addr - 4; // instruction before delay slot
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auto bit = addr_to_idx_.find(branch_addr);
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if (bit != addr_to_idx_.end()) {
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branch_instr = &decoded_[bit->second];
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}
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} else if (term_it && (term_it->is_branch || term_it->is_jump)) {
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branch_instr = term_it;
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}
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if (branch_instr) {
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uint32_t fall_through = block.end_addr + 4; // after delay slot
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if (branch_instr->is_branch) {
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// Conditional: fall-through + taken target
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if (fall_through < exe_.analysis_end_address())
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block.successors.push_back(fall_through);
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if (branch_instr->branch_target >= exe_.load_address() &&
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branch_instr->branch_target < exe_.analysis_end_address())
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block.successors.push_back(branch_instr->branch_target);
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} else if (branch_instr->is_jump) {
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if (branch_instr->is_jr_ra) {
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// Function return — no successor within this function
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} else if (branch_instr->opcode == 0x03) {
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// JAL — control returns here; fall-through is successor
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if (fall_through < exe_.analysis_end_address())
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block.successors.push_back(fall_through);
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} else if (branch_instr->jump_target >= exe_.load_address() &&
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branch_instr->jump_target < exe_.analysis_end_address()) {
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block.successors.push_back(branch_instr->jump_target);
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}
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}
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} else if (term_it) {
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// Straight-line end: fall through to next instruction
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uint32_t fall_through = block.end_addr + 4;
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if (fall_through < exe_.analysis_end_address())
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block.successors.push_back(fall_through);
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}
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}
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return block;
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}
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// ---------------------------------------------------------------------------
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// analyze: main entry point
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// ---------------------------------------------------------------------------
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std::vector<BasicBlock> BasicBlockAnalyzer::analyze() {
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blocks_.clear();
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addr_to_block_.clear();
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decoded_.clear();
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addr_to_idx_.clear();
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// Step 1: Decode all instructions
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decoded_ = MipsDecoder::decode_executable(exe_);
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addr_to_idx_.reserve(decoded_.size());
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for (size_t i = 0; i < decoded_.size(); ++i) {
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addr_to_idx_[decoded_[i].address] = i;
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}
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// Step 2: Find all leader addresses
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auto leaders = find_leaders();
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// Step 3: Build blocks — for each leader, scan forward until the next leader
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// We need to know where blocks end, so use leaders as boundaries.
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// Reserve to avoid reallocation while pointers into decoded_ are live.
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blocks_.reserve(leaders.size());
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for (size_t li = 0; li < leaders.size(); ++li) {
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uint32_t start = leaders[li];
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uint32_t next_leader = (li + 1 < leaders.size())
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? leaders[li + 1]
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: exe_.analysis_end_address();
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// Only create a block if start_addr is in the decoded range
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if (addr_to_idx_.count(start) == 0) continue;
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BasicBlock block{};
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block.start_addr = start;
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block.end_addr = start;
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block.instr_count = 0;
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block.has_delay_slot = false;
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block.delay_slot_addr = 0;
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size_t idx = addr_to_idx_.at(start);
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bool in_delay_slot = false;
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bool block_ended = false;
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for (size_t i = idx; i < decoded_.size() && !block_ended; ++i) {
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const auto& instr = decoded_[i];
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// Stop if we've reached the next leader (and we're not in a delay slot)
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if (!in_delay_slot && instr.address >= next_leader && instr.address != start) {
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break;
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}
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block.end_addr = instr.address;
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block.instr_count++;
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if (in_delay_slot) {
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block.delay_slot_addr = instr.address;
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block_ended = true;
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break;
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}
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if (instr.is_delay_slot_user) {
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block.has_delay_slot = true;
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in_delay_slot = true;
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// Continue loop to pick up the delay slot instruction
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continue;
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}
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// Check if next instruction is a leader → block ends here
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if (i + 1 < decoded_.size()) {
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uint32_t next_addr = decoded_[i + 1].address;
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if (next_addr >= next_leader) {
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block_ended = true;
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}
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} else {
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block_ended = true; // end of executable
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}
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}
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// Compute successors
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// Find the branch/jump instruction (before delay slot if present)
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const DecodedInstruction* branch_instr = nullptr;
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if (block.has_delay_slot && block.instr_count >= 2) {
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uint32_t branch_addr = block.delay_slot_addr - 4;
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auto bit = addr_to_idx_.find(branch_addr);
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if (bit != addr_to_idx_.end()) {
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branch_instr = &decoded_[bit->second];
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}
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} else {
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auto eit = addr_to_idx_.find(block.end_addr);
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if (eit != addr_to_idx_.end()) {
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const auto& end_instr = decoded_[eit->second];
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if (end_instr.is_branch || end_instr.is_jump) {
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branch_instr = &end_instr;
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}
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}
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}
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if (branch_instr) {
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// Instruction after the delay slot (or after the branch if no delay slot)
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uint32_t after_branch = block.has_delay_slot
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? block.delay_slot_addr + 4
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: block.end_addr + 4;
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if (branch_instr->is_branch) {
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// Conditional: two successors
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if (after_branch < exe_.analysis_end_address())
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block.successors.push_back(after_branch);
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if (branch_instr->branch_target >= exe_.load_address() &&
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branch_instr->branch_target < exe_.analysis_end_address())
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block.successors.push_back(branch_instr->branch_target);
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} else { // jump
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if (branch_instr->is_jr_ra) {
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// Return: no intra-function successors
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} else if (branch_instr->opcode == 0x03) { // JAL
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// JAL: fall-through after delay slot
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if (after_branch < exe_.analysis_end_address())
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block.successors.push_back(after_branch);
|
|
} else if (branch_instr->jump_target >= exe_.load_address() &&
|
|
branch_instr->jump_target < exe_.analysis_end_address()) {
|
|
block.successors.push_back(branch_instr->jump_target);
|
|
} else if (branch_instr->opcode == 0x08 || branch_instr->opcode == 0x09) {
|
|
// JR/JALR to register — dynamic target, can't statically determine
|
|
}
|
|
}
|
|
} else {
|
|
// Straight-line: fall through
|
|
uint32_t fall_through = block.end_addr + 4;
|
|
if (fall_through < exe_.analysis_end_address() && fall_through < next_leader) {
|
|
// Only add if it's in range (typically the next block)
|
|
}
|
|
if (fall_through < exe_.analysis_end_address())
|
|
block.successors.push_back(fall_through);
|
|
}
|
|
|
|
// Deduplicate successors
|
|
std::sort(block.successors.begin(), block.successors.end());
|
|
block.successors.erase(
|
|
std::unique(block.successors.begin(), block.successors.end()),
|
|
block.successors.end());
|
|
|
|
size_t block_idx = blocks_.size();
|
|
addr_to_block_[block.start_addr] = block_idx;
|
|
blocks_.push_back(std::move(block));
|
|
}
|
|
|
|
// Step 4: Build predecessor lists
|
|
build_predecessors(blocks_);
|
|
|
|
return blocks_;
|
|
}
|
|
|
|
// ---------------------------------------------------------------------------
|
|
// build_predecessors: reverse the successor edges
|
|
// ---------------------------------------------------------------------------
|
|
void BasicBlockAnalyzer::build_predecessors(std::vector<BasicBlock>& blocks) {
|
|
// Build addr → block index map
|
|
std::unordered_map<uint32_t, size_t> addr_map;
|
|
for (size_t i = 0; i < blocks.size(); ++i) {
|
|
addr_map[blocks[i].start_addr] = i;
|
|
}
|
|
|
|
// For each block, add this block's start as a predecessor of each successor
|
|
for (size_t i = 0; i < blocks.size(); ++i) {
|
|
for (uint32_t succ_addr : blocks[i].successors) {
|
|
auto it = addr_map.find(succ_addr);
|
|
if (it != addr_map.end()) {
|
|
blocks[it->second].predecessors.push_back(blocks[i].start_addr);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
// ---------------------------------------------------------------------------
|
|
// find_block: look up a block containing addr
|
|
// ---------------------------------------------------------------------------
|
|
const BasicBlock* BasicBlockAnalyzer::find_block(uint32_t addr) const {
|
|
// First check if addr is an exact start address
|
|
auto it = addr_to_block_.find(addr);
|
|
if (it != addr_to_block_.end()) {
|
|
return &blocks_[it->second];
|
|
}
|
|
|
|
// Linear scan for containment (slow but correct for occasional lookups)
|
|
for (const auto& block : blocks_) {
|
|
if (block.contains(addr)) {
|
|
return █
|
|
}
|
|
}
|
|
return nullptr;
|
|
}
|
|
|
|
} // namespace PSXRecomp
|