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8b819eb7e0
MMX6 16:9 attract wedged (misaligned wild dispatch 0x21010001 -> fatal halt, stack-sampled at psx_unknown_dispatch under dirty_ram_dispatch). Mechanism: the enlarged site caches persist across overlay reloads, and the generation counter only sees page-marking hooks (kernel writes + DMA executable-range marks) - code replaced by plain CPU stores (loader memcpy) keeps the page dirty and never bumps the generation, so a cached backdrop verdict derived from the PREVIOUS overlay bytes could fire a GPR rewrite at the wrong instruction. The old 256-slot cache had the same hole but evicted within seconds; the 8192-slot cache widened the exposure to a real wedge. Each entry now also stores the site instruction word and revalidates it on lookup (one fetch_word) - any code change at the site forces re-derivation. Cost on the hot path: one load + compare per candidate instruction. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>