mirror of
https://github.com/RetroPortingToolKit/psxrecomp
synced 2026-10-26 18:25:35 -04:00
Matthew Stanley
8e81afd111
Recompiler bug fix: full_function_emitter treated conditional branch delay slots at function boundaries as fully resolved control flow, suppressing the fall-through tail call for the "not taken" path. This broke 15 cross-function fall-throughs across the BIOS, most critically the find-free-EvCB-slot function (BFC11800) whose search loop was silently skipped — causing OpenEvent to return garbage handles (0xF100E1E8) instead of valid slot indices (0xF1000000..0xF1000005). Fix: only suppress fall-through for unconditional flow (j/jr/jal/jalr/rfe). Conditional branches (beq/bne/blez/bgtz/bltz/bgez) now always emit `cpu->pc = next_addr; return;` for the not-taken path. Also included: - Tier 1 reverse debugger: 1M-entry write trace ring (32 MB), 64K-entry MMIO trace ring (2 MB), 8-slot multi-range address filtering, function attribution via g_debug_current_func_addr. 6 new TCP commands: wtrace_add/del/ranges/stats, mmio_dump/clear. - 3 new dispatch seeds for functions exposed by fall-through fix (SIO epilogue, exception chain walker, GTE init). - Diagnostic tools: analyze_sio_trace, decode_insn, decode_jt, mmio_tally. - Pattern 5 trampoline fix + PLAN.md Phase 4 status update. Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
336 lines
13 KiB
C++
336 lines
13 KiB
C++
#include "mips_decoder.h"
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namespace PSXRecomp {
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// Register names (MIPS O32 ABI)
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static const char* kRegisterNames[32] = {
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"$zero", "$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3",
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"$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7",
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"$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7",
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"$t8", "$t9", "$k0", "$k1", "$gp", "$sp", "$fp", "$ra"
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};
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const char* MipsDecoder::register_name(uint8_t reg) {
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if (reg >= 32) return "$??";
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return kRegisterNames[reg];
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}
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bool MipsDecoder::is_nop(uint32_t instr) {
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return instr == 0;
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}
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uint32_t MipsDecoder::compute_branch_target(uint32_t address, int16_t imm16) {
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// Branch target = PC + 4 + (sign_extended_offset << 2)
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return address + 4u + (uint32_t)((int32_t)imm16 << 2);
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}
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uint32_t MipsDecoder::compute_jump_target(uint32_t address, uint32_t target26) {
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// Jump target = ((PC+4) & 0xF0000000) | (target26 << 2)
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return ((address + 4u) & 0xF0000000u) | (target26 << 2u);
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}
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const char* MipsDecoder::get_mnemonic(const DecodedInstruction& instr) {
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return instr.mnemonic ? instr.mnemonic : "???";
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}
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// ---------------------------------------------------------------------------
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// SPECIAL opcode (opcode == 0): funct field [5:0] determines operation
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// ---------------------------------------------------------------------------
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void MipsDecoder::decode_special(DecodedInstruction& out) {
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out.format = InstrFormat::SPECIAL;
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switch (out.funct) {
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case 0x00: out.mnemonic = "SLL"; break;
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case 0x02: out.mnemonic = "SRL"; break;
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case 0x03: out.mnemonic = "SRA"; break;
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case 0x04: out.mnemonic = "SLLV"; break;
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case 0x06: out.mnemonic = "SRLV"; break;
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case 0x07: out.mnemonic = "SRAV"; break;
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case 0x08: out.mnemonic = "JR"; break;
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case 0x09: out.mnemonic = "JALR"; break;
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case 0x0C: out.mnemonic = "SYSCALL"; break;
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case 0x0D: out.mnemonic = "BREAK"; break;
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case 0x10: out.mnemonic = "MFHI"; break;
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case 0x11: out.mnemonic = "MTHI"; break;
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case 0x12: out.mnemonic = "MFLO"; break;
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case 0x13: out.mnemonic = "MTLO"; break;
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case 0x18: out.mnemonic = "MULT"; break;
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case 0x19: out.mnemonic = "MULTU"; break;
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case 0x1A: out.mnemonic = "DIV"; break;
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case 0x1B: out.mnemonic = "DIVU"; break;
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case 0x20: out.mnemonic = "ADD"; break;
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case 0x21: out.mnemonic = "ADDU"; break;
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case 0x22: out.mnemonic = "SUB"; break;
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case 0x23: out.mnemonic = "SUBU"; break;
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case 0x24: out.mnemonic = "AND"; break;
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case 0x25: out.mnemonic = "OR"; break;
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case 0x26: out.mnemonic = "XOR"; break;
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case 0x27: out.mnemonic = "NOR"; break;
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case 0x2A: out.mnemonic = "SLT"; break;
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case 0x2B: out.mnemonic = "SLTU"; break;
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default:
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out.mnemonic = "SPECIAL?";
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out.format = InstrFormat::UNKNOWN;
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break;
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}
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}
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// ---------------------------------------------------------------------------
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// REGIMM opcode (opcode == 1): rt field [20:16] determines operation
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// ---------------------------------------------------------------------------
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void MipsDecoder::decode_regimm(DecodedInstruction& out) {
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out.format = InstrFormat::REGIMM;
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switch (out.rt) {
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case 0x00: out.mnemonic = "BLTZ"; break;
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case 0x01: out.mnemonic = "BGEZ"; break;
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case 0x10: out.mnemonic = "BLTZAL"; break;
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case 0x11: out.mnemonic = "BGEZAL"; break;
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default:
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out.mnemonic = "REGIMM?";
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out.format = InstrFormat::UNKNOWN;
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break;
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}
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}
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// ---------------------------------------------------------------------------
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// COP0 (opcode == 0x10): rs field [25:21] determines sub-operation
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// ---------------------------------------------------------------------------
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void MipsDecoder::decode_cop0(DecodedInstruction& out) {
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out.format = InstrFormat::COP0;
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// rs field holds the COP sub-opcode
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switch (out.rs) {
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case 0x00: out.mnemonic = "MFC0"; break;
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case 0x04: out.mnemonic = "MTC0"; break;
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case 0x10:
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// CO bit set — could be RFE (funct==0x10) or TLBR/TLBWI/etc.
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if (out.funct == 0x10) out.mnemonic = "RFE";
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else out.mnemonic = "COP0CO";
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break;
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default: out.mnemonic = "COP0"; break;
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}
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}
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// ---------------------------------------------------------------------------
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// COP2 / GTE (opcode == 0x12): rs field determines sub-operation
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// ---------------------------------------------------------------------------
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void MipsDecoder::decode_cop2(DecodedInstruction& out) {
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out.format = InstrFormat::COP2;
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switch (out.rs) {
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case 0x00: out.mnemonic = "MFC2"; break;
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case 0x02: out.mnemonic = "CFC2"; break;
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case 0x04: out.mnemonic = "MTC2"; break;
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case 0x06: out.mnemonic = "CTC2"; break;
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default:
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// CO bit (bit 25) set => GTE command word
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if (out.rs & 0x10) out.mnemonic = "GTE";
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else out.mnemonic = "COP2";
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break;
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}
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}
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// ---------------------------------------------------------------------------
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// Classification flags (called after mnemonic/format are set)
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// ---------------------------------------------------------------------------
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void MipsDecoder::set_classification_flags(DecodedInstruction& out) {
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out.is_branch = false;
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out.is_jump = false;
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out.is_load = false;
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out.is_store = false;
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out.is_alu = false;
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out.is_nop = (out.raw == 0);
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out.is_syscall = false;
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out.is_break = false;
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out.is_jr_ra = false;
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out.is_delay_slot_user = false;
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if (out.format == InstrFormat::UNKNOWN) return;
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if (out.is_nop) return;
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// SPECIAL (opcode == 0)
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if (out.opcode == 0x00) {
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switch (out.funct) {
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case 0x08: // JR
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out.is_jump = true;
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out.is_delay_slot_user = true;
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if (out.rs == 31) out.is_jr_ra = true;
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break;
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case 0x09: // JALR
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out.is_jump = true;
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out.is_delay_slot_user = true;
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break;
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case 0x0C: out.is_syscall = true; break;
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case 0x0D: out.is_break = true; break;
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default: out.is_alu = true; break;
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}
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return;
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}
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// REGIMM (opcode == 1) — all are conditional branches
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if (out.opcode == 0x01) {
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out.is_branch = true;
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out.is_delay_slot_user = true;
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return;
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}
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switch (out.opcode) {
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// Unconditional jumps
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case 0x02: // J
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case 0x03: // JAL
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out.is_jump = true;
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out.is_delay_slot_user = true;
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break;
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// Conditional branches
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case 0x04: // BEQ
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case 0x05: // BNE
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case 0x06: // BLEZ
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case 0x07: // BGTZ
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out.is_branch = true;
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out.is_delay_slot_user = true;
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break;
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// ALU (immediate variants)
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case 0x08: // ADDI
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case 0x09: // ADDIU
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case 0x0A: // SLTI
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case 0x0B: // SLTIU
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case 0x0C: // ANDI
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case 0x0D: // ORI
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case 0x0E: // XORI
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case 0x0F: // LUI
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out.is_alu = true;
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break;
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// Loads
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case 0x20: // LB
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case 0x21: // LH
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case 0x22: // LWL
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case 0x23: // LW
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case 0x24: // LBU
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case 0x25: // LHU
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case 0x26: // LWR
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case 0x32: // LWC2
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out.is_load = true;
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break;
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// Stores
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case 0x28: // SB
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case 0x29: // SH
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case 0x2A: // SWL
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case 0x2B: // SW
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case 0x2E: // SWR
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case 0x3A: // SWC2
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out.is_store = true;
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break;
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// COP0, COP2: neither load/store/alu/branch/jump
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default:
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break;
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}
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}
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// ---------------------------------------------------------------------------
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// Main decode function
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// ---------------------------------------------------------------------------
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DecodedInstruction MipsDecoder::decode(uint32_t instr, uint32_t address) {
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DecodedInstruction out{};
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out.raw = instr;
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out.address = address;
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out.mnemonic = "???";
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out.format = InstrFormat::UNKNOWN;
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// Extract all bit fields
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out.opcode = (instr >> 26) & 0x3F;
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out.rs = (instr >> 21) & 0x1F;
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out.rt = (instr >> 16) & 0x1F;
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out.rd = (instr >> 11) & 0x1F;
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out.shamt = (instr >> 6) & 0x1F;
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out.funct = (instr ) & 0x3F;
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out.uimm16 = (uint16_t)(instr & 0xFFFF);
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out.imm16 = (int16_t)(instr & 0xFFFF);
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out.target26 = instr & 0x03FFFFFF;
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out.sign_ext_imm = (int32_t)out.imm16;
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// Dispatch to format-specific decoder
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switch (out.opcode) {
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case 0x00: decode_special(out); break;
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case 0x01: decode_regimm(out); break;
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case 0x02: out.mnemonic = "J"; out.format = InstrFormat::J; break;
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case 0x03: out.mnemonic = "JAL"; out.format = InstrFormat::J; break;
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case 0x04: out.mnemonic = "BEQ"; out.format = InstrFormat::I; break;
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case 0x05: out.mnemonic = "BNE"; out.format = InstrFormat::I; break;
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case 0x06: out.mnemonic = "BLEZ"; out.format = InstrFormat::I; break;
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case 0x07: out.mnemonic = "BGTZ"; out.format = InstrFormat::I; break;
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case 0x08: out.mnemonic = "ADDI"; out.format = InstrFormat::I; break;
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case 0x09: out.mnemonic = "ADDIU"; out.format = InstrFormat::I; break;
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case 0x0A: out.mnemonic = "SLTI"; out.format = InstrFormat::I; break;
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case 0x0B: out.mnemonic = "SLTIU"; out.format = InstrFormat::I; break;
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case 0x0C: out.mnemonic = "ANDI"; out.format = InstrFormat::I; break;
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case 0x0D: out.mnemonic = "ORI"; out.format = InstrFormat::I; break;
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case 0x0E: out.mnemonic = "XORI"; out.format = InstrFormat::I; break;
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case 0x0F: out.mnemonic = "LUI"; out.format = InstrFormat::I; break;
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case 0x10: decode_cop0(out); break;
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case 0x12: decode_cop2(out); break;
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case 0x20: out.mnemonic = "LB"; out.format = InstrFormat::I; break;
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case 0x21: out.mnemonic = "LH"; out.format = InstrFormat::I; break;
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case 0x22: out.mnemonic = "LWL"; out.format = InstrFormat::I; break;
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case 0x23: out.mnemonic = "LW"; out.format = InstrFormat::I; break;
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case 0x24: out.mnemonic = "LBU"; out.format = InstrFormat::I; break;
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case 0x25: out.mnemonic = "LHU"; out.format = InstrFormat::I; break;
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case 0x26: out.mnemonic = "LWR"; out.format = InstrFormat::I; break;
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case 0x28: out.mnemonic = "SB"; out.format = InstrFormat::I; break;
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case 0x29: out.mnemonic = "SH"; out.format = InstrFormat::I; break;
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case 0x2A: out.mnemonic = "SWL"; out.format = InstrFormat::I; break;
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case 0x2B: out.mnemonic = "SW"; out.format = InstrFormat::I; break;
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case 0x2E: out.mnemonic = "SWR"; out.format = InstrFormat::I; break;
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case 0x32: out.mnemonic = "LWC2"; out.format = InstrFormat::I; break;
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case 0x3A: out.mnemonic = "SWC2"; out.format = InstrFormat::I; break;
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default:
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out.mnemonic = "???";
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out.format = InstrFormat::UNKNOWN;
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break;
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}
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// Compute branch/jump targets
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if (out.opcode == 0x02 || out.opcode == 0x03) {
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// J / JAL
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out.jump_target = compute_jump_target(address, out.target26);
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}
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if (out.opcode == 0x04 || out.opcode == 0x05 ||
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out.opcode == 0x06 || out.opcode == 0x07 ||
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out.opcode == 0x01) {
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// BEQ/BNE/BLEZ/BGTZ + REGIMM (BLTZ/BGEZ/etc.)
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out.branch_target = compute_branch_target(address, out.imm16);
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}
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// Set classification flags
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set_classification_flags(out);
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// Override mnemonic for NOP (0x00000000 = SLL $zero,$zero,0)
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if (out.raw == 0) {
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out.mnemonic = "NOP";
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}
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return out;
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}
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// ---------------------------------------------------------------------------
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// Decode all instructions in a PS1 executable
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// ---------------------------------------------------------------------------
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std::vector<DecodedInstruction> MipsDecoder::decode_executable(
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const PS1Executable& exe)
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{
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std::vector<DecodedInstruction> result;
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const uint32_t word_count = exe.code_size() / 4;
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result.reserve(word_count);
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for (uint32_t addr = exe.load_address(); addr < exe.end_address(); addr += 4) {
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auto word = exe.read_word(addr);
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if (!word.has_value()) break;
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result.push_back(decode(*word, addr));
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}
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return result;
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}
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} // namespace PSXRecomp
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