mirror of
https://github.com/RetroPortingToolKit/psxrecomp
synced 2026-10-26 02:11:36 -04:00
Matthew Stanley
9ae534dc42
Replace the placeholder region cost (RAM +3 / everything-else +0) in psx_cyc_readmem with the full Beetle MemRW device-region read-wait table (libretro.cpp), size-aware: main RAM (<0x800000) +3 SPU 0x1F801C00-1FFF +36 (32-bit) / +16 (8/16-bit) CDC 0x1F801800-180F +6 * size GPU/MDEC/SysCtrl/FIO/SIO/IRQ/DMA/Timers (0x1F801000-113F) +1 BIOS ROM / Expansion-PIO / unmatched / scratchpad +0 Thread the access size (1/2/4) from psx_cyc_load_word/half/byte and psx_cyc_lwc2_read into psx_cyc_readmem (SPU/CDC waits are width-dependent). The device wait combines with the existing +2 completion (+1 LWC2) and fudge exactly as Beetle ReadMemory (LDAbsorb = region + completion). Runtime-only: psx_cyc_load_* signatures unchanged, no emitter regen. New ruler #2 loops mmio_timer (Timer0 read -> +3) and mmio_spu (32-bit SPU read -> +38) added to gen_testrom.py. Validated: cyctest compiled (4600) == Beetle (4382) EXACT on all 15 loops incl. mmio_timer +3 / mmio_spu +38; the 13 prior loops unchanged; Tomba 2 boots past the BIOS to its SCEA-Presents intro splash, no freeze. Documented residual: DMACycleSteal (dynamic per-read DMA bus-steal) remains unmodeled — needs the live steal count from the DMA controller; not statically rulerable. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>