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https://github.com/RetroPortingToolKit/psxrecomp
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Matthew Stanley
d8c4a8ec9f
Implements the last unmodeled load-path cycle component — the R3000A load-delay pipeline interlock (Beetle ReadAbsorb/ReadFudge/LDAbsorb/ LDWhich) — as ONE shared per-instruction model across the dirty interp and BOTH static emitters, replacing the flat per-instruction +1 base and the flat +4 main-RAM read wait-state. Model (transcribed from beetle-psx cpu.cpp + libretro.cpp, verified Δ): - §1 base: a pending load's per-register give-back (read_absorb) is consumed INSTEAD of charging +1 (pipeline write-back overlap). - GPR_DEPRES: each opcode's src/dst regs end the give-back on use. - DO_LDS: commits the prior load's give-back + ReadFudge. - load ReadMemory: +2 fudge iff the predecessor committed no load; main-RAM region +3 + completion +2 (LWC2 +1) become the LDAbsorb give-back; scratchpad +0. New runtime/include/psx_cyc.h (inline §1/deps/DO_LDS + step) over new CPUState timing fields; psx_cyc_load_*/psx_cyc_lwc2_read in memory.c (region-aware, own the whole load interlock, value via uncharged psx_read_*); psx_cyc_dep_res_mask in psx_instr_cost.h (per-opcode GPR_DEP/RES, gen-time literal). cpu->read_* rewired to uncharged in main.cpp; charge_main_ram_read removed. Wired before each instruction body in code_generator.cpp (game) and full_function_emitter.cpp + strict_translator.cpp (BIOS); loads route through psx_cyc_load_*. Validated against the Beetle oracle: - ruler #2 load2: native +10 -> +11 == Beetle (all other components still exact: alu+1/load+5/div+38/mult+15/gte_rtps+15/gte_nclip+8). - ruler #1 [0x80001C5C->0x80001CA4]: 54 -> 56 == Beetle steady-state (residual 84/77 spikes = I-cache cold refill, the separate P2 axis). - Tomba 2 boots to the intro FMV (pixels on screen, no regression). Follow-up (separate commit): GTE-read (MFC2/CFC2) + MFC0 LDAbsorb give-back, and muldiv-stall give-back consumption — needed for mixed game/FMV faithfulness but do not affect the rulers. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>