mirror of
https://github.com/RetroPortingToolKit/psxrecomp
synced 2026-10-26 02:11:36 -04:00
Matthew Stanley
fba58d76b3
Three interrupt delivery bugs fixed that were blocking shell progression: 1. RFE after handler exit: The exception handler's normal exit path (jmpbuf longjmp at 0xBFC10944) does not execute RFE. In our model the handler returns to psx_check_interrupts, not to the WaitEvent caller. Without RFE, IEc stays 0 forever after the first interrupt. Fix: apply RFE in psx_check_interrupts if IEc is still 0 after the handler returns. 2. GPR save/restore around handler dispatch: The handler's jmpbuf exit restores callee-saved registers from the kernel jmpbuf (intended for a non-local jump to WaitEvent's caller). In our model this corrupts the interrupted code's registers. Fix: save all GPRs before handler dispatch and restore them after, matching real hardware where the interrupted code's registers are preserved via TCB save/restore. 3. VBlank tick gated on !in_exception: The handler runs thousands of block leaders, each calling psx_check_interrupts. Without gating, dispatch_count advances inside the handler, firing new VBlanks that stack up and starve the main code. Fix: only increment dispatch_count and fire VBlank/timer ticks when not in exception handling. 4. DMA IRQ edge-triggered: update_master_irq() was level-triggered, re-asserting i_stat bit 3 on every call while master_flag=1. Combined with no BIOS callback to acknowledge DMA IRQs, this caused an interrupt storm. Fix: edge-detect master_flag 0->1 transition, and suppress DMA completion IRQs entirely since transfers are synchronous. Also adds GPU debug diagnostics: GP0 command counters (nop/fill/draw/ env/copy), draw area/offset in gpu_state, vram_peek debug command. Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
173 lines
5.9 KiB
JSON
173 lines
5.9 KiB
JSON
[
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{
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"address": "0xBFC0233C",
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"raw_word": "0x44801000",
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"reason": "addr=0xBFC0233C raw=0x44801000 opcode=0x11: top-level opcode 0x11 not implemented in Phase 1a"
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{
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"address": "0xBFC33CCC",
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"reason": "addr=0xBFC33CCC raw=0x012A4822 opcode=0x00: SPECIAL funct 0x22 not implemented in Phase 1a strict translator"
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"address": "0xBFC33FBC",
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"raw_word": "0x48C4C000",
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"reason": "addr=0xBFC33FBC raw=0x48C4C000 opcode=0x12: top-level opcode 0x12 not implemented in Phase 1a"
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"address": "0xBFC33FCC",
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"raw_word": "0x48C4D000",
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"reason": "addr=0xBFC33FCC raw=0x48C4D000 opcode=0x12: top-level opcode 0x12 not implemented in Phase 1a"
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"address": "0xBFC33F0C",
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"reason": "addr=0xBFC33F0C raw=0x48C46800 opcode=0x12: top-level opcode 0x12 not implemented in Phase 1a"
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"address": "0xBFC33F2C",
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"address": "0xBFC35B1C",
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"address": "0xBFC35B74",
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"address": "0xBFC33FD8",
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"address": "0xBFC33FE4",
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"reason": "addr=0xBFC33C98 raw=0x4884F000 opcode=0x12: top-level opcode 0x12 not implemented in Phase 1a"
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},
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{
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"address": "0xBFC0233C",
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"raw_word": "0x44801000",
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"reason": "addr=0xBFC0233C raw=0x44801000 opcode=0x11: top-level opcode 0x11 not implemented in Phase 1a"
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},
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{
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"address": "0xBFC3370C",
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"raw_word": "0x48C8E800",
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"reason": "addr=0xBFC3370C raw=0x48C8E800 opcode=0x12: top-level opcode 0x12 not implemented in Phase 1a"
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},
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{
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"address": "0xBFC33C98",
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"raw_word": "0x4884F000",
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"reason": "addr=0xBFC33C98 raw=0x4884F000 opcode=0x12: top-level opcode 0x12 not implemented in Phase 1a"
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},
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{
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"address": "0xBFC33CCC",
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"raw_word": "0x012A4822",
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"reason": "addr=0xBFC33CCC raw=0x012A4822 opcode=0x00: SPECIAL funct 0x22 not implemented in Phase 1a strict translator"
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},
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{
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"address": "0xBFC33F0C",
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"raw_word": "0x48C46800",
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"reason": "addr=0xBFC33F0C raw=0x48C46800 opcode=0x12: top-level opcode 0x12 not implemented in Phase 1a"
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},
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{
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"address": "0xBFC33F2C",
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"raw_word": "0x48C4A800",
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"reason": "addr=0xBFC33F2C raw=0x48C4A800 opcode=0x12: top-level opcode 0x12 not implemented in Phase 1a"
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},
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{
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"address": "0xBFC33FBC",
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"raw_word": "0x48C4C000",
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"reason": "addr=0xBFC33FBC raw=0x48C4C000 opcode=0x12: top-level opcode 0x12 not implemented in Phase 1a"
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},
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{
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"address": "0xBFC33FCC",
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"raw_word": "0x48C4D000",
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"reason": "addr=0xBFC33FCC raw=0x48C4D000 opcode=0x12: top-level opcode 0x12 not implemented in Phase 1a"
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},
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{
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"address": "0xBFC33FD8",
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"raw_word": "0x48C4D800",
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"reason": "addr=0xBFC33FD8 raw=0x48C4D800 opcode=0x12: top-level opcode 0x12 not implemented in Phase 1a"
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},
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{
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"address": "0xBFC33FE4",
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"raw_word": "0x48C4E000",
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"reason": "addr=0xBFC33FE4 raw=0x48C4E000 opcode=0x12: top-level opcode 0x12 not implemented in Phase 1a"
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},
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{
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"address": "0xBFC35AEC",
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"raw_word": "0x48C80000",
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"reason": "addr=0xBFC35AEC raw=0x48C80000 opcode=0x12: top-level opcode 0x12 not implemented in Phase 1a"
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},
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{
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"address": "0xBFC35B1C",
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"raw_word": "0x48C84000",
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"reason": "addr=0xBFC35B1C raw=0x48C84000 opcode=0x12: top-level opcode 0x12 not implemented in Phase 1a"
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},
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{
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"address": "0xBFC35B4C",
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"raw_word": "0x48C88000",
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"reason": "addr=0xBFC35B4C raw=0x48C88000 opcode=0x12: top-level opcode 0x12 not implemented in Phase 1a"
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},
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{
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"address": "0xBFC35B74",
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"raw_word": "0x48C82800",
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"reason": "addr=0xBFC35B74 raw=0x48C82800 opcode=0x12: top-level opcode 0x12 not implemented in Phase 1a"
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},
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{
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"address": "0xBFC36068",
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"raw_word": "0xC8800000",
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"reason": "addr=0xBFC36068 raw=0xC8800000 opcode=0x32: top-level opcode 0x32 not implemented in Phase 1a"
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},
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{
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"address": "0xBFC362D0",
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"raw_word": "0x484D0000",
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"reason": "addr=0xBFC362D0 raw=0x484D0000 opcode=0x12: top-level opcode 0x12 not implemented in Phase 1a"
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},
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{
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"address": "0xBFC36740",
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"raw_word": "0xC8800000",
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"reason": "addr=0xBFC36740 raw=0xC8800000 opcode=0x32: top-level opcode 0x32 not implemented in Phase 1a"
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}
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]
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