mirror of
https://github.com/RetroPortingToolKit/psxrecomp
synced 2026-10-26 18:25:35 -04:00
Matthew Stanley
fba58d76b3
Three interrupt delivery bugs fixed that were blocking shell progression: 1. RFE after handler exit: The exception handler's normal exit path (jmpbuf longjmp at 0xBFC10944) does not execute RFE. In our model the handler returns to psx_check_interrupts, not to the WaitEvent caller. Without RFE, IEc stays 0 forever after the first interrupt. Fix: apply RFE in psx_check_interrupts if IEc is still 0 after the handler returns. 2. GPR save/restore around handler dispatch: The handler's jmpbuf exit restores callee-saved registers from the kernel jmpbuf (intended for a non-local jump to WaitEvent's caller). In our model this corrupts the interrupted code's registers. Fix: save all GPRs before handler dispatch and restore them after, matching real hardware where the interrupted code's registers are preserved via TCB save/restore. 3. VBlank tick gated on !in_exception: The handler runs thousands of block leaders, each calling psx_check_interrupts. Without gating, dispatch_count advances inside the handler, firing new VBlanks that stack up and starve the main code. Fix: only increment dispatch_count and fire VBlank/timer ticks when not in exception handling. 4. DMA IRQ edge-triggered: update_master_irq() was level-triggered, re-asserting i_stat bit 3 on every call while master_flag=1. Combined with no BIOS callback to acknowledge DMA IRQs, this caused an interrupt storm. Fix: edge-detect master_flag 0->1 transition, and suppress DMA completion IRQs entirely since transfers are synchronous. Also adds GPU debug diagnostics: GP0 command counters (nop/fill/draw/ env/copy), draw area/offset in gpu_state, vram_peek debug command. Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
35 lines
740 B
C
35 lines
740 B
C
/* dma.h — PS1 DMA controller simulation (Phase 3).
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*
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* 7 DMA channels:
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* Ch0: MDEC in 0x1F801080
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* Ch1: MDEC out 0x1F801090
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* Ch2: GPU 0x1F8010A0
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* Ch3: CDROM 0x1F8010B0
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* Ch4: SPU 0x1F8010C0
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* Ch5: PIO 0x1F8010D0
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* Ch6: OTC 0x1F8010E0
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*
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* Global:
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* DPCR: 0x1F8010F0 (DMA control — enable bits per channel)
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* DICR: 0x1F8010F4 (DMA interrupt control)
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*/
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#ifndef PSXRECOMP_V4_DMA_H
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#define PSXRECOMP_V4_DMA_H
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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void dma_init(void);
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uint32_t dma_read(uint32_t addr);
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void dma_write(uint32_t addr, uint32_t val);
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#ifdef __cplusplus
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}
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#endif
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#endif /* PSXRECOMP_V4_DMA_H */
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