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Matthew Stanley
fc85d8b34d
The dirty-RAM interpreter charged cycles but emitted no cyc_observe, so interp-executed PCs were not anchorable by cyc_watch — interp-side cycle work (the muldiv + GTE completion-stalls just added) could only be validated by construction, not measured. Add a gated debug_server_cyc_observe(pc) at the top of the interp's per-instruction loop (parity with the compiled emitter's block-leader observe), so any interpreted PC becomes a cyc_watch anchor. Gated #ifndef PSX_NO_DEBUG_TOOLS (zero prod overhead); early-returns when cyc_watch is disarmed. Validated: Tomba2 boots to FMV no-regression (safe over 150M+ interp insns); a live overlay interp loop (0x8010724C) records 10 stable cyc_watch hits at 38 cycles/iter, parity with compiled-PC anchoring. This is the interp-path ruler enabler; a fully isolated single-component interp loop (cyctest dirty-RAM loop) remains TODO — the cyctest harness does not route indirect jumps to the dirty interp (dirty_ram_insns=0 there), so that fixture needs interp-dispatch wiring. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>