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feat(firmware): attribute hardware MMIO peripheral memory regions in native disassembly (#5348)
* feat(firmware): attribute hardware MMIO peripheral memory regions in native disassembly - introduce hardwareMemoryMap domain model supporting standard ARM Cortex-M, RISC-V, MIPS, x86, and ARM64 physical memory region classifications (Code, SRAM, Peripheral MMIO, System Control Space, External Device) - distinguish RAM/ROM and address-space segments from MMIO (isolate ARM External RAM / Device and MIPS kseg0/kseg1 uncached mirrors and boot ROM as non-MMIO) - add hardwarePeripheralAttribution to map analyzed instruction references to hardware peripheral blocks and summarize peripheral register interaction profiles with numerical offset ordering - expand ReaGhidraBridge.java decoder_context to capture ARM TMode execution register alongside MIPS ISA_MODE for native instruction inspection - add focused unit and boundary tests across hardwareMemoryMap.test.ts, hardwarePeripheralAttribution.test.ts, GhidraFunctionValues.test.ts, and ghidraCompactReferencesMcp.test.ts verifying region bounds, MMIO isolation, numerical sorting, 32-bit/64-bit overflow rejection, ARM TMode MCP preservation, and bridge contract bindings - make fake Ghidra installation host platform-aware on Windows in GhidraLanguageOverride.test.ts * test(ghidra): inspect ARM and Thumb context in the Java bridge --------- Co-authored-by: morluto <76467478+morluto@users.noreply.github.com>
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@@ -140,6 +140,13 @@ try {
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address: entry,
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});
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assert.equal(instruction.normalized_result.address, entry);
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assert.ok(Array.isArray(instruction.normalized_result.decoder_context));
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const tmodeContext = instruction.normalized_result.decoder_context.find(
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(ctx) => ctx.register === "TMode",
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);
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assert.ok(tmodeContext !== undefined);
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assert.equal(tmodeContext.source, "ghidra-program-context");
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assert.ok([null, "0", "1"].includes(tmodeContext.value));
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}
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assert.equal(profiles[0], profiles[1]);
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assert.notEqual(profiles[1], profiles[2]);
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