mirror of https://github.com/RPCS3/rpcs3
462 lines
13 KiB
C++
462 lines
13 KiB
C++
#include "stdafx.h"
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#include "FPASM.h"
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#include "Emu/RSX/Program/RSXFragmentProgram.h"
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#include <stack>
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#ifndef _WIN32
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#define sscanf_s sscanf
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#endif
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namespace rsx::assembler
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{
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struct FP_opcode_encoding_t
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{
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FP_opcode op;
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bool exec_if_lt;
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bool exec_if_eq;
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bool exec_if_gt;
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bool set_cond;
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};
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static std::unordered_map<std::string, FP_opcode_encoding_t> s_opcode_lookup
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{
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// Arithmetic
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{ "NOP", { .op = RSX_FP_OPCODE_NOP, .exec_if_lt = true, .exec_if_eq = true, .exec_if_gt = true, .set_cond = false } },
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{ "MOV", { .op = RSX_FP_OPCODE_MOV, .exec_if_lt = true, .exec_if_eq = true, .exec_if_gt = true, .set_cond = false } },
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{ "ADD", { .op = RSX_FP_OPCODE_ADD, .exec_if_lt = true, .exec_if_eq = true, .exec_if_gt = true, .set_cond = false } },
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{ "MAD", { .op = RSX_FP_OPCODE_MAD, .exec_if_lt = true, .exec_if_eq = true, .exec_if_gt = true, .set_cond = false } },
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{ "FMA", { .op = RSX_FP_OPCODE_MAD, .exec_if_lt = true, .exec_if_eq = true, .exec_if_gt = true, .set_cond = false } },
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{ "DP3", { .op = RSX_FP_OPCODE_DP3, .exec_if_lt = true, .exec_if_eq = true, .exec_if_gt = true, .set_cond = false } },
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{ "DP4", { .op = RSX_FP_OPCODE_DP4, .exec_if_lt = true, .exec_if_eq = true, .exec_if_gt = true, .set_cond = false } },
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// Constant load
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{ "SFL", {.op = RSX_FP_OPCODE_SFL, .exec_if_lt = true, .exec_if_eq = true, .exec_if_gt = true, .set_cond = false } },
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{ "STR", {.op = RSX_FP_OPCODE_STR, .exec_if_lt = true, .exec_if_eq = true, .exec_if_gt = true, .set_cond = false } },
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// Pack-unpack operations are great for testing dependencies
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{ "PKH", { .op = RSX_FP_OPCODE_PK2, .exec_if_lt = true, .exec_if_eq = true, .exec_if_gt = true, .set_cond = false } },
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{ "UPH", { .op = RSX_FP_OPCODE_UP2, .exec_if_lt = true, .exec_if_eq = true, .exec_if_gt = true, .set_cond = false } },
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{ "PK16U", { .op = RSX_FP_OPCODE_PK16, .exec_if_lt = true, .exec_if_eq = true, .exec_if_gt = true, .set_cond = false } },
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{ "UP16U", { .op = RSX_FP_OPCODE_UP16, .exec_if_lt = true, .exec_if_eq = true, .exec_if_gt = true, .set_cond = false } },
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{ "PK8U", { .op = RSX_FP_OPCODE_PKB, .exec_if_lt = true, .exec_if_eq = true, .exec_if_gt = true, .set_cond = false } },
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{ "UP8U", { .op = RSX_FP_OPCODE_UPB, .exec_if_lt = true, .exec_if_eq = true, .exec_if_gt = true, .set_cond = false } },
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{ "PK8G", { .op = RSX_FP_OPCODE_PKG, .exec_if_lt = true, .exec_if_eq = true, .exec_if_gt = true, .set_cond = false } },
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{ "UP8G", { .op = RSX_FP_OPCODE_UPG, .exec_if_lt = true, .exec_if_eq = true, .exec_if_gt = true, .set_cond = false } },
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{ "PK8S", { .op = RSX_FP_OPCODE_PK4, .exec_if_lt = true, .exec_if_eq = true, .exec_if_gt = true, .set_cond = false } },
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{ "UP8S", { .op = RSX_FP_OPCODE_UP4, .exec_if_lt = true, .exec_if_eq = true, .exec_if_gt = true, .set_cond = false } },
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// Basic conditionals
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{ "IF.LT", { .op = RSX_FP_OPCODE_IFE, .exec_if_lt = true, .exec_if_eq = false, .exec_if_gt = false, .set_cond = false } },
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{ "IF.LE", { .op = RSX_FP_OPCODE_IFE, .exec_if_lt = true, .exec_if_eq = true, .exec_if_gt = false, .set_cond = false } },
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{ "IF.EQ", { .op = RSX_FP_OPCODE_IFE, .exec_if_lt = false, .exec_if_eq = true, .exec_if_gt = false, .set_cond = false } },
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{ "IF.GE", { .op = RSX_FP_OPCODE_IFE, .exec_if_lt = false, .exec_if_eq = true, .exec_if_gt = true, .set_cond = false } },
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{ "IF.GT", { .op = RSX_FP_OPCODE_IFE, .exec_if_lt = false, .exec_if_eq = false, .exec_if_gt = true, .set_cond = false } },
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{ "SLT", { .op = RSX_FP_OPCODE_SLT, .exec_if_lt = false, .exec_if_eq = false, .exec_if_gt = false, .set_cond = true } },
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{ "SEQ", { .op = RSX_FP_OPCODE_SEQ, .exec_if_lt = false, .exec_if_eq = false, .exec_if_gt = false, .set_cond = true } },
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{ "SGT", { .op = RSX_FP_OPCODE_SGT, .exec_if_lt = false, .exec_if_eq = false, .exec_if_gt = false, .set_cond = true } },
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// TODO: Add more
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};
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Instruction* FPIR::load(const RegisterRef& ref, int operand, Instruction* prev)
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{
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Instruction* target = prev;
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if (!target)
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{
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m_instructions.push_back({});
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target = &m_instructions.back();
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}
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SRC_Common src{ .HEX = target->bytecode[operand + 1] };
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src.reg_type = RSX_FP_REGISTER_TYPE_TEMP;
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src.fp16 = ref.reg.f16 ? 1 : 0;
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src.tmp_reg_index = static_cast<u32>(ref.reg.id);
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src.swizzle_x = 0;
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src.swizzle_y = 1;
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src.swizzle_z = 2;
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src.swizzle_w = 3;
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target->bytecode[operand + 1] = src.HEX;
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return target;
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}
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Instruction* FPIR::load(const std::array<f32, 4>& constants, int operand, Instruction* prev)
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{
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Instruction* target = prev;
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if (!target)
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{
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m_instructions.push_back({});
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target = &m_instructions.back();
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}
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// Unsupported for now
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ensure(target->length == 4, "FPIR cannot encode more than one constant load per instruction");
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SRC_Common src{ .HEX = target->bytecode[operand + 1] };
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src.reg_type = RSX_FP_REGISTER_TYPE_CONSTANT;
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target->bytecode[operand + 1] = src.HEX;
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src.swizzle_x = 0;
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src.swizzle_y = 1;
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src.swizzle_z = 2;
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src.swizzle_w = 3;
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// Embed literal constant
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std::memcpy(&target->bytecode[4], constants.data(), 4 * sizeof(u32));
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target->length = 8;
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return target;
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}
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Instruction* FPIR::store(const RegisterRef& ref, Instruction* prev)
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{
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Instruction* target = prev;
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if (!target)
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{
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m_instructions.push_back({});
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target = &m_instructions.back();
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}
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OPDEST dst{ .HEX = target->bytecode[0] };
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dst.dest_reg = static_cast<u32>(ref.reg.id);
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dst.fp16 = ref.reg.f16 ? 1 : 0;
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dst.write_mask = ref.mask;
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dst.prec = ref.reg.f16 ? RSX_FP_PRECISION_HALF : RSX_FP_PRECISION_REAL;
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target->bytecode[0] = dst.HEX;
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return target;
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}
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void FPIR::mov(const RegisterRef& dst, f32 constant)
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{
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Instruction* inst = store(dst);
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inst = load(std::array<f32, 4>{ constant, constant, constant, constant }, 0);
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inst->opcode = RSX_FP_OPCODE_MOV;
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}
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void FPIR::mov(const RegisterRef& dst, const RegisterRef& src)
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{
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Instruction* inst = store(dst);
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inst = load(src, 0);
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inst->opcode = RSX_FP_OPCODE_MOV;
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}
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void FPIR::add(const RegisterRef& dst, const std::array<f32, 4>& constants)
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{
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Instruction* inst = store(dst);
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inst = load(constants, 0);
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inst->opcode = RSX_FP_OPCODE_ADD;
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}
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void FPIR::add(const RegisterRef& dst, const RegisterRef& src)
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{
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Instruction* inst = store(dst);
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inst = load(src, 0);
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inst->opcode = RSX_FP_OPCODE_ADD;
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}
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const std::vector<Instruction>& FPIR::instructions() const
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{
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return m_instructions;
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}
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std::vector<u32> FPIR::compile() const
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{
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std::vector<u32> result;
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result.reserve(m_instructions.size() * 4);
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for (u32 i = 0; i < m_instructions.size(); ++i)
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{
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const auto& inst = m_instructions[i];
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auto src = reinterpret_cast<const be_t<u16>*>(inst.bytecode);
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for (u32 j = 0; j < inst.length; ++j)
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{
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const u16 low = src[j * 2];
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const u16 hi = src[j * 2 + 1];
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const u32 word = static_cast<u16>(low) | (static_cast<u32>(hi) << 16u);
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result.push_back(word);
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}
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}
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return result;
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}
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FPIR FPIR::from_source(const std::string& asm_)
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{
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std::vector<std::string> instructions = fmt::split(asm_, { "\n", ";" });
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if (instructions.empty())
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{
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return {};
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}
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auto transform_inst = [](const std::string& s)
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{
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std::string result;
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result.reserve(s.size());
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bool literal = false;
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for (auto& c : s)
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{
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if (c == ' ')
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{
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if (!literal && !result.empty() && result.back() != ',')
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{
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result += ','; // Replace token separator space with comma
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}
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continue;
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}
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if (std::isspace(c))
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{
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continue;
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}
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if (!literal && c == '{')
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{
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literal = true;
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}
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if (literal && c == '}')
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{
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literal = false;
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}
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if (c == ',')
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{
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result += (literal ? '|' : ',');
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continue;
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}
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result += c;
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}
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return result;
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};
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auto decode_instruction = [&](const std::string& inst, std::string& op, std::string& dst, std::vector<std::string>& sources)
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{
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const auto i = transform_inst(inst);
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if (i.empty())
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{
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return;
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}
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const auto tokens = fmt::split(i, { "," });
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ensure(!tokens.empty(), "Invalid input");
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op = tokens.front();
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if (tokens.size() > 1)
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{
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dst = tokens[1];
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}
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for (size_t n = 2; n < tokens.size(); ++n)
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{
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sources.push_back(tokens[n]);
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}
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};
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auto get_ref = [](const std::string& reg)
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{
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ensure(reg.length() > 1, "Invalid register specifier");
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const auto parts = fmt::split(reg, { "." });
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ensure(parts.size() > 0 && parts.size() <= 2);
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const auto index = std::stoi(parts[0].substr(1));
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RegisterRef ref
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{
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.reg { .id = index, .f16 = false },
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.mask = 0x0F
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};
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if (parts.size() > 1 && parts[1].length() > 0)
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{
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// FIXME: No swizzles for now, just lane masking
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ref.mask = 0;
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if (parts[1].find("x") != std::string::npos) ref.mask |= (1u << 0);
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if (parts[1].find("y") != std::string::npos) ref.mask |= (1u << 1);
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if (parts[1].find("z") != std::string::npos) ref.mask |= (1u << 2);
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if (parts[1].find("w") != std::string::npos) ref.mask |= (1u << 3);
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}
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if (reg[0] == 'H' || reg[0] == 'h')
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{
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ref.reg.f16 = true;
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}
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return ref;
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};
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auto get_constants = [](const std::string& reg) -> std::array<f32, 4>
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{
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float x, y, z, w;
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if (sscanf_s(reg.c_str(), "#{%f|%f|%f|%f}", &x, &y, &z, &w) == 4)
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{
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return { x, y, z, w };
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}
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if (sscanf_s(reg.c_str(), "#{%f}", &x) == 1)
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{
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return { x, x, x, x };
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}
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fmt::throw_exception("Invalid constant literal");
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};
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auto encode_branch_else = [](Instruction* inst, u32 end)
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{
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SRC1 src1{ .HEX = inst->bytecode[2] };
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src1.else_offset = static_cast<u32>(end);
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inst->bytecode[2] = src1.HEX;
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};
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auto encode_branch_end = [](Instruction *inst, u32 end)
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{
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SRC2 src2 { .HEX = inst->bytecode[3] };
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src2.end_offset = static_cast<u32>(end);
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inst->bytecode[3] = src2.HEX;
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SRC1 src1{ .HEX = inst->bytecode[2] };
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if (!src1.else_offset)
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{
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src1.else_offset = static_cast<u32>(end);
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inst->bytecode[2] = src1.HEX;
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}
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};
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auto encode_opcode = [](const std::string& op, Instruction* inst)
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{
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OPDEST d0 { .HEX = inst->bytecode[0] };
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SRC0 s0 { .HEX = inst->bytecode[1] };
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SRC1 s1 { .HEX = inst->bytecode[2] };
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#define SET_OPCODE(encoding) \
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do { \
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inst->opcode = encoding.op; \
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d0.opcode = encoding.op & 0x3F; \
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s1.opcode_hi = (encoding.op > 0x3F)? 1 : 0; \
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s0.exec_if_eq = encoding.exec_if_eq ? 1 : 0; \
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s0.exec_if_gr = encoding.exec_if_gt ? 1 : 0; \
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s0.exec_if_lt = encoding.exec_if_lt ? 1 : 0; \
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d0.set_cond = encoding.set_cond ? 1 : 0; \
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inst->bytecode[0] = d0.HEX; \
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inst->bytecode[1] = s0.HEX; \
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inst->bytecode[2] = s1.HEX; \
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} while (0)
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const auto found = s_opcode_lookup.find(op);
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if (found == s_opcode_lookup.end())
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{
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fmt::throw_exception("Unhandled instruction '%s'", op);
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}
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SET_OPCODE(found->second);
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#undef SET_OPCODE
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};
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std::string op, dst;
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std::vector<std::string> sources;
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std::stack<size_t> if_ops;
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std::stack<size_t> loop_ops;
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u32 pc = 0;
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FPIR ir{};
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for (const auto& instruction : instructions)
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{
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op.clear();
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dst.clear();
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sources.clear();
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decode_instruction(instruction, op, dst, sources);
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if (op.empty())
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{
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continue;
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}
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if (op.starts_with("IF."))
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{
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if_ops.push(ir.m_instructions.size());
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}
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else if (op == "LOOP")
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{
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loop_ops.push(ir.m_instructions.size());
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}
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else if (op == "ELSE")
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{
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ensure(!if_ops.empty());
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encode_branch_else(&ir.m_instructions[if_ops.top()], pc);
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continue;
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}
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else if (op == "ENDIF")
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{
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ensure(!if_ops.empty());
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encode_branch_end(&ir.m_instructions[if_ops.top()], pc);
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if_ops.pop();
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continue;
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}
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else if (op == "ENDLOOP")
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{
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ensure(!loop_ops.empty());
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encode_branch_end(&ir.m_instructions[loop_ops.top()], pc);
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loop_ops.pop();
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continue;
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}
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ir.m_instructions.push_back({});
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Instruction* target = &ir.m_instructions.back();
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pc += 4;
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encode_opcode(op, target);
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ensure(sources.size() == FP::get_operand_count(static_cast<FP_opcode>(target->opcode)), "Invalid operand count for opcode");
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if (dst.empty())
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{
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OPDEST dst{ .HEX = target->bytecode[0] };
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dst.no_dest = 1;
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target->bytecode[0] = dst.HEX;
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}
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else
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{
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ir.store(get_ref(dst), target);
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}
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int operand = 0;
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bool has_literal = false;
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for (const auto& source : sources)
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{
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if (source.front() == '#')
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{
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const auto literal = get_constants(source);
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ir.load(literal, operand++, target);
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has_literal = true;
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continue;
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}
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ir.load(get_ref(source), operand++, target);
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}
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if (has_literal)
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{
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pc += 4;
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}
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}
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if (!ir.m_instructions.empty())
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{
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OPDEST d0{ .HEX = ir.m_instructions.back().bytecode[0] };
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d0.end = 1;
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ir.m_instructions.back().bytecode[0] = d0.HEX;
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}
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return ir;
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}
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}
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